Overall Block Diagram - Panasonic DVCPRO50 Service Manual

OVERALL BLOCK DIAGRAM

V_IN C.B.A. (OPTION)
COMPOSITE
Y/C
VIDEO IN
SEP
INPUT
A/D
Y
SEL
COMPONENT
VIDEO IN PB
PR
SDI IN
SD SDI
S/P
DECORDER
SDI OUT
SDI C.B.A.(1/2)
AES/EBU IN
(CH12)
BUF
AES/EBU IN
(CH34)
ADDA C.B.A.(1/2)
ANALOG
IMP LEVEL REC
AUDIO IN AMP
SEL
SEL V.R
(CH1-4)
(SW)
ANALOG
M
LEVEL
AUDIO OUT MUT U
AMP
SEL
T
(CH1-4)
AUDIO
MONITOR Lch
PB
LEVEL
MUT
AMP
AUDIO
SEL V.R
MONITOR Rch
AMP
HEAD
MUT
PHONES V.R
AES/EBU OUT
(CH12)
DRIVER
AES/EBU OUT
(CH34)
1
SD SDI
with EDH
P/S
ENCORDER
2
SDI OUT
3
CHRA
P/S
GEN
(SUPER) without EDH
REF IN SYNC GEN
SYNC SEP
PLL
Y
COMPONENT
PB
VIDEO OUT
PR
DIGITAL
1 ENCORDER
COMPOSITE 2
CHRA
VIDEO OUT
3
ADD
(SUPER)
EEPROM
FPGA
VIDEO_EE_THRU
EVR
A PROC C.B.A.
INT
REC
SG
V.R
REC
V.R
AES DECORDER
PHASE CONV
& &
(INPUT SEL) DELAY
REF PCM
A/D
LV
CNT
(NSTD)
EE THRU
PB
VOL
PB
SEL
DELAY
METER
DE- REF PB FADE
D/A
LV
EMPH SEL MUTE
PCM
CNT
M
DE- REF
D/A VR
U
LV MONI
EMPH
T
SEL
CUE
METER
PHASE
AES
CONV.
DELAY
ENCORDER (NSTD)
SDI C.B.A.(2/2)
INTER-
PROCESS
FPGA
POLATION
AMP
FIFO
TBC
REC
&
INT SG PREPRO50
REC REC RecOutDat
SEL
DELAY
VITC,C.C
&
MIX
PCM
CNT
CUE SEL CueOutDat
&
MIX
PB
PREPRO50
SMP RATE
SLOW
CONV.
or
BYPASS
PHASE
(PLAY)
CONV.
PB
V.R
CUE MIX DATA
V_OUT C.B.A.
DECORDER
Y/C
&
SEP
Edge Comb
Y/C SEP
VIDEO_EE_THRU
REC REC
REC
VBLK
COMP100 ECC100
DV_PROC
(FPGA)
VIDEO
DATA
PB
PB
ECC100
VBLK
PB
COMP100
AMP
EQ
ATF
EQ AMP
ATF
AMP
EQ
ATF
AMP
EQ
ATF
MODE
CONTROL
REC CONTROL
SW
EVR
AMP
HSW SELECT
EQ C.B.A.
RF/CUE C.B.A.
ATT
CUE MET DATA
NR
A/D
MUT
D/A
ADDA C.B.A.(2/2)
PBL2 PBR2
FE4
FE3
RPR2
RPL2
PBR1 PBL1
REC_PB C.B.A.
RF_PROC
(FPGA)
REC
AMP
RPL1
HEAD
AMP
RPL2
REC
AMP
RPR1
HEAD
AMP
RPR2
PBL1
HEAD
AMP
PBL2
PBR1
HEAD
AMP PBR2
MODE
CONTROL
REC
RE1
CONTROL
RE2
RE
RE
DRI-
AMP
RE3
VER
RE4
CUE R/P
HEAD
PB AMP R/P
HSW
REC AMP
CUE ERASE
HEAD
CUE
BIAS OSC
CUE/CTL
ERASE
CTL ERASE
HEAD
Head Width
RPL1
R/P 18 m
RPR1
PB 24 m
FE1
FE 21 m
FE2