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8.1
EUB-5500 Basic Unit
8.1.1
PRB PCB (PRBSW)
No.
Signal Name
1
SNSRT
2
AS1
3
AS2
4
5VUS
5
DBF̲PRB̲D
6
PRB̲LCK
7
PRB̲DBF̲D
8
PRB̲CK
9
TRDIV̲N
10 TRDIV̲P
11 BCLK̲N
12 BCLK̲P
13 PRB̲YSYNC̲N
14 PRB̲YSYNC̲P
15 CWEN̲N
16 CWEN̲P
17 FPGARESET*
18 SYSRESET*
19 PRBCONFDONE
20 AD̲SPARE*
21 AD̲SNSRT*
22 AD̲ADJUST̲RET*
23 AD̲ST4V*
24 AD̲MP5V*
Section 8 Signal List
Terminal No.
IN/OUT
28C
OUT
28B
OUT
28A
OUT
28D
OUT
13C
IN
14D
IN
13E
OUT
13A
IN
15A
IN
16A
IN
15E
IN
16E
IN
15C
IN
16C
IN
17D
IN
18D
IN
17B
IN
18A
IN
18C
OUT
23E
OUT
24B
OUT
24D
OUT
25A
OUT
25C
OUT
From/To
PRB‑26C
AWP‑26B
AWP‑26A
AWP‑26D
DBF‑113D
DBF‑111D
DBF‑114D
DBF‑112D
DBF‑108E
DBF‑107E
DBF‑110E
DBF‑109E
CNF4‑29
CNF4‑31
DBF‑112E
DBF‑111E
CNF2‑73
CNF2‑75
CNF2‑31
AWP‑21E
AWP‑22B
AWP‑22D
AWP‑23A
AWP‑23C
8 - 1
Description
Voltage level of temperature
detection for MPTEE
Voltage level of angle
detection for MPTEE
Voltage level of angle
detection for MPTEE
+5V supply for MPTEE
DBF to PRBSW serial data
PRBSW I/O latch clock.
PRBSW to DBF serial data.
PRBSW I/O serial clock.
Trans/Receive switch control
(LVDS Negative Pole).
Trans /Receive switch control
(LVDS Positive Pole).
128ns PRBSW clock (LVDS Negative
Pole). This stops at reception
timing.
128ns PRBSW clock (LVDS Positive
Pole).
Y‑SYNC* (LVDS Negative Pole).
Y‑SYNC* (LVDS Positive Pole).
Steering CW mode
(LVDS Negative Pole)
Steering CW mode
(LVDS Positive Pole)
FPGA Reset for PRBSW.
System Reset signal
FPGA Configuration signal
Select signal for AD converter
input. Auto‑gain Control for
MINI‑probe is selected
Select signal for AD converter
input. Voltage level of
temperature detection for MPTEE
is selected.
Select signal for AD converter
input. Auto‑gain Control for
ATGC PTGC is selected
Select signal for AD converter
input. ADC ref Voltage is
selected.
Select signal for AD converter
input. MPTEE supply voltage is
selected.
L1E-EA0229
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