Page 1 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2 Page ii Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Issue Date: 98/10/08...
Page 3 Vancouver Design Center CUSTOMER SUPPORT INFORMATION Comprehensive Support Tools Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of imbedded graphics systems. Evaluation / Demonstration Board •...
Page 4 Page iv Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Issue Date: 98/10/08...
Page 5 Epson Research and Development Page v Vancouver Design Center TABLE OF CONTENTS INTRODUCTION SED1352 Graphics LCD Controller Data Sheet SPECIFICATION SED1352 Hardware Functional Specification PROGRAMMER’S REFERENCE SED1352 Programming Notes and Examples UTILITIES 1352SHOW.EXE Display Utility VIRTUAL.EXE Display Utility BIOS1352.COM Utility 1352GRAY.EXE Display Utility...
Page 6 Page vi Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Issue Date: 98/10/08...
Page 7 DESCRIPTION The SED1352 is a graphics display LCD controller capable of displaying a maximum of 16 levels of gray on single and dual scan Liquid Crystal Displays. A 16x4 lookup table is provided to allow remapping of the 16 possible gray shades displayed on the LCD panel.
Page 8 GRAPHICS SED1352 INTERFACE OPTIONS Interface with 16-Bit MC68xxx MPU and 16Kbytes SRAM (2 of 8K x 8) MC68xxx SED1352 A20 to A23 Decoder MEMCS# FC0 to FC1 A16.. A14 VD8-15 VD0-7 IOCS# Decoder VWE# A10 to A19 A1 to A19...
Page 9 GRAPHICS SED1352 Interface with 16-Bit 8086 MPU and 64Kbytes SRAM (2 of 32K x 8) 8086 (Maximum mode) SED1352 8288 MEMR# MRDC# VD0-7 MEMW# AMWC# READY READY VWE# IOR# IORC# RESET# RESET# IOW# AIOWC# 8284A DT/R 256 Kbit A16 to A19...
Page 10 GRAPHICS SED1352 Interface with 16-Bit ISA Bus and 128Kbytes SRAM (1 of 128K x 8) 16-bit ISA Bus SED1352 REFRESH SA16.. SA14 MEMCS# Decoder MEMW# SMEMW# VWE# MEMR# SMEMR# READY IOCHRDY DB0 to DB15 SD0 to SD15 1 Mbit AB0 to AB19...
Page 11 GRAPHICS SED1352 BLOCK DIAGRAM Control Registers IOR#, IOW#, IOCS#, MEMCS#, MEMR#, MEMW#, BHE#, AB[19:0] Port Decoder Sequence Signal LCDENB Controller Translation Memory UD[3:0] Look-Up Decoder LD[3:0] Table Panel READY LP, YD, Interface XSCL Data Bus Address DB[15:0] Conversion Generator Display...
Page 12 GRAPHICS SED1352 FUNCTIONAL BLOCK DESCRIPTIONS Bus Signal Translation Data Bus Conversion According to configuration setting VD2, Bus Signal Trans- According to configuration setting VD0, the Data Bus lation translates MC68000 type CPU signals, or READY Conversion maps the external data bus, either 8-bit or 16- type MPU signals, to internal bus interface signals.
Page 13 GRAPHICS SED1352 DC SPECIFICATIONS Absolute Maximum Ratings Symbol Parameter Rating Units - 0.3 to + 6.5 Supply Voltage - 0.3 to V + 0.3 Input Voltage - 0.3 to V + 0.3 Output Voltage ° C -65 to 150 Storage Temperature °...
Page 14 GRAPHICS SED1352 Output Specifications Symbol Parameter Condition Units Low Level Output Voltage = 6 mA Type 2 - TS2, CO2, TS2D2 (5.0V) + 0.4 = 12 mA Type 3 - TS3 = 24 mA Type 4 - TS4, CO4 Low Level Output Voltage...
Page 15 GRAPHICS SED1352 SED1352 PIN OUTS XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# VA10 MEMR# READY SED1352F0B BHE# OSC1 OSC2 RESET AB19 X16B-C-001-06...
Page 16 GRAPHICS SED1352 XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# VA10 READY SED1352F1B BHE# OSC1 OSC2 RESET AB19 AB18 AB17 X16B-C-001-06...
Page 17 GRAPHICS SED1352 Dummy Pad XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# VA10 MEMR# SED1352D0B READY BHE# OSC1 OSC2 RESET AB19 AB18 AB17 Dummy Pad Chip Size 4.400 mm x 4.400 mm Chip Thickness 0.400 mm Pad Size 0.090 mm x 0.090 mm Pad Pitch 0.140 mm (Min.)
Page 18 GRAPHICS SED1352 PAD Coordinates Pad Center Pad Center Coordinate Coordinate Name Name -1.850 -2.071 2.071 -0.140 -1.670 -2.071 2.071 0.000 DB10 -1.496 -2.071 2.071 0.140 DB11 -1.330 -2.071 VA10 2.071 0.281 DB12 -1.168 -2.071 2.071 0.423 DB13 -1.012 -2.071 2.071 0.566...
Page 19 GRAPHICS SED1352 Pad Center Pad Center Coordinate Coordinate Name Name -1.496 2.071 BHE# -2.071 0.000 -1.670 2.071 OSC1 -2.071 -0.140 -2.021 2.071 OSC2 -2.071 -0.281 -2.071 1.850 -2.071 -0.423 -2.071 1.670 -2.071 -0.566 XSCL -2.071 1.496 -2.071 -0.712 LCDENB -2.071 1.330...
Page 20 GRAPHICS SED1352 PIN DESCRIPTION = Analog = Input = Output I/O = Bidirectional = Power Bus Interface F1B Pin # Pin Name Type F0B Pin # D0B Pad Description 94 - 100, 1, 91 - 98, These pins are connected to the system data bus. In 8-bit bus mode, DB8-DB15...
Page 21 GRAPHICS SED1352 Display Memory Interface F1B Pin # Pin Name Type F0B Pin # D0B Pad Description These pins are connected to the display memory data bus. For 16-bit interface, VD0-VD7 are connected to the display memory data bus of even byte addresses...
Page 22 GRAPHICS SED1352 Clock Inputs F1B Pin # Pin Name Type F0B Pin # D0B Pad Description This pin, along with OSC2 is the 2-terminal crystal interface when using a OSC1 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin is the clock input.
Page 23 GRAPHICS SED1352 Example: If an ISA bus (no byte swap) with memory segment “A” and I/O location 300h are used, the corresponding settings of VD15-VD0 would be: 8-Bit ISA Bus 16-Bit ISA Bus Index Index Pin Name Direct Mapping Direct Mapping...
Page 24 GRAPHICS SED1352 Illustrated below is the display data which is output from the UD0 to UD3 signal pins and the corresponding display on various panels: UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 Dual Panel - Top...
Page 25 GRAPHICS SED1352 MONOCHROME PASSIVE STN LCD PANEL INTERFACE 4-BIT SINGLE PANEL LP : 240 PULSES L P : 4 P UL S E S U D [3:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 239 LINE 240 LINE 1...
Page 26 GRAPHICS SED1352 MONOCHROME PASSIVE STN LCD PANEL INTERFACE 8-BIT SINGLE PANEL LP : 480 PU LSE S L P : 4 P U L S E S U D [3:0], LD [3:0] L I N E 1 L I N E 2...
Page 27 GRAPHICS SED1352 MONOCHROME PASSIVE STN LCD PANEL INTERFACE 8-BIT DUAL PANEL L P : 2 P U L S E S LP : 240 PULSES U D [3:0], LD [3:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480...
Page 28 GRAPHICS SED1352 PACKAGE DIMENSIONS QFP5-100PIN-S2 Unit: mm (SED1352) ± 0.04 23.2 ± 0.1 20.0 Index ± 0.1 ± 0.1 0.65 0.30 0~12° ± 0.1 Actual Size X16B-C-001-06...
Page 29 GRAPHICS SED1352 QFP15-100PIN-STD Unit: mm (SED1352F1B) ± 0.4 16.0 ± 0.1 14.0 Index ± 0.1 0.168 0~10° ± 0.2 Actual Size X16B-C-001-06...
Page 30 Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Ep- son/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current.
Page 31 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 32 Epson Research and Development Page 2 Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Hardware Functional Specification X16-SP-001-16 Issue Date: 99/07/28...
Page 33: Table Of Contents
Epson Research and Development Page 3 Vancouver Design Center Table of Contents INTRODUCTION ........9 Scope .
Page 34 Epson Research and Development Page 4 Vancouver Design Center Display Memory Interface Timing ......37 7.3.1 Write Data to Display Memory ....... . 37 7.3.2 Read Data From Display Memory .
Page 35 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 4-1: SED1352D0A Pad Coordinates ........20 Table 5-1: Bus Interface .
Page 36 Epson Research and Development Page 6 Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Hardware Functional Specification X16-SP-001-16 Issue Date: 99/07/28...
Page 37 Epson Research and Development Page 7 Vancouver Design Center List of Figures Figure 1: 16-Bit 68000 Series ......... . . 12 Figure 2: 8-Bit Mode, Example: Z80 .
Page 38 Epson Research and Development Page 8 Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Hardware Functional Specification X16-SP-001-16 Issue Date: 99/07/28...
Page 39: Introduction
The SED1352 offers a flexible microprocessor interface. The SED1352 is capable of displaying a maximum of 16 levels of gray. A 16x4 Look-Up Table is provided to allow remapping of the 16 possible gray shades displayed on the LCD panel. The SED1352 can interface to an MC68000 family microprocessor or an 8/16-bit MPU/Bus with minimum external “glue”...
Page 40: Features
Epson Research and Development Page 10 Vancouver Design Center 2 FEATURES 2.1 Technology • low power CMOS • 2.7 to 5.5 volt operation • QFP5-100pin-S2 and QFP15-100 surface mount package 2.2 System • maximum 25MHz input clock (or pixel clock) •...
Page 41: Display Support
Epson Research and Development Page 11 Vancouver Design Center 2.4 Display Support • example resolutions: • 640x480 with 4 grays • 640x400 with 16 grays • passive monochrome LCD panels: • 4-bit single (4-bit data transfer) • 8-bit single (8-bit data transfer) •...
Page 42: Typical System Block Diagrams
Vancouver Design Center 3 TYPICAL SYSTEM BLOCK DIAGRAMS The following figures show typical system implementations of the SED1352. All of the following block diagrams are shown without SRAM or LCD display. Refer to interface specific Application Notes for complete details (X16-AN-xxx-xx).
Page 43: Mpu With Ready (Or Wait#) Signal
Epson Research and Development Page 13 Vancouver Design Center 3.1.1 MPU with READY (or WAIT#) signal Decoder SED1352 MEMCS# MREQ# A10 to A15 Decoder IOCS# IORQ# AB0 to AB15 A0 to A15 D0 to D7 DB0 to DB7 WAIT# READY...
Page 44: Isa Bus
Epson Research and Development Page 14 Vancouver Design Center 3.1.2 ISA Bus 8-Bit ISA Bus SED1352 REFRESH SA16 to SA13 MEMCS# Decoder MEMW# SMEMW# MEMR# SMEMR# READY IOCHRDY DB0 to DB7 SD0 to SD7 AB0 to AB19 SA0 to SA19...
Page 45: Internal Block Diagram
Epson Research and Development Page 15 Vancouver Design Center 3.2 Internal Block Diagram Control Registers IOR#, IOW#, IOCS#, MEMCS#, MEMR#, MEMW#, BHE#, AB[19:0] Port Decoder Sequence Signal LCDENB Controller Translation Memory Look-Up UD[3:0] Decoder Table LD[3:0] Panel READY LP, YD,...
Page 46: Look-Up Table
Epson Research and Development Page 16 Vancouver Design Center 3.3.5 Look-Up Table The Look-Up Table contains sixteen 4-bit wide palettes that can be configured as one 16x4 palette, or four 4x4 palettes used for the re-mapping of gray-scale outputs. See “Look-Up Table Architecture” on page 54.
Page 47: Pinout Diagram
Epson Research and Development Page 17 Vancouver Design Center 4 PINOUT DIAGRAM XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# VA10 MEMR# READY SED1352F0B BHE# OSC1 OSC2 RESET AB19 Figure 7: SED1352F0B Pinout Diagram Note Package type: surface mount QFP5-100pin-S2.
Page 48: Figure 8: Sed1352F1B Pinout Diagram
Epson Research and Development Page 18 Vancouver Design Center XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# VA10 READY SED1352F1B BHE# OSC1 OSC2 RESET AB19 AB18 AB17 Figure 8: SED1352F1B Pinout Diagram Note Package type: surface mount QFP15-100pin. SED1352...
Page 49: Figure 9: Sed1352D0B Pad Diagram
Epson Research and Development Page 19 Vancouver Design Center Dummy Pad XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# VA10 MEMR# READY BHE# OSC1 OSC2 RESET AB19 AB18 AB17 Dummy Pad Chip Size 4.00 mm x 4.00 mm Chip Thickness 0.400 mm...
Page 50: Table 4-1: Sed1352D0A Pad Coordinates
Epson Research and Development Page 20 Vancouver Design Center Table 4-1: SED1352D0A Pad Coordinates Pad Center Pad Center Coordinate Coordinate Name Name -1.850 -2.071 2.071 -0.140 -1.670 -2.071 2.071 0.000 DB10 -1.496 -2.071 2.071 0.140 DB11 -1.330 -2.071 VA10 2.071 0.281...
Page 51 Epson Research and Development Page 21 Vancouver Design Center Table 4-1: SED1352D0A Pad Coordinates (Continued) Pad Center Pad Center Coordinate Coordinate Name Name -1.496 2.071 BHE# -2.071 0.000 -1.670 2.071 OSC1 -2.071 -0.140 -2.021 2.071 OSC2 -2.071 -0.281 -2.071 1.850 -2.071...
Page 52: Pinout Description
Epson Research and Development Page 22 Vancouver Design Center 5 PINOUT DESCRIPTION Key: Input Output Bidirectional (Input/Output) Power pin CMOS level output driver, x denotes driver type (see Table 6-4, “Output Specifications,” on page 27) Tri-state CMOS level output driver, x denotes driver type (see Table 6-4, “Output Specifications,” on...
Page 53: Table 5-2: Display Memory Interface
Epson Research and Development Page 23 Vancouver Design Center Table 5-1: Bus Interface (Continued) F1B/D0B Pin Name Type F0B Pin # Driver Description Pin/Pad # Active low input to read data from the display memory. This pin MEMR# TTLS should be tied to V in an MC68000 MPU interface.
Page 54: Table 5-3: Lcd Interface
Epson Research and Development Page 24 Vancouver Design Center Table 5-3: LCD Interface FPDI-1 F1B/D0B Pin Name Type F0B Pin # Driver Description Pin Name Pin/Pad # Upper panel display data for dual panel mode. For single panel mode, these bits are the most significant 4...
Page 55: Table 5-6: Summary Of Power On / Reset Options
5.1 Summary of Configuration Options The SED1352 requires some configuration information on power-up. This information is provided through the SRAM data lines VD[0...15]. The state of these pins are read on the falling edge of RESET and used to configure the following options:...
Page 56: Table 6-1: Absolute Maximum Ratings
Epson Research and Development Page 26 Vancouver Design Center 6 D.C. CHARACTERISTICS Table 6-1: Absolute Maximum Ratings Symbol Parameter Rating Units - 0.3 to + 6.5 Supply Voltage - 0.3 to V + 0.3 Input Voltage - 0.3 to V + 0.3...
Page 57: Table 6-4: Output Specifications
Epson Research and Development Page 27 Vancouver Design Center Table 6-3: Input Specifications Symbol Parameter Condition Units Input Pin Capacitance = 5.0V kΩ Pull Down Resistance = 3.3V kΩ Pull Down Resistance = 3.0V kΩ Pull Down Resistance Table 6-4: Output Specifications...
Page 58: Table 7-1: Iow# Timing (68000)
Epson Research and Development Page 28 Vancouver Design Center 7 A.C. CHARACTERISTICS Conditions: V = 3.0V ± 10%, 3.3V ± 10% or V = 5.0V ± 10% = -40 °C to 85 °C and T for all inputs must be < 5 nsec (10% ~ 90%)
Page 59: Table 7-2: Ior# Timing (68000)
Epson Research and Development Page 29 Vancouver Design Center IOR# Timing AB[9:1] VALID IOCS# UDS#/LDS# INVALID R/W# Hi-Z Hi-Z DTACK# Hi-Z Hi-Z DB[15:0] VALID Figure 11: IOR# Timing (68000) Table 7-2: IOR# Timing (68000) 3V/3.3V Symbol Parameter Max Min Units...
Page 60: Table 7-3: Memw# Timing (68000)
Epson Research and Development Page 30 Vancouver Design Center MEMW# Timing AB[19:1] VALID MEMCS# UDS#/LDS# INVALID R/W# Hi-Z Hi-Z DTACK# Hi-Z Hi-Z DB[15:0] VALID Figure 12: MEMW# Timing (68000) Table 7-3: MEMW# Timing (68000) 3V/3.3V Symbol Parameter Units AB[19:1] and MEMCS# valid before AS# falling edge AB[19:1] and MEMCS# hold from AS# rising edge 3.5 *...
Page 61: Table 7-4: Memr# Timing (68000)
Epson Research and Development Page 31 Vancouver Design Center MEMR# Timing AB[19:1] VALID MEMCS# UDS#/LDS# INVALID R/W# Hi-Z Hi-Z DTACK# Hi-Z Hi-Z DB[15:0] VALID Figure 13: MEMR# Timing (68000) Table 7-4: MEMR# Timing (68000) 3V/3.3V Symbol Parameter Min Typ Units...
Page 62: Non-68000, Mpu/Bus With Ready (Or Wait#) Signal
Epson Research and Development Page 32 Vancouver Design Center 7.1.2 Non-68000, MPU/Bus With READY (or WAIT#) Signal IOW# Timing AB[9:0] VALID BHE# IOCS# IOW# Hi-Z Hi-Z DB[15:0] VALID Figure 14: IOW# Timing (Non-68000) Table 7-5: IOW# Timing (Non-68000) 3V/3.3V Symbol...
Page 63: Table 7-6: Ior# Timing (Non-68000)
Epson Research and Development Page 33 Vancouver Design Center IOR# Timing AB[9:0] VALID BHE# IOCS# IOR# Hi-Z Hi-Z DB[15:0] VALID Figure 15: IOR# Timing (Non-68000) Table 7-6: IOR# Timing (Non-68000) 3V/3.3V Symbol Parameter Max Min Units AB[9:0], BHE# and IOCS# valid before IOR# falling...
Page 64: Table 7-7: Memw# Timing (Non-68000)
Epson Research and Development Page 34 Vancouver Design Center MEMW# Timing AB[19:0] VALID BHE# MEMCS# MEMW# Hi-Z Hi-Z READY Hi-Z Hi-Z DB[15:0] VALID Figure 16: MEMW# Timing (Non-68000) Table 7-7: MEMW# Timing (Non-68000) 3V/3.3V Unit Symbol Parameter AB[19:0], BHE# and MEMCS# valid before MEMW#...
Page 65: Table 7-8: Memr# Timing (Non-68000)
Epson Research and Development Page 35 Vancouver Design Center MEMR# Timing AB[19:0] VALID BHE# MEMCS# MEMR# Hi-Z Hi-Z READY Hi-Z Hi-Z DB[15:0] VALID Figure 17: MEMR# Timing (Non-68000) Table 7-8: MEMR# Timing (Non-68000) 3V/3.3V Symbol Parameter Min Typ Min Typ...
Page 66: Clock Input Requirements
The crystal oscillator must be “fundamental mode” and have the following recommended RC load values: = 2MΩ ± 5% = 6.8 pF The figure below demonstrates both a crystal interface and an oscillator interface to the SED1352. Crystal Interface Oscillator Interface...
Page 67: Display Memory Interface Timing
Epson Research and Development Page 37 Vancouver Design Center 7.3 Display Memory Interface Timing 7.3.1 Write Data to Display Memory VA[15:0] VALID VSC0#, VSC1# VWE# VOE# Hi-Z Hi-Z Hi-Z Hi-Z VD[15:0] INPUT OUTPUT INPUT Figure 20: Write Data to Display Memory Table 7-10: Write Data to Display Memory 3V/3.3V...
Page 68: Read Data From Display Memory
Epson Research and Development Page 38 Vancouver Design Center 7.3.2 Read Data From Display Memory VA[15:0] VALID VSC0#, VSC1# INPUT INPUT VD[15:0] INPUT Figure 21: Read Data From Display Memory Table 7-11: Read Data From Display Memory 3V/3.3V Symbol Parameter...
Page 69: Lcd Interface Timing
Epson Research and Development Page 39 Vancouver Design Center 7.4 LCD Interface Timing SED1352 outputs SED1352 outputs (AUX[01h] bit 5 = 0) XSCL UD[3:0] LD[3:0] SED1352 outputs (AUX[01h] bit 5 = 1) t6b, t6c XSCL UD[3:0] LD[3:0] Figure 22: LCD Interface Timing...
Page 70: 4-Bit Single Lcd Interface Timing
Epson Research and Development Page 40 Vancouver Design Center 7.4.1 4-Bit Single LCD Interface Timing Table 7-12: 4-Bit Single LCD Interface Timing Symbol Parameter Units HT - 24 LP period - 24 YD hold from LP negated (R1 bit 5 = 0)
Page 71: 8-Bit Lcd Interface Timing
Epson Research and Development Page 41 Vancouver Design Center 7.4.2 8-Bit LCD Interface Timing Table 7-13: 8-Bit LCD Interface Timing Symbol Parameter Units HT - 24 LP period (single panel mode) 2*HT - 24 LP period (dual panel mode) - 24...
Page 72: Figure 23: Lcd Interface Pixel/Data Position
Epson Research and Development Page 42 Vancouver Design Center LCD Interface Pixel/Data Position UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 Dual Panel - Top 8-bit Single Panel LD3 LD2 LD1 LD0 Dual Panel - Bottom...
Page 73: Figure 24: 4-Bit Single Monochrome Panel Timing
Epson Research and Development Page 43 Vancouver Design Center LP : 2 4 0 P ULS E S L P : 4 P U L S E S U D [3 :0 ] LINE 1 LINE 2 LINE 3 LINE 4...
Page 74: Figure 25: 8-Bit Single Monochrome Panel Timing
Epson Research and Development Page 44 Vancouver Design Center L P : 4 P U L S E S LP : 4 8 0 P U LS E S U D [3 :0 ], LD [3 :0 ] L I N E 1...
Page 75: Figure 26: 8-Bit Dual Monochrome Panel Timing
Epson Research and Development Page 45 Vancouver Design Center L P : 2 P U L S E S LP : 2 4 0 P U LS E S U D [3 :0 ], LD [3 :0 ] LINE 1/24 1...
Page 76: Hardware Register Interface
Vancouver Design Center 8 HARDWARE REGISTER INTERFACE The SED1352 is configured and controlled via 15 internal 8-bit registers. There are two ways to map these registers into the system I/O space. Direct-mapping: Absolute I/O address = system address lines AB[3:0] + base I/O mapped address...
Page 77 Epson Research and Development Page 47 Vancouver Design Center AUX[01h] Mode Register I/O address = 0001b, Read/Write. Mask LCD Data Memory DISP Panel LCDE Gray Scale RAMS XSCL Width Interface bit 7 DISP This bit selects display on or off. When this bit = 0, Display OFF is selected (LD0-3 and UD0-3 are forced to 0).
Page 78: Table 8-1: Maximum Value Of Line Byte Count Register - 8-Bit Display Memory Interface
Epson Research and Development Page 48 Vancouver Design Center AUX[02h] Line Byte Count Register (LSB) I/O address = 0010b, Read/Write. Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Count Bit 7 Count Bit 6...
Page 79: Table 8-3: Power Save Mode Selection
Epson Research and Development Page 49 Vancouver Design Center Table 8-3: Power Save Mode Selection Mode Activated Normal Operation Power Save Mode 1 Power Save Mode 2 Reserved Refer to Power Save Modes (PSM 1) on page 55 for a complete Power Save Mode description.
Page 80 Epson Research and Development Page 50 Vancouver Design Center AUX[05h] Total Display Line Count Register (MSB) and WF Count Register I/O address = 0101b, Read/Write Total Total WF Count WF Count WF Count WF Count WF Count WF Count Display...
Page 81 Epson Research and Development Page 51 Vancouver Design Center AUX[08h] Screen 2 Display Start Address Register (LSB) I/O address = 1000b, Read/Write. Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Display Display...
Page 82 Epson Research and Development Page 52 Vancouver Design Center AUX[0Ah] Screen 1 Display Line Count Register (LSB) I/O address = 1010b, Read/Write. Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Display Display...
Page 83: Table 8-4: Id Bit Usage
Bit 1 Bit 0 The SED1352 has one internal 16 position, 4-bit wide Look-Up Table (palette). The 4-bit value programmed into each table position determines the output gray shade/weighting of display data. The Look-Up Table can be arranged in two different configurations. Refer to Table 27, “4-Level Gray-Shade Mode Look- Up Table Architecture,”...
Page 84: Look-Up Table Architecture
Epson Research and Development Page 54 Vancouver Design Center AUX[0Fh] Look-Up Table Data Register I/O address = 1111b, Read/Write. Palette Data Palette Data Palette Data Palette Data Bit 3 Bit 2 Bit 1 Bit 0 bits 3-0 Palette Data Bits [3:0] These 4-bits are the gray shade values used for display data output.
Page 85: 16-Level Gray Shade Mode
8.3.1 Power Save Mode 1 (PSM1) Power Save Mode 1 has two states. Initially when set, the SED1352 enters State 1. If no valid memory cycle is detected within 1, 2, or 4 clocks (input clock frequency dependent), the chip will enter State 2. The number of clocks of inactivity before entering State 2 is dependent on the display memory interface and the number of gray shades.
Page 86: Power Save Mode 2 (Psm2)
Epson Research and Development Page 56 Vancouver Design Center 8.3.2 Power Save Mode 2 (PSM2) • I/O read/write of all registers allowed • Memory read/write is disabled • Master clock for display memory access is disabled • LCD outputs are either forced low (AUX[03h] bit 5=0), or high impedance (AUX[03h] bit 5=1) •...
Page 87: Display Memory Interface
Epson Research and Development Page 57 Vancouver Design Center 9 DISPLAY MEMORY INTERFACE 9.1 SRAM Configurations Supported 9.1.1 8-Bit Mode VD0-7 VWE# 8Kx8 SED1352 VCS0# VCS1# VA0-12 Figure 29: 8-Bit Mode - 8K bytes SRAM VD0-7 VWE# 8Kx8 8Kx8 SED1352...
Page 88: Figure 31: 8-Bit Mode - 32K Bytes Sram
Epson Research and Development Page 58 Vancouver Design Center VD0-7 VWE# 32Kx8 SED1352 VCS0# VCS1# VA0-14 Figure 31: 8-Bit Mode - 32K bytes SRAM (Requires AUX[01h] bit 0 = 1) VD0-7 VWE# 8K/32Kx8 32K/8Kx8 SED1352 VCS0# VCS1# VA0-14 Figure 32: 8-Bit Mode - 40K bytes SRAM...
Page 89: 16-Bit Mode
Epson Research and Development Page 59 Vancouver Design Center VD0-7 VWE# 32Kx8 32Kx8 SED1352 VCS0# VCS1# VA0-14 Figure 33: 8-Bit Mode - 64K bytes SRAM (Requires AUX[01h] bit 0 = 1) 9.1.2 16-Bit Mode VD0-7 VWE# 8Kx8 SED1352 VCS0# VA0-12...
Page 90: Figure 35: 16-Bit Mode - 64K Bytes Sram
Epson Research and Development Page 60 Vancouver Design Center VD0-7 VWE# 32Kx8 SED1352 VCS0# VA0-14 VCS1# 32Kx8 VD8-15 Figure 35: 16-Bit Mode - 64K bytes SRAM VWE# SED1352 64Kx16 VCS0# VCS1# VA0-15 A0-15 VD0-7 I/O 1-8 VD8-15 I/O 9-16 Figure 36: 16-Bit Mode - 128K bytes SRAM...
Page 91: Sram Access Time
Epson Research and Development Page 61 Vancouver Design Center 9.2 SRAM Access Time 9.2.1 8-Bit Display Memory Interface: Table 9-1: 8-Bit Display Memory Interface SRAM Access Time Display Mode 3V/3.3V 16-level gray shades Access time < 1 / f - 50ns Access time <...
Page 92: Memory Size Requirement
350 ns 370 ns 150 ns 170 ns (1) Memory more than 128KB cannot be supported by SED1352. (2) Memory more than 64KB can only be supported through 16-bit display memory interface. * KB = K byte = 1024 bytes SED1352...
Page 93: Table 9-4: Memory Size Requirement: Number Of Horizontal Pixels = 480
770 ns 350 ns 370 ns (1) Memory more than 128KB cannot be supported by SED1352. (2) Memory more than 64KB can only be supported through 16-bit display memory interface. * KB = K byte = 1024 bytes Hardware Functional Specification...
Page 94: Mechanical Data
Epson Research and Development Page 64 Vancouver Design Center 10 MECHANICAL DATA ± 0.04 23.2 ± 0.1 20.0 Index ± 0.1 ± 0.1 0.65 0.30 0~12° ± 0.1 All dimensions in mm Figure 37: Mechanical Drawing QFP5-100pin-S2 SED1352 Hardware Functional Specification...
Page 95: Figure 38: Mechanical Drawing Qfp15-100Pin
Epson Research and Development Page 65 Vancouver Design Center ± 0.4 16.0 ± 0.1 14.0 Index ± 0.1 0.168 0~10° ± 0.2 All dimensions in mm Figure 38: Mechanical Drawing QFP15-100pin Hardware Functional Specification SED1352 Issue Date: 99/07/28 X16-SP-001-16...
Page 96 Epson Research and Development Page 66 Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Hardware Functional Specification X16-SP-001-16 Issue Date: 99/07/28...
Page 97 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 98 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Programming Notes and Examples X16-BG-007-04 Issue Date: 98/10/08...
Page 99 INTRODUCTION ........7 INITIALIZING THE SED1352 ......8 GRAY SHADES AND LOOK-UP TABLES .
Page 100 Vancouver Design Center PROGRAMMING THE SED1352 ......46 Main Loop Code ....... 47 Initialization Code .
Page 101 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3-1: SED1352F0B Black-To-White Look-Up Table for 16 Gray Shades ....17 Table 3-2: SED1352F0B Inverted Look-Up Table (White-To-Black) ..... 18 Table 3-3: SED1352F0B Black-To-White Look-Up Table for 4 Gray Shades .
Page 102 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Programming Notes and Examples X16-BG-007-04 Issue Date: 98/10/08...
Page 103: Introduction
1 INTRODUCTION The purpose of this guide is to demonstrate how to program the SED1352 LCD controller, with reference made to the SDU1352B0x evaluation board. The first half of this guide presents the basic concepts of LCD controllers, which describe the following: •...
Page 104: Initializing The Sed1352
Vancouver Design Center 2 INITIALIZING THE SED1352 This section presents two examples to show how to initialize the SED1352 registers and write a pixel to the display. Code to initialize the SED1352 is provided in Section 6.2, “Initialization Code” on page 48.
Page 105 Epson Research and Development Page 9 Vancouver Design Center Data Notes See Also Register (in Binary) • bits 7-0 = bits 7-0 of Screen 1 Display Start Address (application specific) see Section 4.2.1, • bits 15-8 of Screen 1 Display Start Address in AUX[07h] “SDU1352B0x...
Page 106 Page 10 Epson Research and Development Vancouver Design Center Data Notes See Also Register (in Binary) AUX[0Fh] 0000 0100 write monochrome LUT data AUX[0Eh] 0000 0101 increment palette address AUX[0Fh] 0000 0101 write monochrome LUT data AUX[0Eh] 0000 0110 increment palette address...
Page 107 – Example 2: Initialize the registers for a 4 gray shade 640x480 dual panel LCD with 128k of display memory. Afterwards write one pixel to the top left corner of the display. Program SED1352 Registers 00h-0Dh: Data Notes See Also...
Page 108 Page 12 Epson Research and Development Vancouver Design Center Data Notes See Also Register (in Binary) • bits 7-0 = bits 7-0 of Screen 1 Display Start Address (application specific) see Section 4.2.1, • bits 15-8 of Screen 1 Display Start Address in AUX[07h] “SDU1352B0x...
Page 109 Epson Research and Development Page 13 Vancouver Design Center Data Notes See Also Register (in Binary) AUX[0Eh] 0000 0100 increment palette address AUX[0Fh] 0000 0000 write monochrome LUT data AUX[0Eh] 0000 0101 increment palette address AUX[0Fh] 0000 0101 write monochrome LUT data...
Page 110 Page 14 Epson Research and Development Vancouver Design Center Note  Panel Width in Pixels  1 × Line Byte Count ------------------------------------------------------------------------------------------- - bits per pixel (2 or 4 bits) –   Memory Interface Width (8 or 16 bits) ...
Page 111: Gray Shades And Look-Up Tables
(00b, 01b, 10b, or 11b). Similarly, four bits allow 16 different combina- tions of gray shades (0000b, 0001b, 0010b, ... 1111b). The SED1352 can be programmed to use either two bit or four bit pixels. The following sections show how these pixels are stored in display memory.
Page 112: Look-Up Table (Lut)
Bit 1 Bit 0 The SED1352 has one internal 16 position, 4-bit wide Look-Up Table (palette). The 4-bit value programmed into each table position determines the output gray shade of display data. For example, in 16-level gray shade mode, a data value of 0001h (4 bits per pixel) will point to Look-Up Table positions one and display the 4-bit gray shade that was previously programmed into that location.
Page 113: Look-Up Table Description
The SED1352 supports two different data formats; 4 bits-per-pixel (16 gray shades) and 2 bits-per-pixel (4 gray shades). In 4 bits-per-pixel mode the SED1352 provides a 16 position, 4 bit wide LUT. In 2 bits-per-pixel mode, the SED1352 provides 4 “banks” of 4 position, 4 bit wide LUTs.
Page 114 This example shows how to invert an image by changing only the LUT. Inverting means that pixels formally shown as light gray shades are now shown as dark gray shades, and vise versa. It does not matter whether the SED1352 is in 4 gray shade or 16 gray shade mode.
Page 115: Four Gray Shades (Two Bits/Pixel)
3.2.3 Four Gray Shades (Two Bits/Pixel) When the SED1352 is configured for two bit pixels, each pixel can index one of four LUT entries. In this 4 gray shade mode, the SED1352 treats the 16 entries in the LUT as four separate look-up tables or banks, each having four entries (see Figure 3).
Page 116 Page 20 Epson Research and Development Vancouver Design Center 4 LUTs of 4 Entries x 4 Bits b3 b2 b1 b0 Index Palette 0 Bank Bits Palette 1 Display Data (2 Bits/Pixel) Output Value to Gray Scale Engine Palette 2...
Page 117: Sixteen Gray Shades (Four Bits/Pixel)
Vancouver Design Center 3.2.4 Sixteen Gray Shades (Four Bits/Pixel) When the SED1352 has 4 bit pixels, each pixel can index into one of 16 LUT entries. The LUT bank bits are ignored in this mode. 1 LUT of 16 Entries x 4 Bits...
Page 118: Display Memory Models
Page 22 Epson Research and Development Vancouver Design Center 4 DISPLAY MEMORY MODELS This section introduces display memory models. A concise description of the Display Start Address Registers is provided, followed by a description of display memory. Afterwards examples are provided, illustrating how to calculate the display memory model for a given display resolution and gray level mode.
Page 119 Epson Research and Development Page 23 Vancouver Design Center AUX[08] Screen 2 Display Start Address Register (LSB) I/O address = 1000b, Read/Write. Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Display Display...
Page 120: Description
• Although the SED1352 can set the Memory Interface to 8 or 16 bits, the SDU1352B0x evaluation board should be set up for 16 bits. As a result, the Display Start Address Registers are word pointers, not byte pointers. To illustrate how to use a word pointer, refer to Example 6.
Page 121: Display Start Address Registers
The technique shown, however, can also be used to calculate the memory map of other resolutions. In addition, reference is made to the SDU1352B0x evaluation board; other hardware implementations of the SED1352 may assign different display and port addresses from those of the SDU1352B0x. Refer to the SDU1352B0x Evaluation Board User’s Manual for more information on these hardware issues.
Page 122 Compare the required number of bytes with the amount of memory available to the SED1352. • If the SED1352 has 128k available, there is 131,072 bytes available, which is greater than the 76,800 bytes re- quired for 640 x 480 with 4 gray shades.
Page 123: Common Display Memory Requirements For Lcd Panel Sizes
The following is a list of memory requirements and memory maps for common LCD resolutions. Note that the memory required for 640x480 with 16 gray shades exceeds 128k and is therefore not supported on the SED1352. Table 4-1: Memory Size Requirements...
Page 124: Advanced Techniques
5 ADVANCED TECHNIQUES This section presents information on the following: • virtual displays • bitmaps and text displays • reading and writing to the SED1352 registers • split screen displays • panning and scrolling. • power saving. 5.1 Virtual Displays This section presents a detailed description of the Address Pitch Adjustment Register, followed by a description of a virtual display.
Page 125: Description
5.1.2 Description The SED1352 can be programmed to use memory offsets in such a way that the physical display behaves as a viewport into a much larger “virtual” memory space. This viewport can be panned and/or scrolled to display this larger memory space.
Page 126: Bitmaps And Text Displays
Page 30 Epson Research and Development Vancouver Design Center 5.2 Bitmaps and Text Displays For the scope of this guide, a bitmap is a data structure which represents the image shown on the LCD. The bitmap includes the dimensions of the image, and the gray shade palette used to program the look-up table. Text is shown by creating a font, which in this example is a series of bitmaps, one bitmap per alphanumeric character.
Page 127 Epson Research and Development Page 31 Vancouver Design Center Offset Offset (hex) (hex) 0000 000F F F F F F F 0 0 F F F F F F F 0 F F 0 0 0 F F 0 F F F F F F 0 0...
Page 128: Registers
Epson Research and Development Vancouver Design Center 5.3 Registers The SED1352 has an internal set of sixteen 8-bit read/write registers which configure it for various modes of operation. The registers can be accessed in two ways: Indexed Addressing and Direct Addressing. Note Refer to the SED1352 Hardware Functional Specification and SDU1352B0x Evaluation Board User’s...
Page 129 Epson Research and Development Page 33 Vancouver Design Center Example 13: Write 12h to register 08h on the SDU1352B0x evaluation board; the base port address is 310h, and direct port mapping is used. Calculate the port address for register 08h.
Page 130: Split Screen
Page 34 Epson Research and Development Vancouver Design Center 5.4 Split Screen This section describes how to create a split screen for both single and dual LCD panels. For single panel displays, the Screen 1 Display Line Count Registers are used. For dual panel displays, the Screen 2 Display Start Address Registers are used.
Page 131: Description
A split screen is generally considered as the presentation of two different images on the screen. Image 1 is shown on the top half and image 2 is shown on the bottom half of the screen. Due to the design the SED1352, the system is always in split screen mode.
Page 132 Page 36 Epson Research and Development Vancouver Design Center Calculate the total number of bytes required for image 1. × × bytes per scan line number of scan lines for image 1 160 240 38400 bytes 9600h bytes Determine the display memory location for image 2.
Page 133 Epson Research and Development Page 37 Vancouver Design Center • If the line count is set to 99, then the first 100 scan lines of image 1 are shown, following by the first part of im- age 2 (see Figure 12).
Page 134: Dual Panel Lcd
Page 38 Epson Research and Development Vancouver Design Center 5.4.4 Dual Panel LCD The following is the procedure to show a split screen image on a 4 gray shade 640x480 dual panel LCD. For this example the SDU1352B0x is used; the Memory Interface is set to 16 bits, and 128k of display memory is available. In addition, the two images shown on the split screen are each 640x240.
Page 135 Notes When using a dual panel, the Screen 1 Display Line Count Register is ignored by the SED1352. Once the two Display Start Address Registers are programmed, the top panel will show the beginning of image 1, and the bottom panel will show the beginning of image 2 (see Figure 13).
Page 136 Page 40 Epson Research and Development Vancouver Design Center 5.4.4.1 Displaying a Single Image on a Dual Panel The following is the procedure to show a single image on a dual panel LCD. In this procedure the single image is broken into two smaller images;...
Page 137 Epson Research and Development Page 41 Vancouver Design Center Determine the display memory location for image 2. Place image 2 immediately after image 1 (see Figure 14). Assign the starting address for image 2 as follows: image 2 address base display memory address...
Page 138: Panning And Scrolling
Screen 1 Display Start Address Register. Note that the SED1352 can pan right or left by either 2, 4, or 8 pixels. This is because the Screen 1 Display Start Address Register refers to either bytes or words (see Section 4.2.1, “SDU1352B0x Evaluation Board Display Memory” on page 24), and a byte can represent either 2 or 4 pixels, and so a word can represent 4 or 8 pixels;...
Page 139 Epson Research and Development Page 43 Vancouver Design Center Add the number of words in a virtual scan line to the Screen 1 Display Start Address Register. In this example the Screen 1 Display Start Address points to the beginning of the image.
Page 140: Power Saving
Epson Research and Development Vancouver Design Center 5.6 Power Saving The following section introduces the power saving capabilities of the SED1352. A detailed description of the Power Save Register is provided, followed by a description of the power save modes. 5.6.1 Registers Note Register bits discussed in this section are highlighted.
Page 141 Epson Research and Development Page 45 Vancouver Design Center 5.6.2.3 Power Save Mode Function Summary Table 5-4: Power Save Mode Function Summary Power Save Mode (PSM) Function Normal PSM1 PSM2 (Active) State 1 State 2 Display Active? I/O Access Possible?
Page 142: Programming The Sed1352
6 PROGRAMMING THE SED1352 The purpose of this section is to show how to program the SED1352 exercising the specific capabilities of this chip. A series of functions written in ‘C’ will be presented, each illustrating a basic feature of the SED1352. These functions are written for the SDU1352B0x evaluation board, and are combined under a menu-driven program called DEMO.EXE.
Page 143: Main Loop Code
Epson Research and Development Page 47 Vancouver Design Center 6.1 Main Loop Code //------------------------------------------------------------------------- // FUNCTION: main() // DESCRIPTION: Start of demo program. // INPUTS: Command line arguments. // RETURN VALUE: None. //------------------------------------------------------------------------- void main(char argc, char **argv) int ch;...
Page 144: Initialization Code
Vancouver Design Center 6.2 Initialization Code //------------------------------------------------------------------------- // FUNCTION: Initialize() // DESCRIPTION: Intialize SED1352 registers. // INPUTS: This function looks at the followingl global variables to determine the appropriate register settings: PanelX, PanelY, PanelType // OUTPUTS: The following global variables are changed:...
Page 145 Epson Research and Development Page 49 Vancouver Design Center // Bits 0-7 are in AUX[2], Bit 8 is in AUX[3]. // Because the Memory Interface is set to 16 bits, the // Line Byte/Word Count Register counts in words. In addition, // there are 2 pixels/byte since there are 16 gray levels.
Page 146 // D000:0000 to D000:FFFF. When the SDU1352B0x is set to 128k, video // memory exists from C000:0000 to D000:FFFF. As far as the SED1352 // is concerned, video memory ALWAYS begins at C000:0000, even if // there is no physical memory present.
Page 147 Epson Research and Development Page 51 Vancouver Design Center // Since this demo program uses only 64k, the Display Start Address // Registers must be adjusted to point to the D000 segment. To do so, // note that these registers refer to words of data, not bytes, // since the Memory Interface is set to 16 bits.
Page 148: Advanced Functions
6.3 Advanced Functions #define VIRTUAL_X (360) #define VIRTUAL_Y (360) //------------------------------------------------------------------------- // FUNCTION: ShowRegisters() // DESCRIPTION: Shows the contents of the SED1352 registers. // INPUTS: None. // RETURN VALUE: None. //------------------------------------------------------------------------- void ShowRegisters(void) static unsigned char x; printf("SED1352 Registers: "); for (x = 0; x < 16; ++x) printf("%02X ", ReadRegister(x));...
Page 149 Epson Research and Development Page 53 Vancouver Design Center Initialize(); ClearLCDScreen(); // For 64k only FP_SEG(pVideo) = 0xd000; FP_OFF(pVideo) = 0x0000; // Update Look-Up Table for 16 gray shades for (x = 0; x < 16; ++x) WriteRegister(0x0e, x); WriteRegister(0x0f, x);...
Page 150 Page 54 Epson Research and Development Vancouver Design Center //------------------------------------------------------------------------- // FUNCTION: ShowVerticalBars() // DESCRIPTION: Displays a series of vertical bars, each with a different gray shade. For 4 gray levels, each vertical bar is 40 pixels wide. For 16 gray levels, each vertical bar is 20 pixels wide.
Page 151 Epson Research and Development Page 55 Vancouver Design Center // In the 16 gray level mode, each pixel is stored as four bits. // Since a byte holds 8 bits, there are 2 pixels per byte. // The variable "val" represents the pixel value.
Page 152 Page 56 Epson Research and Development Vancouver Design Center { 0xF8, 0x6C, 0x66, 0x66, 0x66, 0x6C, 0xF8, 0x00 }, // D { 0xFE, 0x62, 0x68, 0x78, 0x68, 0x62, 0xFE, 0x00 }, // E { 0xFE, 0x62, 0x68, 0x78, 0x68, 0x60, 0xF0, 0x00 },...
Page 153 Epson Research and Development Page 57 Vancouver Design Center if (val & 0x80) Display = color << 6; else Display = 0; if (val & 0x40) Display |= (color << 4); if (val & 0x20) Display |= (color << 2);...
Page 154 Page 58 Epson Research and Development Vancouver Design Center if (val & 0x80) Display = color << 4; else Display = 0; if (val & 0x40) Display |= color; *pDisplay++ = (unsigned char) Display; if (val & 0x20) Display = color << 4;...
Page 155 Epson Research and Development Page 59 Vancouver Design Center static unsigned char _far *pVideoImage1; static unsigned char _far *pVideoImage2; static unsigned long ImageSize; static unsigned int OriginalLineCount; static unsigned int val; static unsigned int MinLineCount; static unsigned int MaxVirtualScanLines; Initialize();...
Page 156 Page 60 Epson Research and Development Vancouver Design Center WriteRegister(8, (unsigned int) val & 0xff); WriteRegister(9, (unsigned int) val >> 8); // If this is a dual panel, then the split screen has just been shown. // Otherwise, set up the Screen 1 Display Line Count register for single // panels.
Page 157 Epson Research and Development Page 61 Vancouver Design Center void SetStartAddress(int x, int y) int addr; // Assume 16 gray shades addr = 0x8000 + (x/2 + (VIRTUAL_X/2) * y)/2; WriteRegister(6, addr & 0xff); WriteRegister(7, addr >> 8); void PanScroll(void) static unsigned int x, y;...
Page 158 Page 62 Epson Research and Development Vancouver Design Center for (x = 0; x < 300; ++x) FP_OFF(pVideo) = (unsigned int) ((rand() * 0xffffL) / RAND_MAX); val = rand() % 50; ShowText(pVideo, "!", rand() % 16); ShowBorders(); // Move virtual display from (0, 0) to (MaxX, 0) MaxX = VIRTUAL_X - PanelX;...
Page 159 Epson Research and Development Page 63 Vancouver Design Center //------------------------------------------------------------------------- void PowerSaving(void) static unsigned int val; printf("Starting Power Saving\n"); val = ReadRegister(3); val &= 0x3f; val |= 0x80; WriteRegister(3, val); // Set power saving mode 2 printf("Press any key to cancel power saving\n");...
Page 160 Page 64 Epson Research and Development Vancouver Design Center // Step 2: Wait for LCD power supply to drop to zero volts For the SDU1353B0C, wait about a half second. Delay(500); // Step 3: Enter Power Save Mode val = ReadRegister(3);...
Page 161: Glossary
The up and down movement of the viewport in a virtual display. SED1352 The 1352 chip. SDU1352B0x The evaluation board for the SED1352. The SDU1352B0x is an ISA board for a PC- compatible computer. viewport The visible portion of a virtual display.
Page 162 Page 66 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Programming Notes and Examples X16-BG-007-04 Issue Date: 98/10/08...
Page 163 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 164 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 1352SHOW.EXE Display Utility X16-UI-001-08 Issue Date: 98/10/08...
Page 165 1352SHOW.EXE DISPLAY UTILITY 1352SHOW is an OEM demonstration utility used to load and display GIF images. It can also be used to demonstrate the split screen capabilities of the SED1352 by loading two images and vertically scrolling one image. Program Requirements...
Page 166 Page 4 Epson Research and Development Vancouver Design Center Comments • 1352SHOW requires BIOS1352.COM to be loaded prior to running. • Split screen viewing is only allowed on single panels. • The size of screen two is determined by available memory and number of gray shades. If there is insufficient memory for screen two 1352SHOW will not accept the two image files and will generate an error message.
Page 167 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 168 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 VIRTUAL.EXE Display Utility X16-UI-002-08 Issue Date: 08/10/08...
Page 169 Vancouver Design Center VIRTUAL.EXE DISPLAY UTILITY VIRTUAL.EXE demonstrates the virtual panning capabilities of the SED1352. An image larger than the display resolution is loaded in display memory. VIRTUAL.EXE will then display a portion of the complete image while providing panning capabilities using the arrow keys for navigation.
Page 170 Page 4 Epson Research and Development Vancouver Design Center Program Messages ERROR: This program requires BIOS1352 to be loaded! The program BIOS1352.COM must be run before VIRTUAL.EXE. Load BIOS1352.COM and then re-run VIRTUAL.EXE. ERROR: Insufficient memory for virtual display. The virtual display is too large to fit in memory. Choose a smaller x or y value.
Page 171 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 172 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 BIOS1352.COM Utility X16-UI-003-08 Issue Date: 98/10/08...
Page 173 INT 10h. This program provides text, scroll, and cursor functionality when no VGA BIOS is present. Although the SED1352 is not a VGA or EGA compatible controller, this program is supplied to give the user a familiar prompt. Within limits BIOS1352 simulates a VGA BIOS and will allow standard output functions to work. DOS programs such as Edlin, Format, Debug, and internal commands such as Copy, Ren, Mkdir, etc., should work;...
Page 174 The panel specified is too large to run in 16 gray shades mode. Select 4 gray shades instead. ERROR: Video memory and VGA BIOS memory conflict. Both the SED1352 video memory and the VGA BIOS are trying to use the memory at location C000h to CFFFh. ERROR: Only 8k, 16k, 32k, 40k, 64k or 128k memory allowed.
Page 175 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 176 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 1352GRAY.EXE Display Utility X16-UI-004-08 Issue Date: 98/10/08...
Page 177 1352GRAY.EXE DISPLAY UTILITY 1352GRAY is a menu driven display utility for the SED1352 which demonstrates the gray shades and available palettes. For 128K bytes of display memory and a panel size of 640x400 or less, either 4 or 16 gray shades are available. If the panel size is greater than 640x400 only 4 shades of gray are available.
Page 178 Page 4 Epson Research and Development Vancouver Design Center Comments • 1352GRAY requires BIOS1352.COM to be loaded prior to running. • Four gray shades is always possible. Switching to 16 gray shades may not be possible if the panel size exceeds 640x400.
Page 179 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 180 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 1352PD.EXE Power Down Utility X16-UI-005-07 Issue Date: 98/10/08...
Page 181 Page 3 Vancouver Design Center 1352PD.EXE POWER DOWN UTILITY 1352PD is an OEM utility program for setting power down modes in the SED1352 LCD Display Controller. It provides a simple method for setting power modes during power consumption testing. Program Requirements...
Page 182 Program Messages Power Down Mode xx is set. The power down mode xx has been set. This message may not be visible if the active display controller is the SED1352. ERROR: Cannot set power mode xx! 1352PD.EXE cannot set the power down mode requested . The power down mode must be 0, 1, or 2.
Page 183 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 184 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 1352READ.EXE Diagnostic Utility X16-UI-006-06 Issue Date: 98/10/08...
Page 185 1352READ.EXE DIAGNOSTIC UTILITY 1352READ is an OEM utility program which enables the user to read the SED1352 register contents. It is a useful utility for OEMs wishing to submit a problem report for the video controller. If run with BIOS1352 loaded, it will try to interpret the BIOS settings.
Page 186 WARNING: BIOS1352 state is out of sync with SED1352 registers. One or more of the following command line items reported by BIOS1352 does not match the values found in the SED1352 registers; horizontal panel size, vertical panel size, number of gray shades, or panel type (single or dual).
Page 187 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 188 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 SDU1352B0C Rev. 1.0 Evaluation Board User Manual X16-AN-002-09 Issue Date: 98/10/07...
Page 189 Epson Research and Development Page 3 Vancouver Design Center Table of Contents SDU1352B0C REV 1.0 EVALUATION BOARD ....7 Features ....... . 7 Installation and Configuration .
Page 190 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 SDU1352B0C Rev. 1.0 Evaluation Board User Manual X16-AN-002-09 Issue Date: 98/10/07...
Page 191 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 1-1: Configuration DIP Switch Settings ......8 Table 1-2: I/O Mapping Example .
Page 192 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 SDU1352B0C Rev. 1.0 Evaluation Board User Manual X16-AN-002-09 Issue Date: 98/10/07...
Page 193: Sdu1352B0C Rev 1.0 Evaluation Board
Vancouver Design Center 1 SDU1352B0C REV 1.0 EVALUATION BOARD This manual reflects the use of the SDU1352B0C Rev 1.0 evaluation board in conjunction with the SED1352 LCD Controller. All appropriate components are surface-mount to reduce cost and minimize board space.
Page 194: Installation And Configuration
1.2 Installation and Configuration The SED1352 has 16 configuration inputs (VD[15:0]) which are read on power-up. For the purpose of this design, most of these configuration inputs have been factory set and therefore are not configurable. A four position DIP switch block is provided for the selection of 8- or 16-bit bus interface, and setting I/O address bits 4 through 6.
Page 195 Epson Research and Development Page 9 Vancouver Design Center LCD Signal Connector Pinout Table 1-4: LCD Signal Connector J1 Pinout SED1352 Connector Mono STN LCD Comments Pin No. Pin Name 8-bit 4-bit Lower panel display data for dual panel-dual drive mode.
Page 196 +12V 12 volt supply /SBHE Connected to the BHE# signal of the SED1352 IOCHRDY Connected to the READY signal of the SED1352 /IOSC Connected to the IOCS# signal of the SED1352 /MEMCS Connected to the MEMCS# signal of the SED1352 SED1352 SDU1352B0C Rev.
Page 197 Connected to AB19 of the SED1352 Ground Ground 5 volt supply 5 volt supply /IOW Connected to the IOW# signal of the SED1352 /IOR Connected to the IOR# signal of the SED1352 /SMEMW Connected to the MEMW# signal of the SED1352 /SMEMR Connected to the MEMR# signal of the SED1352 SDU1352B0C Rev.
Page 198: Technical Description
1.3.1 ISA Bus Support This board directly supports the 16-bit and 8-bit ISA Bus with indexing I/O via a standard AT edge connector. External logic has been added to provide signals which the SED1352 does not support directly. See Application Note X16-AN-003-xx.
Page 199: Non-Isa Bus Support
Voltage lines are provided on the header strips. U2, a TIBPAL22V10, is currently used to provide the SED1352 IOCS# (pin 23) and MEMCS# (pin 22) input signals for ISA bus use. This functionality must now be provided externally and these two pins need to disconnected as there may be conflict problems associated with two different outputs driving the same input.
Page 200: Adjustable Lcd Panel Positive Power Supply
Refer to Section 9.3 of the SED1352 Functional Specification, Drawing Office No. X16-SP-001-xx for further details. 1.3.9 CPU/Bus Interface Header Strips All of the CPU/Bus interface pins of SED1352 are connected to the header strips H1 and H2 for easy interface to a CPU/Bus other than the ISA bus.
Page 201: Appendix Aparts List
Epson Research and Development Page 15 Vancouver Design Center Appendix A PARTS LIST Qty/ Item # Designation Part Value Description Board C1, C8-C10, 0.1uF 1206 pckg C14-C42 1.0uF/35V Tantalum .1 spacing radical C3, C4 56uF/35V LXF35VB56RM6X11LL C7, C11 - C13...
Page 202: Appendix Bsdu1352B0C Rev. 1.0 Schematic Diagrams
Page 16 Epson Research and Development Vancouver Design Center Appendix B SDU1352B0C REV. 1.0 SCHEMATIC DIAGRAMS Figure 1: SDU1352B0C Rev. 1.0 Schematic Diagram (1 of 7) SED1352 SDU1352B0C Rev. 1.0 Evaluation Board User Manual X16-AN-002-09 Issue Date: 98/10/07...
Page 203 Epson Research and Development Page 17 Vancouver Design Center Figure 2: SDU1352B0C Rev. 1.0 Schematic Diagram (2 of 7) SDU1352B0C Rev. 1.0 Evaluation Board User Manual SED1352 Issue Date: 98/10/07 X16-AN-002-09...
Page 204 Page 18 Epson Research and Development Vancouver Design Center Figure 3: SDU1352B0C Rev. 1.0 Schematic Diagram (3 of 7) SED1352 SDU1352B0C Rev. 1.0 Evaluation Board User Manual X16-AN-002-09 Issue Date: 98/10/07...
Page 205 Epson Research and Development Page 19 Vancouver Design Center Figure 4: SDU1352B0C Rev. 1.0 Schematic Diagram (4 of 7) SDU1352B0C Rev. 1.0 Evaluation Board User Manual SED1352 Issue Date: 98/10/07 X16-AN-002-09...
Page 206 Page 20 Epson Research and Development Vancouver Design Center Figure 5: SDU1352B0C Rev. 1.0 Schematic Diagram (5 of 7) SED1352 SDU1352B0C Rev. 1.0 Evaluation Board User Manual X16-AN-002-09 Issue Date: 98/10/07...
Page 207 Epson Research and Development Page 21 Vancouver Design Center Figure 6: SDU1352B0C Rev. 1.0 Schematic Diagram (6 of 7) SDU1352B0C Rev. 1.0 Evaluation Board User Manual SED1352 Issue Date: 98/10/07 X16-AN-002-09...
Page 208 Page 22 Epson Research and Development Vancouver Design Center Figure 7: SDU1352B0C Rev. 1.0 Schematic Diagram (7 of 7) SED1352 SDU1352B0C Rev. 1.0 Evaluation Board User Manual X16-AN-002-09 Issue Date: 98/10/07...
Page 209 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 210 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Power Consumption X16-AN-006-06 Issue Date: 98/10/08...
Page 211 Epson Research and Development Page 3 Vancouver Design Center 1 SED1352 POWER CONSUMPTION 1.1 Conditions Pixel clock = 25MHz: screen pattern = 00h and AAh on 640x480 single panel. Pixel clock = 12MHz: screen pattern = 00h and AAh on 480x320 single panel.
Page 212 Page 4 Epson Research and Development Vancouver Design Center SED1352 Power Consumption (V = 3.0V) 25MHz Pixel Clock 12MHz Pixel Clock 6MHz Pixel Clock ACTIVE ACTIVE Pattern 00h Pattern AAh Operating Mode Active Active Units Pattern 00h Pattern AAh 25MHz 35.0...
Page 213 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 214 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352F0B ISA Bus Interface Considerations X16-AN-003-05 Issue Date: 98/10/08...
Page 215 Epson Research and Development Page 3 Vancouver Design Center Table of Contents INTRODUCTION ........5 Reference Material .
Page 216 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352F0B ISA Bus Interface Considerations X16-AN-003-05 Issue Date: 98/10/08...
Page 217: Introduction
Epson Research and Development Page 5 Vancouver Design Center 1 INTRODUCTION The SED1352F0B is a general purpose LCD controller capable of interfacing to a variety of microprocessors. This interface is accomplished through the use of minimal external circuitry. This application note describes the interface between the SED1352F0B and the ISA Bus.
Page 218: 16-Bit Isa Bus Interface
Page 6 Epson Research and Development Vancouver Design Center 2 16-BIT ISA BUS INTERFACE For the purpose of the example shown below, the following conditions are set by default: Indexing I/O with addresses 0310h and 0311h (see Configuration Options) 128Kbytes of display memory occupying $C and $D segments (see Configuration Options)
Page 219: Pal Equations
A0 to A9, therefore minimal external circuitry is necessary to provide signals IOCS# and IOCS16# IOCS# is required by the SED1352 to indicate a valid IO cycle. In an ISA bus environment, valid IO decoding must include addresses A15-A0. Given this example, addresses A10-15 must all be ’0’ and AEN must also be ’0’.
Page 220: 8-Bit Isa Bus Interface
Page 8 Epson Research and Development Vancouver Design Center 3 8-BIT ISA BUS INTERFACE For the purpose of the example shown below, the following conditions are set by default: 1. Indexing I/O with partial decoding, i.e. address lines A10 to A15 are not decoded for I/O cycles Note Partial decoding is quite safe on most ISA Bus systems as I/O addresses above 03FFh are rarely used.
Page 221: Sed1352F0B Default Setup
Epson Research and Development Page 9 Vancouver Design Center 1.5 SED1352F0B Default Setup 1.5.1 Configuration Options VD15 - VD13 = 101 memory decoding for locations $A segment VD12 - VD4 = 110000000 I/O decoding for locations 1100000000b - 1100000001b VD3 = 0...
Page 222 Page 10 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352F0B ISA Bus Interface Considerations X16-AN-003-05 Issue Date: 98/10/08...
Page 223 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 224 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 MC68340 Interface Considerations X16-AN-004-06 Issue Date: 98/10/08...
Page 225 PAL Equations ....... . . 7 SED1352 Default Setup ......7 List of Figures Figure 1: MC68340 MPU Interface Block Diagram .
Page 226 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 MC68340 Interface Considerations X16-AN-004-06 Issue Date: 98/10/08...
Page 227: Introduction
Vancouver Design Center 1 INTRODUCTION The SED1352 is a general purpose LCD controller capable of interfacing to a variety of microprocessors. This interface is accomplished through the use of minimal external circuitry. This application note describes the interface between the SED1352 and the 16-bit MC68340 microcontroller.
Page 228: Mc68340 Mpu Interface
The internal chip select signal CS3 of the MC68340, along with external DSACK1 response, is employed to access the SED1352. Direct mapping of the I/O with starting address at 00000000h, and 128Kbytes of display memory with starting address 00020000h are also used.
Page 229: Pal Equations
SED1352; IOCS# = !(!CS3 & !A17 & !A16 & !A15 & !A14 & !A13 & !A12 & !A11 & !A10) With memory locations from 00020000h to 003FFFFh and A17 to A19 decoded internally to SED1352; MEMCS# = CS3 BHE# becomes valid for two conditions: 1.
Page 230 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 MC68340 Interface Considerations X16-AN-004-06 Issue Date: 98/10/08...
Page 231 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 232 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 LCD Panel Options / Memory Requirements X16-AN-005-07 Issue Date: 98/10/08...
Page 233 Epson Research and Development Page 3 Vancouver Design Center Table of Contents INTRODUCTION ........5 Reference Material .
Page 234 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 LCD Panel Options / Memory Requirements X16-AN-005-07 Issue Date: 98/10/08...
Page 235: Introduction
Vancouver Design Center 1 INTRODUCTION The SED1352 is a highly configurable general purpose LCD controller. The LCD panel frame-rate, resolution, and gray shades all determine the memory and input clock requirements. This application note will describe the equations used to determine the various parameters.
Page 236: Configuration Equations
1. Due to oscillator frequency availability, a 12MHz oscillator is selected thus producing a slightly higher frame-rate (~75Hz). 2. For a detailed description of the frame rate formula, see section 9.3 of the SED1352 Hardware Func- tional Specification, drawing office number X16-SP-001-xx.
Page 237: Sram Access Time
- 50. With 12MHz input clock, access time < 283ns. Note For detail description of the SRAM access time, see section 9.2 of the SED1352 Hardware Functional Spec- ification, drawing office number X16-SP-001-xx. LCD Panel Options / Memory Requirements SED1352...
Page 238: Implementation
Page 8 Epson Research and Development Vancouver Design Center 3 IMPLEMENTATION 3.1 8-Bit Display Memory Interface Since 35.7K bytes with at least 116ns access time SRAM is required, one 8K bytes SRAM with 100ns access time, and one 32K bytes SRAM with 100ns access time are used in this example.
Page 239: Register Settings
Epson Research and Development Page 9 Vancouver Design Center 3.1.2 Register Settings AUX[00h] = 0000 0000 not in test mode AUX[01h] = 1001 0011 4-bit single panel, 4 gray shades, 8-bit display memory interface with 32K bytes is the first chip AUX[02h] = 1001 1111 horizontal resolution = 640 ;...
Page 240: 16-Bit Display Memory Interface
Page 10 Epson Research and Development Vancouver Design Center 3.2 16-bit Display Memory Interface Since 35.7K bytes with at least 283ns access time SRAM is required, two 32K bytes SRAM with 120ns access time are used for this example. 640x240 Panel...
Page 241: Register Settings
Note When LCDENB (bit 4 of AUX[01h]) is used to control the LCD power, the following sequence is recommeded to setup the AUX registers of the SED1352: Write to bit 4 of AUX[01h] with value ’0’. Setup the AUX registers accordingly.
Page 242 Page 12 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 LCD Panel Options / Memory Requirements X16-AN-005-07 Issue Date: 98/10/08...

Epson SED1352 Technical Manual

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