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Epson S1R72105 Technical Manual

Scsi interface controller
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MF1530 - 01
SCSI Interface Controller
S1R72105
Technical Manual

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Summary of Contents for Epson S1R72105

  • Page 1 MF1530 - 01 SCSI Interface Controller S1R72105 Technical Manual...
  • Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products.
  • Page 3 Configuration of product number DEVICES 72105 00A0 Packing specifications 00: Besides tape & reel 0A: TCP BL 2 directions 0B: Tape & reel Back 0C: TCP BR 2 directions 0D: TCP BT 2 directions 0E: TCP BD 2 directions 0F: Tape & reel FRONT 0G: TCP BT 4 directions 0H: TCP BD 4 directions 0J: TCP SL 2 directions...

  • Page 4: Table Of Contents

    7.3.19 USB Index(USBIndex) R/W ..................26 7.3.20 USB Window 0(USBWindow_0) R/W ................26 7.3.21 USB Window 1(USBWindow_1) R/W ................26 7.3.22 USB Window 2(USBWindow_2) R/W ................27 7.3.23 USB Window 3(USBWindow_3) R/W ................27 7.3.24 USB Window 4(USBWindow_4) R/W ................27 7.3.25 USB Window 5(USBWindow_5) R/W ................28 Rev.1.0 EPSON...
  • Page 5 7.5.2.14 EP0 SETUP[n](n=0,1,2,3,4,5,6,7) (EP0SETUP[n]) R .......50 7.5.2.15 Frame Number H(FrameNumber_H) R.............51 7.5.2.16 Frame NumberL(FrameNumber_L) R ............51 7.6 SCSI Control Commands ......................52 7.6.1 Control Commands and Command Codes ..............52 7.6.2 Description of Each Control Command................52 7.6.3 Command Execution and Change of State..............60 EPSON Rev.1.0...
  • Page 6 8.4.3.4 DMA Read (PSLV=0: Master mode) ............84 8.4.4 Others...........................85 8.4.4.1 OSCIN Input Clock ( ex.40MHz)..............85 8.4.4.2 EXCLK Input Clock (48MHz) ...............86 8.4.4.3 XRESET Input Pulse Width .................87 8.4.4.4 USB Interface Access Timing..............87 EXAMPLES OF CONNECTION .....................88 10. EXTERNAL DIMENSIONS DRAWING ..................90 Rev.1.0 EPSON...

  • Page 7: Description

    S1R72105 Technical Manual 1. DESCRIPTION S1R72105 contains the SCSI-3 interface controller and the USB 1.1 controller that support SCAM and FAST20 transfer, which is capable of bridging general-purpose I/O port and IDE DMA port as well as SCSI and USB interfaces.

  • Page 8: Block Diagram

    S1R72105 Technical Manual 3. BLOCK DIAGRAM Port interface section SCSI-3 interface section XSRST XPDREQ Command Master mode control Sequence XSDP XPDACK analysis and control XSATN execution XPRD XSBSY Slave mode control XPWR XSIO Phase FIFO control PD15-0 XSCD (16Byte) XSMSG...

  • Page 9: Pin Assignment

    S1R72105 Technical Manual 4. PIN ASSIGNMENT S1R72105F0A (QFP15-100pin) PD4(9) XSACK PD11(8) PD3(7) XSBSY PD12(6) XSATN PD2(5) EPSO EPSO EPSO EPSON XSDBP PD13(4) PD1(3) XSDB7 PD14(2) PD0(1) XSDB6 PD15(0) S1R72105 XSDB5 PDREQ XPWR XSDB4 XPRD XPDACK XSDB3 TOP View TOP View...

  • Page 10: Pin Description

    S1R72105 Technical Manual 5. PIN DESCRIPTION The control signal with “X” at the head of a pin name is LOW-active. Pin No. Symbol Functional description Remarks SCSI interface-related matters (18) XSDB0 Is/Otr SCSI data signal (SD0 to SD7) Drive capability 48mA...
  • Page 11 S1R72105 Technical Manual Pin No. Symbol Functional description Remarks CPU interface-related matters (19) Address input pin (AD0 to AD5) Data pin (DB0 to DB7) Drive capability 3mA Chip select signal for accessing internal register XINTU USB interrupt request output signal...

  • Page 12: Functional Description

    S1R72105 Technical Manual 6. FUNCTIONAL DESCRIPTION 6.1 CPU Interface Circuit This block can be interfaced to a general-purpose CPU. It generally controls the interface with the CPU. When the XCS signal from the CPU is LOW, the block can access the internal register. It decodes the address bus AD5 to AD0 to generate the address of the internal register.

  • Page 13: Usb Interface Circuit

    S1R72105 Technical Manual 6.6 USB Interface Circuit (1) It supports full speed device in conformity to the USB1.1 (It does not support low speed). It supports control transfer (endpoint 0), bulk transfer, and interrupt transfer (It does not support isochronous transfer).
  • Page 14 S1R72105 Technical Manual Depending on the usage, set the control signal as shown below: - When an oscillator circuit (20MHz) is - When an oscillator circuit (40MHz) is used used - When a 20 MHz clock of 3.3V level is - When a 40 MHz clock of 3.3V level is...

  • Page 15: Function Of Registers

    S1R72105 Technical Manual 7. FUNCTION OF REGISTERS 7.1 List of Registers Address Register name Abbreviated name Main Interrupt Status MainIntStat Epr Interrupt Status EPrIntStat Interrupt Status Window_0 IntStatWindow_0 Interrupt Status Window_1 IntStatWindow_1 Main Interrupt Enable MainIntEnb Epr Interrupt Enable EPrIntEnb...
  • Page 16 S1R72105 Technical Manual Address Register name Abbreviated name Main Interrupt Status SCSI MAININTS SCSI Interrupt status 1 SCSIINT1 SCSI Interrupt status 2 SCSIINT2 - Reserved - - Reserved - - Reserved - - Reserved - - Reserved - - Reserved -...

  • Page 17: List Of Register/Window Settings (Usb)

    S1R72105 Technical Manual 7.1.1 List of Register/Window Settings (USB) • Details appearing in IntStatWindow_0(02h) IntIndex(08h) 4 higher Function of IntStatWindow_0 order bits Description on display register (bit7,6,5,4) EP0IntStat Endpoint 0 status display/clear EPaIntStat Endpoint a status display/clear EPbIntStat Endpoint b status display/clear...
  • Page 18 S1R72105 Technical Manual • Details appearing in USBWindow_0(18h) to USBWindow_0(1Fh) USBIndex(17h) Register name Description on display USBWindow_0(18h) USBAddress: USB address USBWindow_1(19h) EP0Config_1：EP0 configuration USBWindow_2(1Ah) EP0InControl: EP0 IN Transaction control USBWindow_3(1Bh) EP0OutControl: EP0 OUT Transaction control USBWindow_4(1Ch) (Reserved) USBWindow_5(1Dh) EP0FIFOremain: EP0 FIFO counter...

  • Page 19: List Of Registers/Bits

    S1R72105 Technical Manual 7.2 List of Registers/Bits Default Address Type Register name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Detect RcvEP0 EPrlnt Port SCSI MainIntStat 40/00h resume reset suspend SETUP Stat DMACmp EPclnt EPblnt EPalnt EP0lnt EPrIntStat Stat...
  • Page 20 S1R72105 Technical Manual Default Address Type Register name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value MAININTS GOOD SABT EXEC SCSI1 SCSI2 DTCMP ASCMP SCSIINT1 SPERR IDERR SELTO SATN BFREE ILPHS SCSEL WOATN SCSIINT2 SRST OFERR UNDEF CMDER RESEL...

  • Page 21: List Of Registers/Bits/List Of Window Configuration(Usb) List Of Bits

    S1R72105 Technical Manual 7.2.1 List of Registers/Bits/List of Window Configuration(USB) List of Bits • Details appearing in IntStatWindow_0(02h) IntIndex(08h) IntStatWindow_0 Higher order Functions of Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 4 bits register (BIT7,6,5,4) EP0IntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv...
  • Page 22 S1R72105 Technical Manual • Details appearing in USBWindow_0(18h) to USBWindow_0(1Fh) Function of USBIndex(17h) Register name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 register USBWindow_0 USBAddress (MSB) USB Address [6:0] (LSB) (18h) USBWindow_1 EP0Config_1 OUTxIN MaxPacketSize[3:0] (19h) USBWindow_2 INForce InForce...

  • Page 23: Detailed Description Of Each Register

    S1R72105 Technical Manual 7.3 Detailed Description of Each Register 7.3.1 Main Interrupt Status (MainIntStat) R/W When the IC interrupts the CPU, the CPU identifies the interrupt status register responsible for interruption by reading this register first. Following the reading of this register, the CPU identifies the bit as a source of interruption and clears it by writing the value read after appropriate interrupt processing.

  • Page 24: Epr Interrupt Status(Eprintstat) R/W

    S1R72105 Technical Manual 7.3.2 EPr Interrupt Status(EPrIntStat) R/W The factor responsible for endpoint interrupt status can be identified by reading this register. When all factors of endpoint-by-endpoint interruption (interrupt factors at the main source) shown by each bit are cleared, the relevant bit is cleared.

  • Page 25: Interrupt Status Window 1(Intstatwindow_1) R/W

    S1R72105 Technical Manual 7.3.4 Interrupt Status Window 1(IntStatWindow_1) R/W The endpoint interrupt status register appears. The interrupt status to be displayed changes according to the value set at IntIndex_1 of the IntIndex register (08h). For set value of the IntIndex register, refer to section “7.4 Detailed Description of Set Values of IntIndex Register.”...

  • Page 26: Interrupt Enable Window 0(Intenbwindow_0) R/W

    S1R72105 Technical Manual 7.3.7 Interrupt Enable Window 0 (IntEnbWindow_0) R/W The register enabling/disabling endpoint interruption appears. The interrupt status to be displayed changes according to the value set at IntIndex_0 of the IntIndex register (08h). For set value of the IntIndex register, refer to section “7.4 Detailed Description of Set Values of IntIndex Register.”...

  • Page 27: System Control(Systemctrl) R/W

    S1R72105 Technical Manual 7.3.10 System Control(SystemCtrl) R/W Sets the system operation. Address Register Name Bit Symbol Description SystemCtrl 7: 0 Reserved 6: 0 Reserved 5: 0 Reserved 4: GoSuspend Go Suspend 3: SendWakeup Send Wakeup 2: 0 Reserved 1: xINTmode 1...

  • Page 28: Reset(Reset) R/W

    S1R72105 Technical Manual 7.3.12 Reset (Reset) R/W Resets internal LSI. Each block is reset by writing HIGH to the corresponding bit. Has the same effect as hard reset. Automatically returns to LOW. Address Register Name Bit Symbol Description Reset 7: 0...

  • Page 29: Port Dma Size High(Portdmasize_H) R/W

    S1R72105 Technical Manual 7.3.14 Port DMA Size High (PortDMASize_H) R/W Sets the most significant byte of the byte-length (3 bytes) for port DMA transfer. Address Register Name Bit Symbol Description PortDMASize_H 7: PortDMASize[23] 6: PortDMASize[22] 5: PortDMASize[21] 4: PortDMASize[20] Port DMA Size High...

  • Page 30: Port Config 0 (Portconfig_0) R/W

    S1R72105 Technical Manual 7.3.17 Port Config 0 (PortConfig_0) R/W Sets the operation mode of the IC. Address Register Name Bit Symbol Description PortConfig_0 7:ActivePort Active Port 6: BUSC Bus Configuration 5:PortSlave Port Slave Reserved 3:PDREQlevel PDREQ level 2:Swap Swap Port Interface Bus...

  • Page 31: Port Config 1(Portconfig_1) R/W

    S1R72105 Technical Manual * Operation settings of the port interface The following list shows the operational settings made by the bit setting: Selecting master/slave of the port by PSLV bit PDREQ XPDACK XPRD/XPWR Remarks PSLV=0 Input Output Output Data input during XPRD...

  • Page 32: Usb Index(Usbindex) R/W

    S1R72105 Technical Manual 7.3.19 USB Index (USBIndex) R/W Set registers to be displayed in USBWindow_0 to USBWindow_7. For details of display by set values of the USBIndex register, refer to section “7.5 Detailed Description of Set Values of USBIndex Register.”...

  • Page 33: Usb Window 2(Usbwindow_2) R/W

    S1R72105 Technical Manual 7.3.22 USB Window 2 (USBWindow_2) R/W Displays the USB-related register. The register to be displayed changes according to the value set at USBIndex register (17h). For details of display by set values of the USBIndex register, refer to section “7.5 Detailed Description of Set Values of USBIndex Register.”...

  • Page 34: Usb Window 5(Usbwindow_5) R/W

    S1R72105 Technical Manual 7.3.25 USB Window 5 (USBWindow_5) R/W Displays the USB-related register. The register to be displayed changes according to the value set at USBIndex register (17h). For details of display by set values of the USBIndex register, refer to section “7.5 Detailed Description of Set Values of USBIndex Register.”...

  • Page 35: Main Interrupt Status Scsi (Mainints) R/W

    S1R72105 Technical Manual 7.3.28 Main Interrupt Status SCSI (MAININTS) R/W When the IC causes an SCSI interruption to the CPU, the CPU identifies the interrupt status register responsible for interruption by reading this register first. Following the reading of this register, the CPU reads the interrupt status register corresponding to each bit and performs appropriate interrupt processing by identifying the bit as a source of interruption.

  • Page 36: Scsi Interrupt Status 1 (Scsiint1) R/W

    S1R72105 Technical Manual 7.3.29 SCSI Interrupt Status 1 (SCSIINT1) R/W Shows the result of executing the SCSI control command. The CPU identifies the source of interruption by reading this register after receiving the interrupt signal. It clears the bit by writing the value read again.

  • Page 37: Scsi Interrupt Status 2 (Scsiint2) R/W

    S1R72105 Technical Manual 7.3.30 SCSI Interrupt Status 2 (SCSIINT2) R/W Shows the result of executing the SCSI control command. The CPU identifies the source of interruption by reading this register after receiving the interrupt signal. It clears the bit by writing the value read again.

  • Page 38: Scsi Mode Select0 (Scsimode0) R/W

    S1R72105 Technical Manual 7.3.31 SCSI Mode Select0 (SCSIMODE0) R/W Sets operation related to the SCSI interface. Address Register Name Bit Symbol Description SCSIMODE0 7: - 6: - 5: - 4: ULTRA ULTRA SCSI 3: AUTO1 AUTO1 (auto status) 2: AUTO2...

  • Page 39: Scsi Mode Select1 (Scsimode1) R/W

    S1R72105 Technical Manual 7.3.32 SCSI Mode Select1 (SCSIMODE1) R/W Sets operation related to the SCSI interface. Address Register Name Bit Symbol Description SCSIMODE1 7: STPPE STOP BY PARITY ERROR 6: ATNPE ATN ASSERT BY PARITY ERROR 5: STATN STOP BY ATN ASSERT...

  • Page 40: Scsi Control (Scsictl) R/W

    S1R72105 Technical Manual 7.3.33 SCSI Control (SCSICTL) R/W This register is accessed when the CPU directly controls SCSI signal lines. For such direct control, DIRECT (bit 1) must be set in the mode setting register (0Ah). The status of each signal is stored as “active high”.

  • Page 41: Synchronize Transfer Mode (Syncmode) R/W

    S1R72105 Technical Manual 7.3.35 Synchronize Transfer Mode (SYNCMODE) R/W Sets the transfer rate and offset for SCSI synchronous transfer. Address Register Name Bit Symbol Description SYNCMODE 7: RATE3 SYNCHRONOUS TRANSFER RATE[3] 6: RATE2 SYNCHRONOUS TRANSFER RATE[2] 5: RATE1 SYNCHRONOUS TRANSFER RATE[1]...

  • Page 42: Source/Destination Id (Sdid) R/W

    S1R72105 Technical Manual 7.3.37 Source/Destination ID (SDID) R/W Sets both the SCSI-ID of the selector side and the target SCSI-ID when selection is made. Address Register Name Bit Symbol Description SDID 7: - 6: SID2 SOURCE ID[2] (R/W) 5: SID1...

  • Page 43: Fifo Control (Fifoctl) R/W

    S1R72105 Technical Manual 7.3.39 FIFO Control (FIFOCTL) R/W Used for clearing the SCSI-FIFO data and for checking its status. Address Register Name Bit Symbol Description FIFOCTL 7: - 6: - 5: - 4: - 3: - 2: FCLR CLEAR FIFO...

  • Page 44: Scsi Command (Command) R/W

    S1R72105 Technical Manual 7.3.42 SCSI Command (COMMAND) R/W Sets SCSI control commands. Address Register Name Bit Symbol Description COMMAND 7: CMD7 (MSB) 6: CMD6 5: CMD5 4: CMD4 SCSI Command 3: CMD3 2: CMD2 1: CMD1 0: CMD0 (LSB) For details of each command, refer to section “7.4 SCSI Control Commands.”...

  • Page 45: Detailed Description Of Set Values Of Intindex Register

    S1R72105 Technical Manual 7.4 Detailed Description of Set Values of INTINDEX Register 7.4.1 Register Showing IntStatWindow_0,1 and IntEnbWindow_0,1 for Set Values of IntIndex Register IntIndex_n IntStatWindow_n IntEnbWindow_n EP0IntStat EP0IntEnb EPaIntStat EPaIntEnb EPbIntStat EPbIntEnb EPcIntStat EPcIntEnb Reserved Reserved Reserved Reserved Reserved...

  • Page 46: Ep{R}(R=0,A,B,C) Interrupt Enable(Ep{R}Intenb) R/W

    S1R72105 Technical Manual 7.4.3 EP {r} (r=0,a,b,c) Interrupt Enable (EP {r} IntEnb) R/W Appears in IntEnbWindow 0,1. This register enables/disables endpoint interruption shown in IntStatWindow_0,1. When the corresponding bit is set to HIGH an interruption to the CPU is enabled.

  • Page 47: Detailed Description Of Set Values Of Usbindex Register

    S1R72105 Technical Manual 7.5 Detailed Description of Set Values of USBIndex Register 7.5.1 List of Registers Showing USBWindow Register (8 bytes) Corresponding to Set Values of USBIndex Register(17h) USBIndex Address Register Name USBAddress EP0Config_1 EP0InControl EP0OutControl (Reserved) EP0FIFOremain EP0FIFOforCPU EP0FIFOCtrl...

  • Page 48: Description Of Registers By Set Value Of Usbindex

    S1R72105 Technical Manual 7.5.2 Description of Registers by Set Value of USBIndex 7.5.2.1 USB Address (USBAddress) R/W Sets the USB Address. This setting is cleared (set 00h) when the USB BusReset is detected. USBIndex : 00h Address Register Name Bit Symbol...

  • Page 49: Ep0 In Transaction Control(Ep0Incontrol) R/W

    S1R72105 Technical Manual 7.5.2.3 EP0 In Transaction Control (EP0InControl) R/W Sets operation to IN Transaction. USBIndex : 00h Address Register Name Bit Symbol Description EP0InControl 7: InForceNAK IN Transaction Force NAK 6: InForceSTALL IN Transaction Force STALL 5: InEnShortPkt IN Transaction Short Packet Enable...

  • Page 50: Ep0 Out Transaction Control(Ep0Outcontrol) R/W

    S1R72105 Technical Manual 7.5.2.4 EP0 OUT Transaction Control (EP0OutControl) R/W Sets operation to OUT Transaction. USBIndex : 00h Address Register Name Bit Symbol Description EP0OutControl 7: OutForceNAK IN Transaction Force NAK 6: OutForceSTALL IN Transaction Force STALL 5: 0 Reserved...

  • Page 51: Ep0 Fifo Remain Counter(Ep0Fiforemain) R

    S1R72105 Technical Manual 7.5.2.5 EP0 FIFO remain Counter (EP0FIFOremain) R Shows the number of bytes of remaining data in FIFO of Endpoint 0. USBIndex : 00h Address Register Name Bit Symbol Description EP0FIFOremain 7: EP0FIFOremainCount[7] 6: EP0FIFOremainCount[6] 5: EP0FIFOremainCount[5] 4: EP0FIFOremainCount[4]...

  • Page 52: Ep0 Fifo Control(Ep0Fifoctrl) R/W

    S1R72105 Technical Manual 7.5.2.7 EP0 FIFO Control (EP0FIFOCtrl) R/W Checks the status and sets operation of FIFO of Endpoint 0. USBIndex : 00h Address Register Name Bit Symbol Description EP0FIFOCtrl 7: FIFOEmpty FIFO Empty 6: FIFOFull FIFO Full 5: FIFOClr...

  • Page 53: Ep{R}(R=A,B,C) Config 0(Eprconfig_0) R/W

    S1R72105 Technical Manual 7.5.2.8 EP {r}(r=a,b,c) Config 0 (EPrConfig_0) R/W Sets operation of Endpoint a, b, and c. USBIndex : 01h to 03h Address Register Name Bit Symbol Description EPrConfig_0 7: EndPointNumber[3] 6: EndPointNumber[2] Endpoint Number 5: EndPointNumber[1] 4: EndPointNumber[0]...

  • Page 54: Ep{R}(R=A,B,C) Control(Eprcontrol) R/W

    S1R72105 Technical Manual 7.5.2.10 EP {r}(r=a,b,c) Control (EPrControl) R/W Sets operation for transaction in the direction of the endpoint set in the EPrConfig_0 register. USBIndex : 01h to 03h Address Register Name Bit Symbol Description EPrControl 7: ForceNAK Force NAK...

  • Page 55: Ep{R}(R=A,B,C) Fifo Remain Counter(Eprfiforemain) R

    S1R72105 Technical Manual 7.5.2.11 EP {r}(r=a,b,c) FIFO remain Counter (EPrFIFOremain) R Shows the number of bytes of remaining data in FIFO of the endpoint. USBIndex : 01h to 03h Address Register Name Bit Symbol Description EPrFIFOremain 7: EPrFIFOremainCount[7] 6: EPrFIFOremainCount[6]...

  • Page 56: Epr Fifo Control(Eprfifoctrl) R/W

    S1R72105 Technical Manual 7.5.2.13 EPr FIFO Control (EPrFIFOCtrl) R/W Checks the status and sets operation of FIFO of the endpoint. USBIndex : 01h to 03h Address Register Name Bit Symbol Description EPrFIFOCtrl 7: FIFOEmpty FIFO Empty 6: FIFOFull FIFO Full...

  • Page 57: Frame Number H(Framenumber_H) R

    S1R72105 Technical Manual 7.5.2.15 Frame Number H (FrameNumber_H) R Displays higher order 3 bits in the FrameNumber field of the SOF Packet received. USBIndex : 09h Address Register Name Bit Symbol Description FrameNumber_H 7: 0 Reserved 6: 0 Reserved 5: 0...

  • Page 58: Scsi Control Commands

    S1R72105 Technical Manual 7.6 SCSI Control Commands 7.6.1 Control Commands and Command Codes Code Command names Summary of commands Reserved Abort_SCSI SCSI Abort command Reserved Assert_RST SCSI Bus Clear command Busfree Reserved Assert_ATN SEL_MSG_clear SCAM control commands Select_WithoutATN Select_WithATN_Commannd SelectWithoutATN_Command...
  • Page 59 S1R72105 Technical Manual Assert_ATN (07H) Asserts the SCSI ATN signal (XSATN). The command is valid only in Initiator mode. If issued in Target mode, it is ignored. Also, it is not asserted in the busfree condition, however, no error occurs.
  • Page 60 S1R72105 Technical Manual Select_WithoutATN_Command (0BH) Executes selection while SCSI ATN is being negated and continues to execute the command phase. This command is valid in both disconnected and connected condition. Issuing this command while any other command is in execution causes a command error.
  • Page 61 S1R72105 Technical Manual Wait_Reselect(0EH) Waits for the re-selection phase. Valid only when it is not connected. Issuing this command in the connected condition sets the SCSIINT2 and CMDER bits and causes an interruption. Any other command being executed continues execution.
  • Page 62 S1R72105 Technical Manual If any other phase is found when the command phase is checked, the IC sets ILPHS of SCSIINT1 and causes an interruption. Note: Be sure to set the number of bytes of transfer before writing data in FIFO.
  • Page 63 S1R72105 Technical Manual DMA_Data_In (15H) Executes the data-in phase between SCSI and buffer. Valid only in the connected condition. It can be issued in either Target or Initiator mode. Issuing in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption.
  • Page 64 S1R72105 Technical Manual In Target mode The CPU issues this command after writing the status byte into SCSI FIFO. The IC transfers the status in FIFO after setting the status phase. It sets the GOOD bit of MAININT register and causes an interruption.
  • Page 65 S1R72105 Technical Manual the command is issued first and then determine the number of bytes to be received from the second byte by checking the message code received. In Initiator mode The CPU sets the number of bytes of a message to be sent in the NON-DMA data-size register before issuing this command.

  • Page 66: Command Execution And Change Of State

    S1R72105 Technical Manual 7.6.3 Command Execution and Change of State The IC goes through the following three states from the viewpoint of execution of SCSI-type commands: Disconnected state (D) Connected state in Initiator mode (I) Connected state in Target mode (T)
  • Page 67 S1R72105 Technical Manual Parity error in the SCSI data phase or command stop operation by detecting ATN The following points should be noted when the port interface is used as slave: If a setting has been made that a parity error or detection of ATN in SCSI data phase stops the operation of a command (STATN/STPPE/SPCEN bit of SCSIMODE register), the occurrence of such factor and subsequent command stop causes negation of PDREQ being output to the port interface at the internal timing of the IC.

  • Page 68: Electrical Characteristics

    S1R72105 Technical Manual 8. ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings = 0[V] Item Symbol Ratings Unit Supply voltage -0.3 to +6.0 -0.3 to +4.6 Input voltage -0.3 to HV +0.5 -0.3 to LV +0.5 Output voltage -0.3 to HV +0.5 -0.3 to LV...
  • Page 69 S1R72105 Technical Manual (2) TTL input characteristics (Ta = 0 to 70°C, V =0V) Names of signals covered: AD0 to 5, DB0 to 7, TESTEN, PD0 to 15, XSATN, XSBSY, XSRST, XSMSG, XSSEL, XSCD, XSIO Item Symbol Conditions Min. Typ.
  • Page 70 S1R72105 Technical Manual (7) Characteristics of pull-up and pull-down input (Ta = 0 to 70°C, V =0V) Names of signals covered: XRESET, TESTEN Item Symbol Conditions Min. Typ. Max. Unit Pull-up resistor kΩ =5.0V = HV Pull-down resistor kΩ =5.0V (8) Output characteristics (Ta = 0 to 70°C, V...

  • Page 71: Ac Characteristics

    S1R72105 Technical Manual (13) Output characteristics (Ta = 0 to 70°C,V = 0V) (I = 48mA) Names of signals covered: XSDB0 to 7, XSDBP, XSREQ, XSACK Item Symbol Conditions Min. Typ. Max. Unit HIGH level =Min. Output voltage =-20mA LOW level =Min.

  • Page 72: Cpu Interface

    S1R72105 Technical Manual 8.4.1 CPU Interface 8.4.1.1 Register Read Timing AD[4:0] DB[7:0] Symbol Item Min. Typ. Max. Unit XCS fall → XRD fall AD [4:0] Valid→ XRD fall XRD rise → AD [4:0] Invalid XRD rise → XCS rise XRD LOW level pulse width...

  • Page 73: Register Write Timing

    S1R72105 Technical Manual 8.4.1.2 Register Write Timing AD[4:0] DB[7:0] Symbol Item Min. Typ. Max. Unit XCS fall → XWR fall AD [4:0] Valid → XWR fall XWR rise → AD [4:0] Invalid XWR rise → XCS rise XWR LOW level pulse width...

  • Page 74: Scsi Interface

    S1R72105 Technical Manual 8.4.2 SCSI Interface 8.4.2.1 Selection Timing XSBSY(IN) XSSEL XSBSY(OUT) XSDB0-7,P XSATN XSIO Symbol Specification Min. Typ. Max. Unit XSBSY(IN) ↑ - XSBSY(OUT) ↓, 1600 OWNID valid XSBSY(OUT) ↓ - XSSEL ↓ 3000 XSSEL ↓ - SELID valid 1500 SELID valid - XSBSY(OUT) ↑...

  • Page 75: Re-Selection Timing

    S1R72105 Technical Manual 8.4.2.2 Re-selection Timing XSBSY(IN) XSSEL XSBSY(OUT) XSDB0-7,P XSIO Symbol Specification Min. Typ. Max. Unit XSBSY(IN) ↑ - XSBSY(OUT) ↓, 1600 OWNID valid XSBSY(OUT) ↓ - XSSEL ↓ 3000 XSSEL↓ -SELID valid, XSIO ↓ 1500 SELID valid - XSBSY(OUT) ↑...

  • Page 76: Timing Of Being Selected

    S1R72105 Technical Manual 8.4.2.3 Timing of Being Selected XSBSY(IN) XSSEL XSBSY(OUT) XSDB0-7,P Symbol Specification Min. Typ. Max. Unit SELID valid - XSBSY(IN) ↑ XSBSY(IN) ↑ - XSBSY(OUT) ↓ XSBSY(OUT) ↓ - XSSEL ↑ EPSON Rev.1.0...

  • Page 77: Timing Of Being Selected

    S1R72105 Technical Manual 8.4.2.4 Timing of Being Selected XSBSY(IN) XSSEL XSBSY(OUT) XSDB0-7,P XSIO Symbol Specification Min. Typ. Max. Unit SELID valid - XSBSY(IN) ↑ XSBSY(IN) ↑ - XSBSY(OUT) ↓ XSBSY(OUT) ↑ - XSSEL ↑ XSSEL ↓ - XSBSY(OUT) ↑ Rev.1.0...

  • Page 78: Xsatn Output Timing

    S1R72105 Technical Manual 8.4.2.5 XSATN Output Timing XSATN XSREQ XSACK XSDB0-7,P LAST MESSAGE XSMSG XSIO XSCD Symbol Specification Min. Typ. Max. Unit XSREQ ↓ - XSATN ↑ XSATN ↑ - XSACK ↓ EPSON Rev.1.0...

  • Page 79: Initiator Asynchronous Data-Out Timing (Data Output)

    S1R72105 Technical Manual 8.4.2.6 Initiator Asynchronous Data-out Timing (Data output) XSDB0-7,P XSREQ XSACK Symbol Specification Min. Typ. Max. Unit XSREQ ↓ - XSACK ↓ XSDB valid - XSACK ↓ XSREQ ↑ - XSACK ↑ XSACK ↑ - XSDB invalid Rev.1.0...

  • Page 80: Initiator Asynchronous Data-In Timing (Data Input)

    S1R72105 Technical Manual 8.4.2.7 Initiator Asynchronous Data-in Timing (Data input) XSDB0-7,P XSREQ XSACK Symbol Specification Min. Typ. Max. Unit XSDB valid - XSREQ ↓ XSREQ ↓ - XSACK ↓ XSACK ↓ - XSDB invalid XSREQ ↑ - XSACK ↑ EPSON...

  • Page 81: Initiator Synchronous Data-Out Timing (Data Output)

    S1R72105 Technical Manual 8.4.2.8 Initiator Synchronous Data-out Timing (Data output) XSDB0-7,P XSACK Symbol Specification Min. Typ. Max. Unit XSDB valid - XSACK ↓ XSACK ↓ - XSDB invalid XSACK ↓ - XSACK ↑ XSACK ↑ - (NEXT) XSACK ↓ Note: Value when RATE3 to 0bit is “0000.”...

  • Page 82: Initiator Synchronous Data-In Timing (Data Input)

    S1R72105 Technical Manual 8.4.2.9 Initiator Synchronous Data-in Timing (Data input) XSDB0-7,P XSREQ Symbol Specification Min. Typ. Max. Unit XSDB0-7, P valid - XSREQ ↓ XSREQ ↓ - XSDB0-7, P invalid XSREQ ↓ - XSREQ ↑ XSREQ ↑ - XSREQ ↓...

  • Page 83: Target Asynchronous Data-In Timing (Data Output)

    S1R72105 Technical Manual 8.4.2.10 Target Asynchronous Data-in Timing (Data output) XSDB0-7,P XSREQ 242a XSACK 242b Symbol Specification Min. Typ. Max. Unit XSDB valid - XSREQ ↓ XSACK ↑ - XSREQ ↑ XSREQ ↑ - XSDB invalid XSACK ↑ - (NEXT) XSREQ ↓...

  • Page 84: Target Asynchronous Data-Out Timing (Data Input)

    S1R72105 Technical Manual 8.4.2.11 Target Asynchronous Data-out Timing (Data input) XSDB0-7,P XSREQ 246a XSACK 246b Symbol Specification Min. Typ. Max. Unit XSDB valid - XSACK ↓ XSACK ↓ - XSREQ ↑ XSREQ ↑ - XSDB invalid XSACK ↑ - XSREQ ↓...

  • Page 85: Target Synchronous Data-In Timing (Data Output)

    S1R72105 Technical Manual 8.4.2.12 Target Synchronous Data-in Timing (Data output) XSDB0-7,P XSREQ Symbol Specification Min. Typ. Max. Unit XSDB valid - XSREQ ↓ XSREQ ↓ - XSDB invalid XSREQ ↓ - XSREQ↑ XSREQ ↑ - XSREQ ↓ Note: Value when RATE3 to 0bit is “0000.”...

  • Page 86: Target Synchronous Data-Out Timing (Data Input)

    S1R72105 Technical Manual 8.4.2.13 Target Synchronous Data-out Timing (Data input) XSDB0-7,P XSACK Symbol Specification Min. Typ. Max. Unit XSDB valid - XSACK ↓ XSACK ↓ - XSDB invalid XSACK ↓ - XSACK ↑ XSACK ↑ - XSACK ↓ EPSON Rev.1.0...

  • Page 87: Port Interface

    S1R72105 Technical Manual 8.4.3 Port Interface 8.4.3.1 DMA Read (PSLV=1: Slave mode) Direction of data transfer Prosessor S1R72105 HOST PDREQ(0) (PRQLV=1) XPDACK(I) XPRD(I) PD15-0(0) XPWR(I) Symbol Specification Min. Typ. Max. Unit XPWR → XPDACK ↓ XPDACK setup time XPDACK ↑ → XPWR XPDACK hold time XPRD ↓...

  • Page 88: Dma Write (Pslv=1: Slave Mode)

    S1R72105 Technical Manual 8.4.3.2 DMA Write (PSLV=1: Slave mode) Direction of data transfer Prosessor S1R72105 HOST PDREQ(0) (PRQLV=1) XPDACK(I) XPWR(I) PD15-0(I) XPRD(I) Symbol Specification Min. Typ. Max. Unit XPRD → XPDACK ↓ XPDACK setup time XPDACK ↑ → XPRD XPDACK hold time XPWR ↓...

  • Page 89: Dma Write (Pslv=0: Master Mode)

    S1R72105 Technical Manual 8.4.3.3 DMA Write (PSLV=0: Master mode) Direction of data transfer Prosessor S1R72105 HOST PDREQ(I) XPDACK(0) XPWR(0) PD15-0(0) Symbol Specification Min. Typ. Max. Unit XPWR ↓ → PDREQ negate PDREQ negate delay time XPDACK ↓ → XPWR ↓...

  • Page 90: Dma Read (Pslv=0: Master Mode)

    S1R72105 Technical Manual 8.4.3.4 DMA Read (PSLV=0: Master mode) Direction of data transfer Prosessor S1R72105 HOST PDREQ(I) XPDACK(0) XPRD(0) PD15-0(I) Symbol Specification Min. Typ. Max. Unit XPRD ↓ → PDREQ negate PDREQ negate delay time XPDACK ↓ → XPRD ↓...

  • Page 91: Others

    S1R72105 Technical Manual 8.4.4 Others 8.4.4.1 OSCIN Input Clock ( ex.40MHz) Note: Maximum input voltage: LV 1.9V 0.9V Symbol Specification Min. Typ. Max. Unit CLK cycle *1 (1/f) CLK HIGH width *1 (1/f)×0.4 (1/f)×0.6 CLK LOW width *1 (1/f)×0.4 (1/f)×0.6...

  • Page 92: Exclk Input Clock (48Mhz)

    S1R72105 Technical Manual 8.4.4.2 EXCLK Input Clock (48MHz) Note: Maximum input voltage: LV 1.9V 0.9V Symbol Specification Min. Typ. Max. Unit CLK cycle *1 20.83 CLK HIGH width *1 8.33 12.5 CLK LOW width *1 8.33 12.5 CLK rise time...

  • Page 93: Xreset Input Pulse Width

    S1R72105 Technical Manual 8.4.4.3 XRESET Input Pulse Width XRESET Symbol Specification Min. Typ. Max. Unit XRESET LOW width 8.4.4.4 USB Interface Access Timing Conformity to the USB 1.1 Specification. For the USB1.1 Specification, visit http://www.usb.org/developers/docs.html. Rev.1.0 EPSON...

  • Page 94: Examples Of Connection

    S1R72105 Technical Manual 9. EXAMPLES OF CONNECTION (When 20MHz OSC oscillation is used) S1R72105 ∗CPU Interface(5V type) ∗USB Interface XPUENB Use figure 2 AD [5:0] AD [5:0] DB [7:0] DB [7:0] XUSBOE XINT0 XINTS XINT1 XINTU ∗PORT Interface(5V type) PD [15:0]...
  • Page 95 S1R72105 Technical Manual S1R72105 100kΩ 3.3V 10kΩ XPUENB USB Connector 5.6kΩ Series B Receptacle 3.3V 3.3V 24Ω 24Ω GND GND Fig.2. USB Connection Diagram 1) Connect the V pin to the V pin of the connector by providing chattering prevention circuit.

  • Page 96: External Dimensions Drawing

    S1R72105 Technical Manual 10. EXTERNAL DIMENSIONS DRAWING Plastic QFP15-100 pin ±0.4 ±0.1 INDEX +0.1 0.18 -0.05 +0.05 0.125 -0.025 0° 10° ±0.2 Unit:mm EPSON Rev.1.0...
  • Page 97 FAX: +852-2827-4346 Crystal Lake, IL 60014, U.S.A. Telex: 65542 EPSCO HX Phone: +1-815-455-7630 FAX: +1-815-455-7633 EPSON TAIWAN TECHNOLOGY & TRADING LTD. Northeast 10F, No. 287, Nanking East Road, Sec. 3 301 Edgewater Place, Suite 120 Taipei Wakefield, MA 01880, U.S.A.
  • Page 98 In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
  • Page 99 S1R72105 Technical Manual SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com/ First issue October, 2002 Printed in Japan...

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