Philips 32PFS5709/12 Service Manual page 81

8.7 Diagram 10-16-12 HDMI /Connector
Block diagram
Pinning information
B12, SII9679CNUC (IC U713)
SiI9679
VDD5V_IN
RPWR5V
SPI_MISO SPI Master
SPI_MOSI
SPI_CS0
SPI Slave
SPI_CS1
SPI_CLK
SPI Logic
1V2 Regulator
HSIC_DAT
HSIC PHY
HSIC_STB
CBUS
CBUS_HPD
Control
1V8
LPSBV LPSB
Regulator
Rx DDC
DDC_Rx
Interface
Authentication
RXCP/N
HDMI/
RX0P/N
MHL1, 2, 3
RX1P/N Receiver
Decryption
RX2P/N
76 75 74 73
VDD33OUT 1
VDD5V IN 2
RPWR5V 3
CBUS HPD 4
CoC GND 5
AVDD10 DoC 6
RXCN 7
RXCP 8
AVDD10 9
VDD33 10
RX0N 11
RX0P 12
RX1N 13
RX1P 14
RX2N 15
RX2P 16
AVDD10 17
FVDD10 18
VDDIO33 19
20 21 22 23
Figure 8-9 Internal block diagram and pin configuration
IC Data Sheets
ISP
OSC
MCU
Data
Tunneling
Control Registers
OTP
Rx HDCP HDCP Tx HDCP
Repeater Authentication
Logic
Logic
Tx HDCP
Video Data
Encryption
Conversion
Logic
Video Data
HDCP
Audio Data
Engine
72 71 70 69 68 67 66 65 64 63 62 61 60 59
SiI 9679
Top View
ePad (GND)
24 25 26 27 28 29 30 31 32 33 34 35 36 37
back to
div. table
TPM14.2E LA
3V3
VCC33OUT
Regulator
2
Local I C
Local I
Slave Logic
CEC
Interface
CEC_A
(SiI9394
Dongle Only)
RESETN
GPIO0_CI2CA
GPIO1_PSCTL
Registers,
GPIO2
Configuration,
GPIO3
and Interrupt
GPIO4
GPIO5
INT
MHL_CD
TX_HPD
WAKEUP
Tx DDC
DDC_Tx
Interface
Logic
TX2P/N
TX1P/N
HDMI TMDS
Transmitter
TX0P/N
Engine TXCP/N
SD0_SPDIF
WS
Audio
SCK
Output
MCLK
Logic
XTALIN
(SiI9394
XTALOUT
Dongle Only)
58
57 HSIC VDD33
56 VDD12OUT
55 HSIC GND
54 HSIC STB
53 HSIC DAT
52 NC
51 XTAL GND
50 XTAL OUT
49 XTAL IN
48 XTAL VDD33
47 TX2P
46 TX2N
45 TX1P
44 TX1N
43 TX0P
42 TX0N
41 TXCP
40 TXCN
39 AVDD10 DP
38
8. EN 81
2
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2014-Sep-26