5.2.4.5
Initiating Write DMA
DMARQ
DMACK-
STOP
tZIORDY
DDMARDY-
HSTROBE
DD(15:0)
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Figure 13 Ultra DMA cycle timing chart (Initiating Write)
PARAMETER
DESCRIPTION
(all values in ns)
Unlimited interlock time
tUI
Setup time before
tACK
DMACK–
Envelope time
tENV
Minimum time before
tZIORDY
driving IORDY
Limited interlock time
tLI
Cycle time
tCYC
Two Cycle time
t2CYC
Data setup time (at
tDS
device side)
Data hold time (at
tDH
device side)
Table 22 Ultra DMA cycle timings (Initiating Write)
HITACHI Deskstar & CinemaStar P7K500 Hard Disk Drive specification (Rev 1.1)
tUI
tACK
tENV
tACK
Host drives DD
MODE0
MODE1
MIN
MAX
MIN
MAX
0
–
0
–
20
–
20
–
20
70
20
70
0
–
0
–
0
150
0
150
112
–
73
–
230
–
154
–
15
–
10
–
5
–
5
–
30
tLI
t2CYC
tCYC
tUI
tDS
xxx
WT Data
WT Data
MODE2
MODE3
MODE4
MIN
MAX
MIN
MAX
MIN
0
–
0
–
0
20
–
20
–
20
20
70
20
55
20
0
–
0
–
0
0
150
0
100
0
54
–
39
–
25
115
–
86
–
57
7
–
7
–
5
5
–
5
–
5
tCYC
tDH
tDS
tDH
xxx
WT Data
MODE5
MODE6
MAX
MIN
MAX
MIN
–
0
–
0
–
20
–
20
55
20
50
20
–
0
–
0
100
0
75
0
–
16.8
–
13.0
–
38
–
29
–
4
–
2.6
–
4.6
–
3.5
MAX
–
–
50
–
60
–
–
–
–