Clock System Diagram; Figure 1.1 Clock System Diagram - Toshiba TXZ+ Series Reference Manual

1.2.3. Clock System diagram

The figure below shows a clock system diagram.
[CGWUPHCR]<WUON>
[CGWUPHCR]<WUPT[15:4]>
High Speed
Warming up timer
[CGWUPHCR]
<WUCLK>
[CGOSCCR]<IHOSC1EN>
After reset :Oscillation
Internal
High Speed
f
oscillator1
IHOSC1
SIWDT
Flash
[CGOSCCR]<EOSCEN[1:0]>
After Reset: Stop
External
X2
High speed
oscillator
X1
f
EHOSC
EHCLKIN
OSCPRO
[CGOSCCR]<IHOSC2EN>
After reset：Stop
Internal
High speed
oscillator2
f
IHOSC2
SIWDT
LCD
[CGWUPLCR]<WULON>
[CGWUPLCR]<WUPTL[18:4]>
Low speed
Warming up timer
XT2 External
Low speed
fs
Oscillator
XT1
[RLMLOSCCR]<XTEN>
After Reset: Stop
fc
1/2
fc
1/2
PLL for fsys
PLL0
f
OSC
[CGOSCCR]
<OSCSEL>
OFD
1/4
1/8
1/16
[CGSYSCR]
<GEAR[2:0]>
1/4 1/8 1/16 1/32 1/64 1/128

Figure 1.1 Clock system diagram

[CGSPCLKEN]
<ADCKEN>
[CGFCEN]<FCIPEN07>
f
PLL
fc
[CGPLL0SEL]
<PLL0SEL>
fc
f
OSC
1/2
fs
fsys
No dividing when fs is selected.
[CGSCOCR]<SCOSEL[2:0]>
f
IHOSC2
f
OSC
[CGSPCLKEN]
<TRCKEN>
fsys
fsys
[CGFSYSENB]<IPENBxx>
[CGFSYSENA]<IPENAxx>
[CGFSYSMENB]<IPMENBxx>
ΦT0
[CGSYSCR]
1/256 1/512
<PRCK[3:0]>
12 / 72
TMPM3H Group(1)
Clock Control and Operation Mode
ADC
ADCLK
DNF
(to fsys and ΦT0 generation)
fc
[CGSCOCR]
<SCOEN>
1/4 1/8 1/16
[CGSCOCR]<SCODIV[2:0]>
RTC, RMC, T32A (TRGSEL)
LCD
1/64
SysTick
CPU
1/2
TRCLKIN
TRCK
DMAC, TSPI, I2C, EI2C,
UART, SIWDT, T32A, RTC,
A-PMD, A-ENC, RMC,
ADC, DAC, OFD, PORT,
TRM, TRGSEL, CRC, RAMP
Flash, RAM, INTIF
【Peripheral function prescaler inputs】
T32A, UART, TSPI
TXZ+ Family
SCOUT
DEBUG
TPIU
2022-05-10
Rev. 1.3