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23.2 Operation List
Instruc- Mnemonic
tion
Group
8-bit
MOV
data
trans-
fer
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Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
2. Clock indicates when a program is in the internal ROM area.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
506
CHAPTER 23 INSTRUCTION SET
Operands
Byte
r, #byte
2
8
saddr, #byte
3
12
sfr, #byte
3
—
A, r
Note 3
1
4
Note 3
r, A
1
4
A, saddr
2
8
saddr, A
2
8
A, sfr
2
—
sfr, A
2
—
A, !addr16
3
16
!addr16, A
3
16
PSW, #byte
3
—
A, PSW
2
—
PSW, A
2
—
A, [DE]
1
8
[DE], A
1
8
A, [HL]
1
8
[HL], A
1
8
A, [HL+byte]
2
16
[HL+byte], A
2
16
A, [HL+B]
1
12
[HL+B], A
1
12
A, [HL+C]
1
12
[HL+C], A
1
12
Clock
Note 1
Note 2
r ← byte
—
(saddr) ← byte
14
sfr ← byte
14
A ← r
—
r ← A
—
A ← (saddr)
10
(saddr) ← A
10
A ← sfr
10
sfr ← A
10
A ← (addr16)
18 + 2n
(addr16) ← A
18 + 2m
PSW ← byte
14
A ← PSW
10
PSW ← A
10
A ← (DE)
10 + 2n
(DE) ← A
10 + 2m
A ← (HL)
10 + 2n
(HL) ← A
10 + 2m
A ← (HL+byte)
18 + 2n
(HL+byte) ← A
18 + 2m
A ← (HL+B)
14 + 2n
(HL+B) ← A
14 + 2m
A ← (HL+C)
14 + 2n
(HL+C) ← A
14 + 2m
CPU
Operation
Z
×
×
) selected by processor clock control
Flag
AC CY
×
×
×
×
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