Stop Mode - NEC 78014Y Series User Manual

20.2.2 STOP mode

(1) STOP mode set and operating status
The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock.
Cautions 1. When the STOP mode is set, X1 input is internally short-circuited to V
The operating status in the STOP mode is described below.
STOP Mode Setting With subsystem clock
Item
Clock generator
CPU
Output port (output latch)
16-bit timer/event counter
www.DataSheet4U.com
8-bit timer/event counter
Watchdog timer
A/D converter
Watch timer
Serial Other than auto- Operation enabled only when external input clock is selected as serial clock.
Interface matic transmit/
receive function
Automatic
transmit/receive
function
External INTP0
interrupt INTP1 to INTP3 Operation enabled.
Bus line in AD0 to AD7
External A8 to A15
Expansion ASTB
WR, RD
WAIT
488
CHAPTER 20 STANDBY FUNCTION
to suppress the leakage at the crystal oscillator. Thus, do not use the STOP mode in a
system where an external clock is used for the main system clock.
2. Because the interrupt request signal is used to clear the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset, the
standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode
immediately after execution of the STOP instruction. After the wait set using the oscillation
stabilization time select register (OSTS), the operating mode is set.
Table 20-3. STOP Mode Operating Status
Only main system clock stops oscillation.
Operation stop.
Status before STOP instruction execution is held.
Operation stop.
Operation enabled when TI1 and TI2 are selected for the count clock.
Operation stop.
Operation enabled when f
for the count clock.
Operation stop.
Operation disabled.
High-impedance
Status before STOP instruction execution is held.
Low level
High level
High-impedance
Without subsystem clock
is selected Operation stop.
XT
(ground potential)
SS