Sony SWF-BR100 Service Manual page 22

SWF-BR100
• Waveforms
– MAIN Board –
IC111 qa (XOUT)
1
2.9 Vp-p
125 ns
1 V/DIV, 50 ns/DIV
IC103 9 (2Q)
2
4 Vp-p
81 ns
1 V/DIV, 50 ns/DIV
3 IC105 qf (XFSOOUT)
2.9 Vp-p
20.6 ns
1 V/DIV, 10 ns/DIV
IC105 wl (LRCK)
4
3.3 Vp-p
20.8 s
1 V/DIV, 10 s/DIV
IC105 e; (BCK)
5
3.3 Vp-p
326 ns
1 V/DIV, 200 ns/DIV
IC107 4
6
3 Vp-p
20.8 ns
1 V/DIV, 10 ns/DIV
SWF-BR100
• IC Block Diagrams
– MAIN Board –
IC101 PST8435UL
GND 1
VREF
+
–
4
VDD 2 3
IC103 TC74LCX74FT (EKJ)
14 13 12 11 10 9 8
VCC
PR
Q
D
CK Q
CLR
PR
D Q
CK Q
CLR
GND
1 2 3 4 5 6 7
IC104 CXD9981TN
1
GVDD_B
/DTW 2
NC 3
INTERNAL PULLUP
NC 4 RESISTORS TO VREG
/SD 5
OUT
CD
PWM
6
PWM_A
RCV.
/RESET_AB 7
PWM
PWM_B 8
RCV.
OC_ADJ 9 I-SENSE
GND 10
AGND 11
VREF 12
VREG
M3 13
M2 14
M1 15
PWM
PWM_C 16
RCV.
/RESET_CD 17
PWM
PWM_D 18
RCV.
NC 19
NC 20
VDD 21
GVDD_C 22
22 22
4
UNDER-
VOLTAGE
4
PROTECTION
PROTECTION
TEMP.
AND
SENSE
I/O LOGIC
GATE
TIMING
CTRL
DRIVE
BTL/PBTL-CONFIGURATION
PULLDOWN RESISTOR
BTL/PBTL-CONFIGURATION
PULLDOWN RESISTOR
GATE
TIMING
CTRL
DRIVE
OVERLOAD
PROTECTION
POWER
ON
RESET
GATE
CTRL TIMING
DRIVE
BTL/PBTL-CONFIGURATION
PULLDOWN RESISTOR
BTL/PBTL-CONFIGURATION
PULLDOWN RESISTOR
GATE
TIMING
CTRL
DRIVE
44 GVDD_A
43 BST_A
42 NC
41 PVDD_A
40 PVDD_A
39
OUT_A
38 GND_A
37
GND_B
36 27 OUT_B
35 PVDD_B
34 BST_B
33
BST_C
32 PVDD_C
31 OUT_C
30 GND_C
29 GND_D
28 OUT_D
27 PVDD_D
26 PVDD_D
25 NC
24 BST_D
23 GVDD_D