Sony KDP-51WS550 Training Manual page 8

The resolution to this dilemma is the creation of a complete end-to-end standard digital video interface, ala DVI.
The DVI interface is a high-speed digital video interface allowing uncompressed high-definition content to be
passed to another DVI equipped device such as an HDTV set. DVI is the only digital interface capable of
accommodating uncompressed digital data such as HD video. DVI also has the bandwidth to support higher
audio fidelity.
DVI has a bandwidth of up to 5 Gigabits/sec, which is more then enough to accommodate an uncompressed HD
video transmission typically requiring 2.2 Gigabits/sec bandwidth.
DVI Connector and Decoding Block
Ref. Figure 2-2
The DVI Molex connector and Decoding circuitry for the AX-1 chassis are located on the UD-Board (NOTE: This
board is NOT field repairable). Figure 2-2 shows a block diagram for the UD-Board. The DVI signal (from a
Digital TV/Satellite Receiver) is received at the 24-pin Molex connector CN7001. There are three serial data
differential channels RX0+/RX0-, RX1+/RX1-, RX2+/RX2- and one reference clock differential channel RXC+/
RXC-.
IC7001 NVM is also connected to the external device through the SDA and SCL (I2C) bus. IC7001 stores the
EDID (Extended Display Identification Data).
EDID is sent to inform the STB or external digital device of the TV's identity and capabilities.
HDCP is an Authentication protocol between the external digital device (transmitter) and the TV (receiver) that
affirms to the transmitter that the receiver is authorized to receive the protected digital video information.
CN 7001/pin 14 (5V) is supplied from the external digital device to power IC7001 (NVM) so EDID can be sent
when the TV set is OFF. If the TV set is ON, IC7001 will receive 5V from CN7002 through D7001.
CN7001/pin 16 is the Hot Plug Detect pin (HPD). The TV set supplies 5V to the external digital device to verify
proper connection between the two devices.
X7001
14.31818MHz
1
9
CONNECTOR
17
R x 1+
R x 2+
R x 1- R x 0-
R x 2-
1 2
9 10 17
3.3V 2.5V
94
IC7004
DVI-DECODER
95
SDA,
SCL
5V
2
IC7005
MCU
X7002
3
12MHz
FIGURE 2-2 - UD BOARD BLOCK (DVI DECODER)
R x 0+ R x C- SDA
R x C+ SCL
18 23 24 6 7
EDID
IC7001
5V
NVM
5V
COMPONENT OUT
SDA, SCL
IC7006
NVM
HDCP
6
8
16
24
CN7001
HPD
24P MOLEX
5V
CONNECTOR
14 16
R7021
CN2304/
10kHz
PIN 1
5V
D7001
TO
CN7002/
PIN 1 (5V)
3.3V
3.3V
REG
2.5V
CN7002
2.5V
REG
Y
10
8 PB
6
PR
SET-UP
13
4 MUTE
3
VGA
2
RESET
5V
1 5V
5V
TVP16.2-2 1/30/04
2. New Features