Halt - Epson S1C17 Series Manual

halt

Function HALT
Standard)
Extension 1) Unusable
Extension 2) Unusable
15 14 13 12 11 10
Code
0 0 0
| |
IL IE C
Flag
| |
– – –
Mode –
CLK Six cycles
Description Sets the processor to HALT mode for power saving.
Program execution is halted at the same time that the S1C17 Core executes the halt instruction,
and the processor enters HALT mode.
HALT mode commonly turns off only the S1C17 Core operation, note, however that modules to be
turned off depend on the implementation of the clock control circuit outside the core.
Initial reset is one cause that can bring the processor out of HALT mode. Other causes depend on
the implementation of the clock control circuit outside the S1C17 Core.
Initial reset, maskable external interrupts, NMI, and debug interrupts are commonly used for
canceling HALT mode.
The interrupt enable/disable status set in the processor does not affect the cancellation of HALT
mode even if an interrupt signal is used as the cancellation. In other words, interrupt signals are
able to cancel HALT mode even if the IE flag in PSR or the interrupt enable bits in the interrupt
controller (depending on the implementation) are set to disable interrupts.
When the processor is taken out of HALT mode using an interrupt that has been enabled (by the
interrupt controller and IE flag), the corresponding interrupt handler routine is executed. Therefore,
when the interrupt handler routine is terminated by the reti instruction, the processor returns to
the instruction next to halt.
When the interrupt has been disabled, the processor restarts the program from the instruction next
to halt after the processor is taken out of HALT mode.
Refer to the technical manual of each model for details of HALT mode.
Example
halt
S1C17 CORE MANUAL
(Rev. 1.2)
Sets the processor to HALT mode
9 8 7 6
|
0 0 0 0 0 0 0
| | | | | |
V Z N
| | |
– – –
; Sets the processor in HALT mode.
Seiko Epson Corporation
5 4 3 2 1 0
0 0 1 0 0 0
| | | | | |
7 DETAILS OF INSTRUCTIONS
7-35