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Model 5065A
Circuit Diagrams, Theory, and Maintenance
CIRCUIT DESCRIPTION
"
The 1 MHz drive signal connects through J1 to A5A2(1)
Master Clock Board. The master clock board has the
— following circuits:
a.
Input Filter and Shaper Circuit
b.
Sync One-Shot mV Circuit
—
c.
Gated 1 MHz mV and the Master and Clock
Drive mV
d.
Master Clock (six decades connected for a
10
6
division)
INPUT FILTER AND SHAPER
_ Diodes A2CR1 and A2CR2 limit input signal level.
A2Q1 and A2Q2 drive the 1 MHz high "Q" filter to
suppress unwanted signals.
A2C4 resonates T1 at 1
MHz. CR3 provides regulated bias for A2Q1.
In the
— filter circuit, A2C9 tunes A2Y1 to 1 MHz. The spectrally
clean 1 MHz signal from A2Y1 is applied to shaper
amplifiers A2Q4 and A2Q6 to drive gated 1 MHz MV
A2IC2.
Diode A2CR5 and saturating amplifier A2Q6
^ p r o v i d e the shaping (squaring) action.
_ GATED 1 MHz MULTIVIBRATOR
A2IC2 produces a 1 MHz, 200 nsec wide, positive
pulse for 1 MHz clock drive MV A2IC3. This pulse also
— „ g o e s to the output gates on A5A3 circuit board [A5A2(4)
to A5A3(5)] to A5A3IC2C(1) and to A5A3IC12B(9).
When proper gate sequencing occurs, this pulse is gated
through A3IC2C or through A3IC12B (as shown in the
—timing diagrams) to the 1 PPS output circuits.
The 1 MHz master and preset clock
multivibrator
A2IC3 is triggered by the negative transition of A2IC2
^output pulse, producing a negative 1 MHz output pulse
at A2IC3(7) delayed by 150 nsec. This pulse is the count
pulse for the master and preset clock.
The master clock is a six-decade divider producing a
negative, 100 msec wide, 1 PPS output.
This master
pulse controls the reset and preset circuits of the preset
__clock divider. Since all decades of the master clock are
identical, only A2IC6 will be discussed.
Normally, decade dividers are allowed to fill until the
—count cycles to "0". At this time, an output pulse is
applied to the next decade. Thus, for each 10 inputs, 1
output pulse is applied to the next stage. However, this
technique introduces error due to decade cycling time
~and decade temperature sensitivity.
This error is ac
cumulative through a divider chain and, with 6 decades,
:ould amount to as much as 1 Msec. The technique used
n the master clock divider reduces this error to less than
100 nanoseconds.
\r\ " H " input pulse at A2IC6(5) is necessary for the
—Jecade to divide; therefore, all count inputs to the in
verter A2IC4A(1) must be "L". When the decade is at
"0", voltage levels at pins 6, 7, 8, and 1 are " H " and out
put NAND gate A2IC12A(6) will be "L", applying a
"L" count pulse to the following decade inverter. If any
input signal to NAND gate A2IC12A is "L", the fol
lowing decade inverter will receive an " H " which will
not count.
The 1 MHz "L" pulses applied to A2IC4A(1) are inverted
and applied to divider, A2IC6. As the count progresses
within the IC, pins 6, 7, 8, and 1 will change from " H " to
"L" at various counts as shown in the timing diagram
for A2IC6. When the tenth count pulse is applied to
A2IC6(5), the divider cycles to "0" and A2IC6 (6, 7, 8,
and 1) place an " H " at A2IC12A (1, 2, 4, and 5). How
ever, A2IC12A(6) is still " H " because the same pulse
cycling the decade to "0" places an "L" through A2CR6
to the NAND gate, holding it closed. When this pulse
goes " H " , the NAND gate applies an "L" to the fol
lowing decade input inverter as a count pulse. This state
will remain until the next "L" count pulse, " 1 " , is
applied to A2IC4A(1). A2IC12A(3) goes "L", closes the
gate and ends the "L" input to the following decade in
put inverter.
Since the actual output pulse was not
processed through the decade, delay due the decade is
eliminated.
This process is repeated through the five remaining
decades with the final output master tick, 1 PPS, 100
msec, negative pulse applied to the following preset
clock divider and associated circuits.
RESET AND PRESET ONE-SHOT CIRCUITS
Operation of Digital Divider A5 is illustrated in the A5
timing diagrams. The 1 PPS master clock tick triggers
reset one-shot A3IC15 producing complementary 1.3
/u sec pulses at pins 7 and 10. The "L" signal at pin 7
drives reset amplifiers A3Q7, A3Q9, A3Q11, and decade
control NOR gate A3IC17B through inverting amplifier
A3IC17A.
This signal resets decade A3IC3, A3IC4,
A3IC5, A3IC6, A3IC7, and A3IC8 to "0".
During the
decade reset time, A3IC17B(7) output holds all decade
input NAND gates closed to any input count. Each time
the reset one-shot is triggered, a 1.3 /usec " H " signal is
also placed at NAND gate A3IC12B(10).
When the complementary 1.3 psec pulse at A3IC15(10)
goes "L", it triggers preset one-shot A3IC16. The output
at pin 10 of A3IC16 is inverted by A3Q8, A3Q10, and
A3Q12 applying a 0.5 jusec "L" preset pulse into the
thumbwheel switches to preset the desired count into
the preset clock. The same signal at A3IC16(10) causes
NOR gate A3IC17B(7) to remain "L" an additional 0.5
yusec, which holds the decade input NAND gates closed
to any input count during this presetting action.
The
preset clock decades are now reset and preset.
PRESET CLOCK DIVIDERS
Six adjustable decade dividers make up the preset clock
divider.
The dividing scheme allows division by any
integer between 1 and 10
6
by simply setting TIME
8-29
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