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Service
Model 35601A
NOTE
HP-IB input lines have a low true logic definition.
The signals denoted with ' ' are HP-IB control lines.
When the Al board is addressed to listen or the 'ATN' line is true (low), the Al board must
do a three-wire handshake to get data from lines 'DIOT through 'DI08\ This is done using
the 'NRFD' and 'NDAC lines which are driven by the Handshake circuitry
6-80. Handshake
Three R-S flip-flops, each consisting of gates, are included in the circuit; for this discussion,
these will be defined as FFl, FF2, and FF3. FFl consists of U32A and U32B where pin 4 is
defined as Ql. FF2 consists of U32C and U32D where pin 13 is defined as Q2. FF3 (the ad
dressed flip-flop) consists of U27B and U25D with the Q output (defined as LADS) at pin 8.
Figure 6-25 shows the timing relationship of the handshake signals; Figure 6-26 is a state
diagram of the events in the handshake which shows the outputs of FFl and FF2 (Ql and
Q2) as their inputs vary.
The output of U33A is pin 4 and defined as MONOl. The output of U33B is pin 5 and de
fined as MON02. U33A is triggered by a positive-going edge on pin 3; the monostable signal
(MONOl) has a period of 0.5 Q sec. U33B is triggered by a negative-going edge on pin 10;
MON02 has a period of 0.5 Q sec.
The next state of FFl and FF2 is determined by the HP-IB handshake signals, MON02, and
the present states of FFl and FF2. These flip-flops are driven by U24, U29D, U29C, and
U28D. NDAC is generated by U26C and is determined by this expression:
'NDAC = DAC • MON02
DAV is generated by U26B and is defined as follows:
DAV = 'DAV • ( 'ATN' + LADS )
RFD is generated by FFl and is equivalent to Ql; DAC is generated by FF2 and is equivalent
to Q2.
'RFD'
'DAV
MONO
•*V*
MONO,
DAV = 'DAV CATN + LADS)
'DAC' = Q « M -
6-72
Figure 6 25. Timing Diagram for HP IB Handshake
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