Interrupt Function; Setting Of Tout Output - Epson 0C88832 Technical Manual

The pulse width measurement timer mode is the
same as the timer mode except that the input clock
is controlled by the level of the signal (EVIN) input
to the K10 input port terminal.
See "5.10.2 Count operation and setting basic mode"
for the basic operation and control.

5.10.7 Interrupt function

The programmable timer can generate an interrupt
due to an underflow signal of timer 0 and timer 1.
Figure 5.10.7.1 shows the configuration of the
programmable timer interrupt circuit.
The respectively corresponding interrupt factor
flags FPT0 and FPT1 are set to "1" and an interrupt
is generated by an underflow signal of timers 1 and
0. Interrupt can also be prohibited by the setting of
the interrupt enable registers EPT0 and EPT1
corresponding to each interrupt flag.
In addition, a priority level of the programmable
timer interrupt for the CPU can be optionally set at
levels 0 to 3 by the interrupt priority registers PPT0
and PPT1.
For details on the above mentioned interrupt control
registers and the operation following generation of
an interrupt, see "5.14 Interrupt and Standby Status".
The exception processing vector addresses of each
interrupt factor are respectively set as shown below.
Programmable timer 1 interrupt:
Programmable timer 0 interrupt:
When the 16-bit mode is selected, the interrupt
factor flag FPT0 is not set to "1" and a timer 0
interrupt cannot be generated. (In the 16-bit mode,
the interrupt factor flag FPT1 is set to "1" by an
underflow of the 16-bit counter.
Address
Timer 1 underflow
Address
Address
Timer 0 underflow
Address
Address
Fig. 5.10.7.1 Configuration of programmable timer interrupt circuit
E0C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
000006H
000008H
Interrupt priority
register PPT0, PPT1
Interrupt factor
flag FPT1
Interrupt enable
register EPT1
Interrupt factor
flag FPT0
Interrupt enable
register EPT0
EPSON

5.10.8 Setting of TOUT output

The programmable timer can generate the TOUT
signal due to an underflow of timer 0 or timer 1.
The TOUT signal is generated from the above
mentioned underflow signal by halving the
frequency. The timer underflow which is to be used
can be selected by the TOUT output channel
selection register CHSEL. When writing "0" to
register CHSEL, timer 0 is selected and when "1" is
written, timer 1 is selected. However, in the 16-bit
mode, it is fixed in timer 1 (underflow of the 16-bit
timer) and the setting of register CHSEL becomes
invalid.
Figure 5.10.8.1 shows the TOUT signal waveform
when channel switching.
CHSEL 0
Timer 0 underflow
Timer 1 underflow
TOUT output (R27)
Fig. 5.10.8.1 TOUT signal waveform at channel change
The TOUT signal can be output from the R27
output port terminal, and the programmable clock
can be supplied to an external device.
Furthermore, the R26 output port terminal can be
used to output the TOUT signal (TOUT inverted
signal) by mask option.
The configuration of the output ports R27 and R26
is shown in Figure 5.10.8.2.
Register R27D
Register PTOUT
TOUT signal
Register R26D
Fig. 5.10.8.2 Configuration of R27 and R26
Interrupt priority
level judgement
circuit
1
R27 output
R26 output
Mask option
Interrupt
request
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