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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Controller)
When 1/32 duty is selected, since the display area
is only for one screen, the setting of DSPAR
becomes invalid.
The correspondence between the display memory
bits set according to the display area, and the
common/segment terminals are shown in Figures
5.11.5.1–5.11.5.6.
At initial reset, DSPAR is set to "0" (display area 0).
LCDC0, LCDC1: 00FF11H•D4, D5
Controls the LCD display.
Table 5.11.7.2 LCD display control
LCDC1
LCDC0
1
1
1
0
0
1
0
0
The four settings mentioned above can be made
without changing the display memory data.
At initial reset and in the SLEEP status, this register
is set to "0" (drive off).
LC0–LC3: 00FF11H•D0–D3
Adjusts the LCD contrast.
Table 5.11.7.3 LCD contract adjustment
LC3
LC2
LC1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
The contrast can be adjusted in 16 stages as men-
tioned above. This adjustment changes the drive
voltage on terminals V
C1
At initial reset, this register is set to "0".
Notes: • If external power supply has been selected
by the mask option, the contrast adjustment
register LC0–LC3 is ineffective.
• Fixing the LCD contrast is not
recommended. A contrast adjustment
function should be included in the software.
102
LCD display
All LCDs lit (Static)
All LCDs out (Dynamic)
Normal display
Drive OFF
LC0
Contrast
1
Dark
↑
0
1
0
1
0
1
0
1
0
1
0
1
0
↓
1
0
Light
–V
.
C5
5.11.8 Programming note
When the SLP instruction is executed, display
control registers LCDC0 and LCDC1 are automati-
cally reset to "0" by hardware.
EPSON
E0C88832/88862 TECHNICAL MANUAL
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