Yamaha DRX-1 Service Manual page 96

DRX-1
DV_PDN
DVCODEC Power Down
DV_RSTN
DVCODEC System Reset for NW701
DV_RWN
DVCODEC Read/Write control signal
DV_VS
DVCODEC Vertical synchronisation
FIFOA_A(0:15)
FIFO buffer A Address bus
FIFOA_OEN
FIFO buffer A Output enable
FIFOA_WEN
FIFO buffer A Write enable
HAD(0:7)
Host Address/Data bus for register settings of IC7404
INITN
Initiate Configuration
IO(0:30)
Data bus of IC7404
ISPN
In System Program Line (used for programming IC7203)
LCASN
Lower Column Address strobe for IC7404 DRAMS
LINK_AVCLK
LINK IC Audio/Video Interface Clock
LINK_AVFSYNC
LINK IC Audio/Video frame sync
LINK_AVREADY
LINK IC Audio/Video data ready to send
LINK_AVSYNC
LINK IC Audio/Video packet sync
LINK_AVVALID
LINK IC Audio/Video data valid
LINK_CSN
LINK IC chip select
LINK_INTN
LINK IC interrupt
LINKFIFO_DQ(0:7)
Audio Video data interface
PA(0:15)
SRAM processor address
PAD(0:7)
SRAM processor data
PALE
Processor Address Latch Enable
PHY_CNA
PHY 1394 cable not active
PHY_LPS
LINK IC power status
PINT0N
Processor interrupt 0
PINT1N
Processor interrupt 1
PRDN
Processor read
PROGRAMN
Low active input to initiate a configuration cycle
96
PRSTN
Processor reset
PWRN
Processor write
RASN
Row address strobe
RESETN
DVIO board reset
RTSN
System Reset
RXD
Receive Data
SRAMCE0N
SRAM processor chip enable 0
SRAMRDN
SRAM processor output enable
TCK
Boundary scan Test Clock
TDI
Boundary scan Test Data Input
TDO
Boundary scan Test Data Output
TDO_CONF
Boundary scan Test Data Output from IC 7309
TMS
Boundary scan Test Mode Select
TXD
Transmitted Data
UCASN
Upper column address strobe
WEN
Write Enable control signal to SRAM
YUV(0:7)
Digital Video