Motorola APX 5000 Service Manual page 62

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3.2.4.6 Synchronous External Memory Interface
This interfaces the OMAP to a 32 MB Double Data Rate (DDR) RAM IC (U6301). Upon boot-up
OMAP configures this interface to operate in synchronous mode at 96MHz. This volatile memory unit
is primarily accessed during code execution.
3.2.4.7 Double Data Rate (DDR) Memory (U6301)
The 32MB DDR Synchronous DRAM IC is interfaced to the OMAP using 13 address bits and a 16bit
data bus. The DDR IC is driven by a complementary clock signal originating from the OMAP IC. The
DDR clock is initialized to 96MHz by the OMAP boot code. Additional control signals are also
dedicated for the DRAM interface, as illustrated in
Board Memory Interface Circuit" on page 8-136
3.2.4.8 Multi-Media Card (MMC) Interface
The OMAP processor's MMC interface is used for a 4GB external e-MMC NAND flash memory. This
external memory is located on the expansion board. The VOCON board is connected to the
expansion board through connector J4001.
3.2.4.9 eMMC Memory
The MMC2 port interface on the OMAP processor is configured as a Secure Digital interface used for
memory modules. The memory module uses a 10bit interface, which include 4 bit wide bi-directional
data bus, command line, clock and three direction control bits. The SDIO signals are conveyed to the
expansion board via J4001. A 4GB eMMC is the only size used on the expansion board.
The Micron eMMC is a communication and mass data storage device that includes a
Multi-Media Card (MMC) interface, a NAND Flash component, and a controller on an advanced
11-signal bus, which is compliant with the MMC system specification. Its low cost, small size, Flash
technology independence, and high data throughput make e MMC ideal for smart phones, digital
cameras, PDAs, MP3 players, and other portable applications. The nonvolatile eMMC draws no
power to maintain stored data, delivers high performance across a wide range of operating
temperatures, and resists shock and vibration disruption.
The MMC specification defines the communication protocol between a host and a device. The
protocol is independent of the NAND Flash features included in the device and the device handles its
management functions internally, making them invisible to the host processor.
Micron eMMC incorporates advanced technology for defect and error management. If a defective
block is identified, the device completely replaces the defective block with one of the spare blocks.
This process is invisible to the host and does not affect data space allocated for the user. The device
also includes a built-in error correction code (ECC) algorithm to ensure that data integrity is
maintained.
The card-specific data (CSD) register provides information about accessing the device contents. The
CSD register defines the data format, error correction type, maximum data access time, and data
transfer speed, as well as whether the DS register can be used. The programmable part of the
register (entries marked with W or E in the following table) can be changed by the PROGRAM_CSD
(CMD27) command. The maximum READ and WRITE data block lengths are 512 bytes, and the
device size is 4095.
In order to accurately identify memory that is greater than 1GB, there is an additional register to
consider. The 512-byte extended card-specific data (ECSD) register defines device properties and
selected modes. The most significant 320 bytes are the properties segment. This segment defines
device capabilities and cannot be modified by the host. The lower 192 bytes are the modes segment.
The modes segment defines the configuration in which the device is working. The host can change
the properties of modes segments using the SWITCH command.
Theory of Operation
Figure 8-70. " HLN5979B/ HLN5960A Controller
.
: Controller