Figure 8-70. Hln5979B/ Hln5960A Controller Board Memory Interface Circuit - Motorola APX 5000 Service Manual

8-136
DDR INTERFACE
U6302
OMAP1710
D9
SDCLKX
C9
SDCLK
H12
SDCLK_EN
H8
NSWE
B3
SBANK_0
C3
SBANK_1
D6 H7
0
SDATA_0 CONTROL NSRAS
C6 B4
1
SDATA_1 NSCAS
2 C5 G8
SDATA_2 CS_SDRAM
3 D7 D10
SDATA_3 NSDQMU
4 D5 C8
SDATA_4 NSDQML
5 C7 C14
SDATA_5 DSQ_H
6 C4 D4
SDATA_6 DSQ_L
7 D8 A2
SDATA_7 SADD_0
8 C10 B2
SDATA_8 DATA SADD_1
9 D14 B6
SDATA_9 SADD_2
10 D11 A1
SDATA_10 SADD_3
11 C13 G10
SDATA_11 SADD_4
12 C11 B9
SDATA_12 SADD_5
13 D13 G12
SDATA_13 SADD_6
14 D12 G11
SDATA_14 ADDRESS SADD_7
15 C12 G9
SDATA_15 SADD_8
B12
SADD_9
B8
SADD_10
H10
SADD_11
H9
SADD_12
H11
SADD_13
DDR_DATA<17..0>
MMC INTERFACE
F2_TIMER_OUT
U6302
V11
MMC1_CLK
M15
OMAP1710
MMC1_CLKIN
P11
MMC1_CMD
P19
MMC1_CMDDIR
P20
MMC1_DATDIR0
P18
OPTION CARD INTF MMC1_DATDIR1
M14
MMC1_DATDIR2
R18
MMC1_DATDIR3
R11
MMC1_DAT0
V10
MMC1_DAT1
W10
MMC1_DAT2
W11
MMC1_DAT3
Y10
MMC2_CLK
Y8
MMC2_CMD
V9
MMC2_CMDDIR
V5
MMC2_DATDIR0
MEMORY CARD INTF
W19
MMC2_DATDIR1
W8
MMC2_DAT0
V8
MMC2_DAT1
W15
MMC2_DAT2
R10
MMC2_DAT3
R6302
R6303 DNP

Figure 8-70. HLN5979B/ HLN5960A Controller Board Memory Interface Circuit

V_EXT_1.85
R6301 TP6307
10K TEST_POINT
DNP
TP6308
TEST_POINT
DNP U6301
MT46H16M16LF
DDR_CLKX_1
DDR_CLK_1 G2
CLK
DDR_CLKE G3
CLK*
DDR_WE 0 G1
EN_CLKE
DDR_BANK0 1
DDR_BANK1 DDR_WE G7
2 0 WE
DDR_RAS DDR_CAS G8
3 4 CAS
DDR_CAS DDR_RAS G9
4 3 RAS
DDR_CS DDR_CRTL<6..0> DDR_CS H7
5 5
EN_CS
DDR_UDM
DDR_LDM 1 DDR_BANK0 H8
BA0
DDR_DQSH 2 H9
BA1
DDR_DQSL 0 J8
A0
0 1 J9
A1
1 2 DDR_ADDR<2> K7
A2
2 3 DDR_ADDR<3> K8
A3
3 4 DDR_ADDR<4> K2
A4
4 5 DDR_ADDR<5> K3
A5
5 6 DDR_ADDR<6> J1
A6
6 7 DDR_ADDR<7> J2
A7
7 8 DDR_ADDR<8> J3
A8
8 9 DDR_ADDR<9> H1
A9
9 10 DDR_ADDR<10> J7
A10_AP
10 11 DDR_ADDR<11> H2
A11
DDR_ADDR<12> H3
11 12 A12
DDR_UDM F2
12 UDM
DDR_LDM F8
13 LDM
DDR_ADDR<13..0>
13
TP6301
TEST_POINT
1
DNP
AVR_STATUS_1.8
IN
R6307
0
R6305
10
0
1
2
3
4
5
DNP
100K MMC<5..0>
IO
100K
DNP
1
TP6304
TP6303 DNP
TEST_POINT
1
TEST_POINT
E2 DDR_DQSH
UDQS
E8 DDR_DQSL
LDQS
A8 0 DDR_DATA<0>
DQ0
B7 DDR_DATA<1>
1
DQ1
B8 DDR_DATA<2>
2
DQ2
C7 DDR_DATA<3>
3
DQ3
C8 DDR_DATA<4>
4
DQ4
D7 5 DDR_DATA<5>
DQ5
D8 6 DDR_DATA<6>
DQ6
E7 7 DDR_DATA<7>
DQ7
E3 8 DDR_DATA<8>
DQ8
D2 9 DDR_DATA<9>
DQ9
D3 10 DDR_DATA<10>
DQ10
C2 11 DDR_DATA<11>
DQ11
C3 12 DDR_DATA<12>
DQ12
B2 13 DDR_DATA<13>
DQ13
B3 14 DDR_DATA<14>
DQ14
A2 15 DDR_DATA<15>
DQ15
F3
NC1 NC
F7 FLASH INTERFACE
NC2
OUT
PA_SHTDN
R6308
1.8K
0 1 TP6305 DNP
TEST_POINT
U6302
8 1
OMAP1710
TP6306 DNP
TEST_POINT
L4
NF_ADV
M7
NFCS_0
M3
NFCS_1
M4
NFCS_2
N8
NFCS_3
U4
NFOE
CONTROL
W1
NFRP
W2
NFWE
V4
NFWP
N4 N3
0
FDATA_0 FCLK
N2 V2
1
FDATA_1 FRDY
N7 J8
2
FDATA_2 FADD_1
P2
3 D3
FDATA_3 FADD_2
4 P4 C1
FDATA_4 FADD_3
5 P7 E4
FDATA_5 FADD_4
6 R2 D2
FDATA_6 FADD_5
7 R3 F4
FDATA_7 FADD_6
8 R4 E3
FDATA_8 DATA FADD_7
9 T2 J7
FDATA_9 FADD_8
10 T3 F3
FDATA_10 FADD_9
11 P8 G4
FDATA_11 FADD_10
12 U1 G3
FDATA_12 FADD_11
13 U3 G2
FDATA_13 FADD_12
14 T4 K8
FDATA_14 ADDRESS FADD_13
15 V3 H4
FDATA_15 FADD_14
H3
FADD_15
K7
FADD_16
J2
FADD_17
J4
FADD_18
J3
FADD_19
F2
FADD_20
L8
FADD_21
K4
FADD_22
K3
FADD_23
L7
FADD_24
E1
FADD_25
FLASH_DATA<15..0>
Schematics, Boards Overlays, and Parts Lists: Controller Board
V_EXT_1.85
V_EXT_1.85
R6316
10K
FLASH_CTRL<8..0>
R6304
0
7 FLASH_RDY V_FLASH
V_EXT_1.85
R6306
10K
U6304
R6314
6 R6310 33
33
0
1 R6311 33 E6
CLK
B4
CE
WAIT
FLASH_OE_A
2 F8
OE
8 4 R6313 33 G8
WE DQ0
PC28F512P30BF
TP6302 1 3 D4
TEST_POINT RST DQ1
DNP
1 C6
WP DQ2
R6312 33 2 0 F6
ADV DQ3
3
DQ4
4
DQ5
1 A1
A1 DQ6
B1
6 2 A2 DQ7
C1
7 3 A3
D1
1 4 A4 DQ8
D2
2 5 A5 DQ9
3 6 A2
A6 DQ10
4 7 C2
A7 DQ11
5 8 A3
A8 DQ12
6 9 B3
A9 DQ13
7 10 C3
A10 DQ14
8 11 D3
A11 DQ15
9 12 C4
A12
10 13 A5
A13
11 14 B5
A14 RFU1
12 15 C5
A15 RFU2
13 16 D7
A16 RFU3
14 17 D8
A17 RFU4
15 18 A7
A18
16 19 B7
A19
17 20 C7
A20
C8
18 21 A21
A8
19 22 A22
G1
20 23 A23
21 24 H8 A24
22 25 B6
A25_512M
23 B8
A26_1G
NC
24
25
FLASH_ADDR<25..1>
C6308 C6309 C6310 C6311
0.1UF 0.1UF 0.1UF 0.1UF
F7
F2 0
E2 1
G3 2
E4 3
E5 4
G5 5
G6 6
H7
7
E1
8
E3
9
F3 10
F4 11
F5 12
H5 13
G7 14
E7 15
E8
NC
F1
NC
G2
NC
H1
NC