Winbond W83627DHG Manuals

Winbond W83627DHG Manuals

Manuals and User Guides for Winbond W83627DHG. We have 1 Winbond W83627DHG manual available for free PDF download: Manual

Winbond W83627DHG Manual

Winbond W83627DHG Manual (268 pages)

Low Pin Count interface

Brand: Winbond | Category: I/O Systems | Size: 1.8 MB

Table of Contents

Table of Contents
6
1 General Description

13
2 Features

14
3 Block Diagram

17
4 Pin Layout

18
5 Pin Description

20
- LPC Interface
  21
- FDC Interface
  21
- Multi-Mode Parallel Port
  22
- Serial Port & Infrared Port Interface
  24
- KBC Interface
  26
- Serial Peripheral Interface
  26
- Hardware Monitor Interface
  27
- PECI Interface
  29
- SST Interface
  29
- Advanced Configuration and Power Interface
  29
- General Purpose I/O Port
  30
  - Smbus Interface
    30
  - GPIO Power Source
    30
  - GPIO-2 Interface
    31
  - GPIO-3 Interface
    32
  - GPIO-4 Interface
    32
  - GPIO-5 Interface
    33
  - GPIO-6 Interface
    33
  - GPIO-4 with WDTO# / SUSLED Multi-Function
    34
- Particular ACPI Function Pins - both for UBE and UBF Version Only
  34
- Power Pins
  35
6 Configuration Register Access Protocol

36
- Configuration Sequence
  37
7 Hardware Monitor

40
- General Description
  40
- Access Interfaces
  40
  - LPC Interface
    41
  - C Interface
    42
- Analog Inputs
  43
- SST Command Summary
  46
  - Command Summary
    46
  - Combination Sensor Data Format
    47
- Peci
  48
- Fan Speed Measurement and Control
  51
  - Fan Speed Measurement
    51
  - Fan Speed Control
    52
  - SMART FAN TM Control
    53
- Interrupt Detection
  62
  - SMI# Interrupt Mode
    62
  - OVT# Interrupt Mode
    65
  - Caseopen Detection
    66
  - BEEP Alarm Function
    67
8 Hardware Monitor Register Set

68
9 Serial Peripheral Interface

120
- Using the SPI Interface Via the LPC
  120
10 Floppy Disk Controller

123
- FDC Functional Description
  123
  - FIFO (Data)
    123
  - Data Separator
    124
  - Write Precompensation
    124
  - Perpendicular Recording Mode
    124
  - FDC Core
    124
  - FDC Commands
    125
- Register Descriptions
  136
11 Uart Port

148
- Universal Asynchronous Receiver/Transmitter (UART A, UART B)
  148
- Register Description
  148
12 Parallel Port

157
- Printer Interface Logic
  157
- Enhanced Parallel Port (EPP)
  158
  - Data Port (Data Swapper)
    159
  - Printer Status Buffer
    159
  - Printer Control Latch and Printer Control Swapper
    159
  - EPP Address Port
    160
  - EPP Data Port 0-3
    160
  - EPP Pin Descriptions
    161
  - EPP Operation
    161
- Extended Capabilities Parallel (ECP) Port
  162
  - ECP Register and Bit Map
    163
  - Data and Ecpafifo Port
    164
  - Device Status Register (DSR)
    164
  - Device Control Register (DCR)
    165
  - CFIFO (Parallel Port Data FIFO) Mode = 010
    165
  - ECPDFIFO (ECP Data FIFO) Mode = 011
    165
  - TFIFO (Test FIFO Mode) Mode = 110
    166
  - CNFGA (Configuration Register A) Mode = 111
    166
  - CNFGB (Configuration Register B) Mode = 111
    166
  - ECR (Extended Control Register) Mode = All
    167
  - ECP Pin Descriptions
    168
  - ECP Operation
    169
  - FIFO Operation
    170
  - DMA Transfers
    170
  - Programmed I/O (NON-DMA) Mode
    170
13 Keyboard Controller

171
- Output Buffer
  171
- Input Buffer
  171
- Status Register
  172
- Commands
  172
- Hardware Gatea20/Keyboard Reset Control Logic
  174
  - KB Control Register
    174
  - Port 92 Control Register
    175
14 Power Management Event

176
- Power Control Logic
  176
  - PSON# Logic
    177
  - AC Power Failure Resume
    178
- Wake up the System by Keyboard and Mouse
  179
  - Waken up by Keyboard Events
    179
  - Waken up by Mouse Events
    179
- Resume Reset Logic
  180
- PWROK Generation
  181
  - The Relation Among PWROK/PWROK2, ATXPGD and FTPRST# - both for UBE and UBF Version Only
    182
15 Serialized Irq

185
- Start Frame
  185
- Irq/Data Frame
  186
- Stop Frame
  187
16 Watchdog Timer

188
17 General Purpose I/O

189
18 VID Inputs and Outputs

190
- VID Input Detection
  190
- VID Output Control
  190
19 Pci Reset Buffers

191
20 Configuration Register

192
- Chip (Global) Control Register
  192
- Logical Device 0 (FDC)
  199
- Logical Device 1 (Parallel Port)
  202
- Logical Device 2 (UART A)
  203
- Logical Device 3 (UART B)
  203
- Logical Device 5 (Keyboard Controller)
  205
- Logical Device 6 (Serial Peripheral Interface)
  206
- Logical Device 7 (GPIO6)
  207
- Logical Device 8 (WDTO# & PLED)
  208
- Logical Device 9 (GPIO2, GPIO3, GPIO4, GPIO5)
  210
- Logical Device a (ACPI)
  214
- Logical Device B (Hardware Monitor)
  222
- Logical Device C (PECI, SST)
  224
21 Specifications

228
- Absolute Maximum Ratings
  228
- DC Characteristics
  228
- Ac Characteristics
  237
  - AC Power Failure Resume Timing
    237
  - VSBGATE# Timing - for UBE and UBF Version Only
    242
  - Clock Input Timing
    243
  - PECI and SST Timing
    244
  - SPI Timing
    245
  - Smbus Timing
    246
  - Floppy Disk Drive Timing
    247
  - Uart/Parallel Port
    248
  - Parallel Port Mode Parameters
    250
  - Parallel Port
    251
  - KBC Timing Parameters
    260
  - GPIO Timing Parameters
    263
- LPC Timing
  265
22 Top Marking Specification

266
23 Package Specification

267

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