Page 1 查询W83627DHG供应商捷多邦，专业PCB打样工厂，24小时加急出货 www.DataSheet4U.com www.DataSheet4U.com W83627DHG WINBOND LPC I/O Note: This document is for UBC, UBE and UBF version except specified descriptions Date : April 10, 2007 Version : 1.4...
Page 3 W83627DHG Data Sheet Revision History PAGES DATES VERSION MAIN CONTENTS VERSION N.A. N.A. 12/15/2005 First published version. Add descriptions of the registers, functions,, AC/DC N.A. 02/22/2006 N.A. timing, and top marking Revise Table 8.1 and the timing chart of section 10.3.1...
Page 4 Power Management, Serialized IRQ, Watchdog Timer VID Inputs and Outputs, and PCI Reset Buffers. Update the feature lists of the W83627DHG in Chapter 2 Features. Add descriptions of PECI and SST and a table of SMBus in Chapter 5 Pin Description.
Page 5 These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Page 6: Table Of Contents
W83627DHG Table of Contents- 1. GENERAL DESCRIPTION ....................... 1 2. FEATURES............................2 3. BLOCK DIAGRAM ..........................5 4. PIN LAYOUT............................. 6 5. PIN DESCRIPTION .......................... 8 LPC Interface .......................... 9 FDC Interface .......................... 9 Multi-Mode Parallel Port......................10 Serial Port & Infrared Port Interface..................12 KBC Interface ........................
Page 7 W83627DHG 7.3.3 Temperature Sensing......................32 SST Command Summary ..................... 34 7.4.1 Command Summary ......................34 7.4.2 Combination Sensor Data Format..................35 PECI ............................36 Fan Speed Measurement and Control.................. 39 7.6.1 Fan Speed Measurement.......................39 7.6.2 Fan Speed Control .........................40 7.6.3 SMART FAN Control ......................41 Interrupt Detection.........................
Page 8 8.43 FAN IN/OUT Control Register - Index 4Dh (Bank 0) ............80 8.44 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0) .......... 81 8.45 Winbond Vendor ID Register - Index 4Fh (Bank 0) .............. 81 8.46 Reserved Register - Index 50h ~ 55h (Bank 0) ..............82 8.47 BEEP Control Register 1 - Index 56h (Bank 0)..............
Page 9 W83627DHG 8.67 CPUFANOUT0 Critical Temperature Register - Index 6Ch (Bank 0) ........93 8.68 AUXFANOUT Critical Temperature Register - Index 6Dh (Bank 0) ........93 8.69 CPUFANOUT1 Critical Temperature Register - Index 6Eh (Bank 0) ........94 8.70 CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1)..94 8.71 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1) ..
Page 10 W83627DHG 10.1.6 FDC Commands ........................113 10.2 Register Descriptions ......................124 10.2.1 Status Register A (SA Register) (Read base address + 0) ..........124 10.2.2 Status Register B (SB Register) (Read base address + 1) ..........126 10.2.3 Digital Output Register (DO Register) (Write base address + 2)..........128 10.2.4...
Page 11 W83627DHG 12.3.10 ECR (Extended Control Register) Mode = all ..............155 12.3.11 ECP Pin Descriptions......................156 12.3.12 ECP Operation........................157 12.3.13 FIFO Operation ........................158 12.3.14 DMA Transfers........................158 12.3.15 Programmed I/O (NON-DMA) Mode ..................158 13. KEYBOARD CONTROLLER ......................159 13.1 Output Buffer ........................159 13.2 Input Buffer..........................
Page 12 W83627DHG 20.7 Logical Device 6 (Serial Peripheral Interface)..............194 20.8 Logical Device 7 (GPIO6) ....................195 20.9 Logical Device 8 (WDTO# & PLED) ................... 196 20.10 Logical Device 9 (GPIO2, GPIO3, GPIO4, GPIO5) ............198 20.11 Logical Device A (ACPI)...................... 202 20.12 Logical Device B (Hardware Monitor) .................
Page 13: General Description
W83627DHG GENERAL DESCRIPTION The W83627DHG is a member of Winbond's Super I/O product line. This family features the LPC (Low Pin Count) interface. This interface is more economical than its ISA counterpart, in that it has approximately forty pins fewer, yet still provides as great performance. In addition, the improvement allows even more efficient operation of software, BIOS and device drivers.
Page 14: Features
W83627DHG FEATURES General Meet LPC Spec. 1.01 Support LDRQ# (LPC DMA), SERIRQ (Serialized IRQ) Integrated hardware monitor functions Compliant with Microsoft PC98/PC99/PC2001 System Design Guide Support DPM (Device Power Management), ACPI (Advanced Configuration and Power Interface) Programmable configuration settings Single 24- or 48-MHz clock input...
Page 15 Built-in case open detection circuit Programmable hysteresis and setting points for all monitored items Over-temperature indicator output Issue SMI#, OVT# to activate system protection Winbond Hardware Doctor support Eight VID inputs / outputs Provide I C interface to read / write registers...
Page 16 W83627DHG Infrared • Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps • Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps General Purpose I/O Ports 40 programmable general purpose I/O ports...
Page 17: Block Diagram
W83627DHG BLOCK DIAGRAM LRESET#, PCICLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ Interface Floppy drive Interface interface signals SMBus UARTA interface UARTA Interface signals UARTB interface signals General-purpose UARTB GPIO I/O pins Infrared interface signals Hardware Monitor Printer port channel and Vref interface signals...
Page 18: Pin Layout
AFD# AFD# VID7 VID7 ERR# ERR# VID6 VID6 INIT# INIT# VID5 VID5 SLIN# SLIN# VID4 VID4 VID3 VID3 VID2 VID2 VID1 VID1 3VCC 3VCC VID0 VID0 Pin Layout for W83627DHG UBC version Publication Release Date: Aug, 22, 2007 Version 1.4...
Page 19 CPUFANOUT0 RTSA#/GP65(HEFRAS) SYSFANOUT DSRA#/GP66 (FAN_SET)PLED CTSA#/GP67 BEEP/SO 3VCC GP21/CPUFANIN1 STB# GP20/CPUFANOUT1 AFD# VID7 ERR# VID6 INIT# VID5 SLIN# VID4 VID3 VID2 VID1 3VCC VID0 Pin Layout for W83627DHG UBE and UBF version Publication Release Date: Aug, 22, 2007 Version 1.4...
Page 20: Pin Description
W83627DHG PIN DESCRIPTION Note: Please refer to Section 21.2 DC CHARACTERISTICS for details. AOUT - Analog output pin - Analog input pin - CMOS-level input pin with internal pull-down resistor - CMOS-level, Schmitt-trigger input pin - CMOS-level, Schmitt-trigger input pin with internal pull-up resistor...
Page 21: Lpc Interface
W83627DHG LPC Interface SYMBOL DESCRIPTION System clock input, either 24MHz or 48MHz. The actual frequency IOCLK must be specified in the register. The default value is 48MHz. PME# Generated PME event. 12p3 PCICLK PCI-clock 33-MHz input. tsp3 LDRQ# Encoded DMA Request signal.
Page 22: Multi-Mode Parallel Port
W83627DHG FDC Interface, continued SYMBOL DESCRIPTION Write protected. This active-low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin needs to connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive compatibility. The read-data input signal from the FDD. This input pin needs to RDATA# connect a pulled-up 1-KΩ...
Page 23 W83627DHG Multi-Mode Parallel Port, continued. SYMBOL DESCRIPTION PRINTER MODE: INIT# INIT# Output line for the printer initialization. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: AFD# An active-low output from this pin causes the printer to auto feed a AFD# line after a line is printed.
Page 24: Serial Port & Infrared Port Interface
W83627DHG Serial Port & Infrared Port Interface SYMBOL DESCRIPTION Ring Indicator. An active-low signal indicates that a ring signal is RIA# being received from the modem or the data set. GP60 I/OD General-purpose I/O port 6 bit 0. Data Carrier Detection. An active-low signal indicates the modem DCDA# or data set has detected a data carrier.
Page 25 Note: This pin changes to input state during internal PWROK from GP42* low to high, then goes back to the previous setting state. (Please see the AP Note 1 of W83627DHG) Serial Input. This pin is used to receive serial data through the SINB communication link.
Page 26: Kbc Interface
To initiate the data transfer between the W83627DHG and a slave device, SCE# must go low. This synchronizes the slave device with the W83627DHG. Data can now be transferred between the W83627DHG and the slave device in one of two modes: the data is sampled either on the rising or the falling edge of the clock.
Page 27: Hardware Monitor Interface
SI of serial flash. CASE OPEN detection. An active-low input from an external device when the case is open. This signal can be latched if pin VBAT is connected to the battery, even if the W83627DHG is CASEOPEN# turned off.
Page 28 W83627DHG Hardware Monitor Interface, continued. SYMBOL DESCRIPTION The input of temperature sensor 1. It is used for system SYSTIN temperature sensing. The output of over temperature Shutdown. This pin indicates OVT# the temperature is over the temperature limit. (Default after...
Page 29: Peci Interface
Two of the primary states that the W83627DHG supports are the S0 (working) and S3 (suspend to RAM) states. S0 is a full-power state, in which the computer is actively used. S3 is a sleeping state, in which the processor is powered down, but the memory, where the last procedural state is stored, is still active.
Page 30: General Purpose I/O Port
W83627DHG Continued SYMBOL DESCRIPTION RSTOUT0# PCI Reset Buffer 0. RSTOUT1# PCI Reset Buffer 1. RSTOUT2# PCI Reset Buffer 2. (Default) GP32 I/OD General-purpose I/O port 3 bit 2. Serial Bus clock. RSTOUT3# PCI Reset Buffer 3. (Default) GP33 I/OD General-purpose I/O port 3 bit 3.
Page 31: Gpio-2 Interface
W83627DHG 5.11.3 GPIO-2 Interface SYMBOL DESCRIPTION GP20 I/OD General-purpose I/O port 2 bit 0. AOUT/ DC/PWM fan output control. (Default) CPUFANOUT1 CPUFANOUT0 and AUXFANOUT are default PWM mode, CPUFANOUT1 and SYSFANOUT are default DC mode. GP21 I/OD General-purpose I/O port 2 bit 1.
Page 32: Gpio-3 Interface
W83627DHG 5.11.4 GPIO-3 Interface SYMBOL DESCRIPTION RSTOUT0# PCI Reset Buffer 0. RSTOUT1# PCI Reset Buffer 1. GP30 I/OD General-purpose I/O port 3 bit 0. This pin generates the PWROK2 signal while 3VCC comes in. PWROK2 (This pin function is both for UBE and UBF version only)
Page 33: Gpio-5 Interface
W83627DHG 5.11.6 GPIO-5 Interface SYMBOL DESCRIPTION GP50 General-purpose I/O port 5 bit 0. (Default after strapping) During VSB power reset (RSMRST), this pin is pulled high internally and is defined as VID transition voltage level (GTL or TTL), and the value is shown at CR2C bit 3. The PCB layout EN_GTL should reserve space for a 1-kΩ...
Page 34: Gpio-4 With Wdto# / Susled Multi-Function
W83627DHG 5.11.8 GPIO-4 with WDTO# / SUSLED Multi-function SYMBOL DESCRIPTION GPxx* I/OD This GPxx* can serve as GPIO or the Watchdog Timer output signals. WDTO# GPxx*** I/OD This GPxx*** can serve as GPIO or Suspend-LED output signals. SUSLED 5.12 Particular ACPI Function pins – both for UBE and UBF Version Only...
Page 35: Power Pins
W83627DHG 5.13 POWER PINS SYMBOL DESCRIPTION 3VSB +3.3 V stand-by power supply for the digital circuits. VBAT +3 V on-board battery for the digital circuits. 3VCC 12,28,48 +3.3 V power supply for driving 3 V on host interface. Analog +3.3 V power input. Internally supply power to all analog AVCC circuits.
Page 36: Configuration Register Access Protocol
W83627DHG CONFIGURATION REGISTER ACCESS PROTOCOL The W83627DHG uses Super I/O protocol to access configuration registers to set up different types of configurations. The W83627DHG has totally twelve Logical Devices (from Logical Device 0 to Logical Device C with the exception of Logical Device 4 for backward compatibility) corresponding to twelve...
Page 37: Configuration Sequence
“87h”? Extended Function Extended Function Mode Mode To program the W83627DHG configuration registers, the following configuration procedures must be followed in sequence: (1). Enter the Extended Function Mode. (2). Configure the configuration registers. (3). Exit the Extended Function Mode. 6.1.1...
Page 38: Exit The Extended Function Mode
W83627DHG 6.1.3 Exit the Extended Function Mode To exit the Extended Function Mode, writing 0xAA to the EFER is required. Once the chip exits the Extended Function Mode, it is in the normal running mode and is ready to enter the configuration mode.
Page 39 W83627DHG Chip (Global) Control Registers INDEX DEFAULT VALUE DESCRIPTION Write Only Software Reset Logical Device Read Only Chip ID, MSB Read Only Chip ID, LSB Device Power Down Immediate Power Down 0100_0ss0b Global Option Interface Tri-state Enable 0s000000b Global Option...
Page 40: Hardware Monitor
Winbond’s Hardware Doctor , or BIOS. In addition, the W83627DHG can generate pop-up warnings or beep tones when a parameter goes outside of a user-specified range. The rest of this section introduces the various features of the W83627DHG hardware-monitor capability.
Page 41: Lpc Interface
Read Time Status Read Time Status Read Time Status Port 6h Port 6h Port 6h Port 6h Registers Registers Registers Registers Winbond Vendor ID Winbond Vendor ID Winbond Vendor ID Winbond Vendor ID 59h~5Bh 59h~5Bh 59h~5Bh 59h~5Bh Data Data Data...
Page 42: C Interface
7.2.2 C interface This interface uses the I C Serial Bus to access the internal registers. The W83627DHG has a programmable serial-bus address that is controlled by index 48h. The two timing diagrams below illustrate how to use the I C interface to write to an internal register and how to read the value in an internal register, respectively.
Page 43: Analog Inputs
W83627DHG Analog Inputs The maximum input voltage on analog pins is 2.048 V because the 8-bit ADC has an 8-mV LSB. Usually, the voltage ports of CPU Vcore (pin 100), battery (pin 74), 3VSB (pin 61), 3VCC (pin 12), and AVCC (pin 95) can be directly connected to their respective analog pins, as illustrated in the figure below.
Page 44: Voltage Detection
The W83627DHG uses the same approach. Pins 12 and 95 provide two functions. One, these pins are connected to VCC at +3.3 V to supply internal (digital / analog) power to the W83627DHG. Two, these pins monitor VCC. The W83627DHG has two internal, 34-KΩ serial resistors that reduce the ADC-input voltage to 1.65 V.
Page 45 The thermal diode D- pin is connected to CPUD-(pin 105), and the D+ pin is connected to the temperature sensor pin in the W83627DHG. A 15-KΩ resistor is connected to VREF to supply the bias current for the diode, and the 2200-pF, bypass capacitor is added to filter high-frequency noise.
Page 46: Sst Command Summary
W83627DHG 7.3.3.3. Monitor Temperature from Thermal Diode (Current Mode) The W83627DHG can also sense the diode temperature through Current Mode and the circuit is shown in the following figure. W83627DHG (SYSTIN) CPUTIN (AUXTIN) Thermal C=2200pF Diode CPUD-(AGND) The pin of processor D- is connected to CPUD-(pin 105) and the pin D+ is connected to temperature sensor pin in the W83627DHG.
Page 47: Combination Sensor Data Format
FEC0h 7.4.2.2. Voltage Data Format The W83627DHG can return five (5) voltage values through the SST interface. The voltage data format is 16-bit two’s-complement binary. The relation between the 2-byte data and the monitored voltage is listed below: 1) CPUVCORE (pin 100) = Decimal[2-byte data by GetVoltVccp() ] / 1024 volts 2) 3VCC (pin 12) = Decimal[2-byte data by GetVolt3p3V()] / 1024 volts 3) “+12V”...
Page 48: Peci
4. Program Logical Device C, CR[E0h] bit (7..4) for each PECI Agent. Setting to “1” enables the W83627DHG to access the agent. The power-on default is disabled. After an agent is enabled, the W83627DHG issues PING and GetTemp commands to obtain the PECI temperature...
Page 49 8. In addition, the W83627DHG provides a PECISB pin that can be connected to a PECI host (e.g. chipset), so the W83627DHG becomes a bridge between that PECI host and the PECI client (e.g. CPU with PECI function).
Page 50 9. A warning flag register at Logical Device C, CR[E8h] bit (7..4) is designed for each PECI Agent to report whether the W83627DHG (PECI host) detects the PECI client or not and whether the PECI client returns invalid FCS values from the polling for three successive times.
Page 51: Fan Speed Measurement And Control
7.6.1 Fan Speed Measurement The W83627DHG can measure fan speed for fans equipped with tachometer outputs. The tachometer signals should be set to TTL-level, and the maximum input voltage cannot exceed +3.3 V. If the tachometer signal exceeds +3.3 V, an external trimming circuit should be added to reduce the voltage accordingly.
Page 52: Fan Speed Control
Fan Speed Control The W83627DHG has four output pins for fan control, each of which offers PWM duty cycle and DC voltage to control the fan speed. The output type (PWM or DC) of each pin is configured by Bank0 Index 04h, bits 1 ~ 0;...
Page 53: Smart Fan Tm Control
W83627DHG 7.6.3 Control MART The W83627DHG supports two S I features—Thermal Cruise mode and Fan Speed MART Cruise mode—and S III. Each of these is discussed in the following sections. When MART enabling S I features, fan output starts from the previous setting in Bank0 Index 01h, Index...
Page 54 W83627DHG Thermal Cruise mode controls the fan speed to keep the temperature in a specified range. First, this range is defined in BIOS by a temperature and the interval (e.g., 55 °C ± 3 °C). As long as the current temperature remains below the low end of this range (i.e., 52 °C), the fan is off.
Page 55 W83627DHG 7.6.3.2. Fan Speed Cruise Mode Four pairs of fan input sensors and fan outputs in Fan Speed Cruise mode. • SYSFANIN and SYSFANOUT • CPUFANIN0 and the temperature sensor selected by Bank0 Index 49h, bits 2 ~ 0 •...
Page 56 W83627DHG Count output The following tables show current temperatures, fan output values and the relative control registers at Thermal Cruise and Fan Speed Cruise mode. Display Registers - at S I Mode MART REGISTER DESCRIPTION REGISTER NAME ATTRIBUTE BIT DATA...
Page 57 W83627DHG Relative Registers - at Thermal Cruise Mode KEEP MIN. STEP- THERMAL-CRUI TARGET START-UP STOP STOP STEP-UP TOLERANCE DOWN TEMPERATURE VALUE VALUE OUTPUT TIME TIME MODE TIME VALUE Bank0, 07h Bank0, Bank0, Bank0, 12h, Bank0, SYSFANOUT Bank0, 05h Bit5 Bit0-3...
Page 58 W83627DHG 7.6.3.3. MART III controls the fan speed so that the temperature meets the target temperature set in MART BIOS or application software. There are only two pairs of fan outputs and temperature sensors in III mode. MART • CPUFANOUT0 and the temperature sensor selected by Bank0 Index 49h, bits 2 ~ 0 •...
Page 59 W83627DHG Setting Setting Setting Fan output Fan output Fan output Tolerance Tolerance Tolerance (DC / PWM) (DC / PWM) (DC / PWM) Max. Fan Output Max. Fan Output Max. Fan Output Min. Fan Output Min. Fan Output Min. Fan Output Tar.
Page 60 W83627DHG If the current temperature rises higher than (Target Temperature 1 + Temperature Tolerance), the fan speed rises one step again, and the target temperature shifts to (Target Temperature 1 + Temperature Tolerance), or Target Temperature 2. This process repeats whenever the current temperature is higher than (Target Temperature X ±...
Page 61 W83627DHG The following tables show current temperatures, fan output values and the relative control registers at III mode. MART Display Register- at S III Mode MART REGISTER DESCRIPTION REGISTER NAME ATTRIBUTE BIT DATA ADDRESS Bank1 Index Current CPU CPUTIN Temperature 8 MSB, 1°C bit 7,...
Page 62: Interrupt Detection
W83627DHG Interrupt Detection 7.7.1 SMI# Interrupt Mode The SMI#/OVT# pin (pin 5) is a multi-function pin. It can be in SMI# mode or in OVT# mode by setting Configuration Register CR[29h], bit 6 to one or zero, respectively. In SMI# mode, it can monitor voltages, fan counts, or temperatures.
Page 63 W83627DHG HYST 127'C HYST SMI# SMI# *Interrupt Reset when Interrupt Status Registers are read Comparator Interrupt Mode Two-Time Interrupt Mode (2) Two-Time Interrupt Mode This mode is enabled by setting T (Temperature Hysteresis) lower than T and setting Bank0 HYST Index 4Ch, bit 5 to zero.
Page 64 W83627DHG HYST SMI# *Interrupt Reset when Interrupt Status Registers are read One-Time Interrupt Mode 7.7.1.3.2. Temperature Sensor 2(CPUTIN) And Sensor 3(AUXTIN) SMI# Interrupt The SMI# pin has two interrupt modes with CPUTIN / AUXTIN. (1) Comparator Interrupt Mode This mode is enabled by setting Bank0 Index 4Ch, bit 6, to one.
Page 65: Ovt# Interrupt Mode
W83627DHG (2) Two-Times Interrupt Mode This mode is enabled by setting Bank0 Index 4Ch, bit 6, to zero. In this mode, the SMI# pin can create an interrupt when the current temperature rises above T when the current temperature falls below T .
Page 66: Caseopen Detection
W83627DHG 7.7.3 Caseopen Detection The purpose of Caseopen function is used to detect whether the computer case is opened. This feature must be able to function even when there is no 3VSB power. Consequently, the power source for the circuit is from either Pin 74 (VBAT) or Pin 61 (3VSB). 3VSB is the default power source. If there is no 3VSB power, the power source is VBAT.
Page 67: Beep Alarm Function
W83627DHG 7.7.4 BEEP Alarm Function The W83627DHG provides an alarm output function at the BEEP/SO pin. The BEEP/SO pin is a multi-function pin and can be configured as BEEP output, if Configuration Register CR[24h], bit 1 is set to zero.
Page 68: Hardware Monitor Register Set
W83627DHG HARDWARE MONITOR REGISTER SET The base address of the Address Port and Data Port is specified in registers CR60 and CR61 of Device B, the hardware monitor device. CR60 is the high byte, and CR61 is the low byte. The Address Port and Data Port are located at the base address, plus 5h and 6h, respectively.
Page 69: Sysfanout Pwm Output Frequency Configuration Register - Index 00H (Bank 0)
W83627DHG SYSFANOUT PWM Output Frequency Configuration Register - Index 00h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits PWM_SCALE1 PWM_CLK_SEL1 The register is meaningful only when SYSFANOUT is programmed for PWM output ( i.e., Bank0 Index 04h, bit 0 is 0).
Page 70: Cpufanout0 Pwm Output Frequency Configuration Register - Index 02H (Bank 0)
W83627DHG (1)If SYSFANOUT is programmed for PWM output (Bank0 Index 04h,bit0 is 0) Bit 7-0: The PWM duty cycle is equal to this eight-bit value, divided by 255, times 100%. FFh creates a duty cycle of 100%, and 00h creates a duty cycle of 0%.
Page 71: Cpufanout0 Output Value Select Register - Index 03H (Bank 0)
W83627DHG CPUFANOUT0 Output Value Select Register - Index 03h (Bank 0) Register Location: Power on Default Value: Strap by FAN_SET(Pin 117) Attribute: Read/Write Size: 8 bits CPUFANOUT0 Value (1)If CPUFANOUT0 is programmed for PWM output (Bank0 Index 04h,bit1 is 0) Bit 7-0: CPUFANOUT0 PWM Duty Cycle.
Page 72: Systin Target Temperature Register/ Sysfanin Target Speed Register - Index 05H
W83627DHG Bit 7-6: Reserved Bit 5-4: CPUFANOUT0 mode control. 00: CPUFANOUT0 is in Manual Mode. (Default) 01: CPUFANOUT0 is in Thermal Cruise Mode. 10: CPUFANOUT0 is in Fan Speed Cruise Mode. 11: CPUFANOUT0 is in S III Mode. MART Bit 3-2: SYSFANOUT mode control.
Page 73: Cputin Target Temperature Register/ Cpufanin0 Target Speed Register - Index 06H (Bank 0)
W83627DHG CPUTIN Target Temperature Register/ CPUFANIN0 Target Speed Register - Index 06h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits Target Temperature / Target Speed (1)In Thermal Cruise mode or S III mode, MART Bit 7: Reserved.
Page 74: Sysfanout Stop Value Register - Index 08H (Bank 0)
W83627DHG Bit 3-0: Tolerance of SYSFANIN Target Speed. 8.11 SYSFANOUT Stop Value Register - Index 08h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits SYSFANOUT Stop Value In Thermal Cruise mode, the SYSFANOUT value decreases to this eight-bit value if the temperature stays below the lowest temperature limit.
Page 75: Sysfanout Start-Up Value Register - Index 0Ah (Bank 0)
W83627DHG 8.13 SYSFANOUT Start-up Value Register - Index 0Ah (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits SYSFANOUT Start-up Value In Thermal Cruise mode, SYSFANOUT value increases from zero to this eight-bit register value to provide a minimum value to turn on the fan.
Page 76: Sysfanout Stop Time Register - Index 0Ch (Bank 0)
W83627DHG 8.15 SYSFANOUT Stop Time Register - Index 0Ch (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits SYSFANOUT Stop Time In Thermal Cruise mode, if the stop value is enabled, this register determines the amount of time it takes the SYSFANOUT value to fall from the stop value to zero.
Page 77: Fan Output Step Down Time Register - Index 0Eh (Bank 0)
W83627DHG 8.17 Fan Output Step Down Time Register - Index 0Eh (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits FANOUT Value Step Down Time In S mode, this register determines the amount of time it takes FANOUT to decrease its MART value by one step.
Page 78: Auxfanout Pwm Output Frequency Configuration Register - Index 10H (Bank 0)
W83627DHG 8.19 AUXFANOUT PWM Output Frequency Configuration Register - Index 10h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits PWM_SCALE3 PWM_CLK_SEL3 The register is only meaningful when AUXFANOUT is programmed for PWM output (i.e., Bank0 Index 12h, bit 0 is 0).
Page 79: Fan Configuration Register Ii - Index 12H (Bank 0)
W83627DHG (1)If AUXFANOUT is programmed for PWM output (Bank0 Index 12h,bit0 is 0) Bit 7-0: AUXFANOUT PWM Duty Cycle. The PWM duty cycle is equal to this eight-bit value, divided by 255, times 100%. FFh creates a duty cycle of 100%, and 00h creates a duty cycle of 0%.
Page 80: Auxtin Target Temperature Register/ Auxfanin0 Target Speed Register - Index 13H
W83627DHG Bit 2-1: AUXFANOUT mode control. 00: AUXFANOUT is in Manual Mode. (Default) 01: AUXFANOUT is in Thermal Cruise Mode. 10: AUXFANOUT is in Fan Speed Cruise Mode. 11: Reserved and no function. Bit 0: 0: AUXFANOUT pin produces a PWM output duty cycle. (Default) 1: AUXFANOUT pin produces DC output.
Page 81: Tolerance Of Target Temperature Or Target Speed Register - Index 14H (Bank 0)
W83627DHG 8.23 Tolerance of Target Temperature or Target Speed Register - Index 14h (Bank Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits AUXTIN Target Temperature Tolerance / AUXFANIN Target Speed Tolerance Reserved (1)In Thermal Cruise mode: Bit 3-0: Tolerance of AUXTIN Target Temperature.
Page 82: Auxfanout Start-Up Value Register - Index 16H (Bank 0)
W83627DHG 8.25 AUXFANOUT Start-up Value Register - Index 16h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits AUXFANOUT Start-up Value In Thermal Cruise mode, the AUXFANOUT value increases from zero to this eight-bit register value to provide a minimum value to turn on the fan.
Page 83: Ovt# Configuration Register - Index 18H (Bank 0)
W83627DHG 8.27 OVT# Configuration Register - Index 18h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits Reserved Reserved Reserved Reserved OVT1_Mode Reserved DIS_OVT1 Reserved Bit 7: Reserved. Bit 6: 0: Enable SYSTIN OVT# output. (Default) 1: Disable temperature sensor SYSTIN over-temperature (OVT#) output.
Page 84 W83627DHG Value RAM ⎯ Index 20h ~ 3Fh (Bank 0) , continued. ADDRESS A6-A0 DESCRIPTION AUXFANIN0 reading Note: This location stores the number of counts of the internal clock per revolution. CPUVCORE High Limit CPUVCORE Low Limit VIN0 High Limit...
Page 85: Configuration Register - Index 40H (Bank 0)
W83627DHG 8.30 Configuration Register - Index 40h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits START SMI#Enable Reserved INT_Clear Reserved Reserved Reserved INITIALIZATION Bit 7: A one restores the power-on default values to some registers. This bit clears itself since the power-on default of this bit is zero.
Page 86: Interrupt Status Register 2 - Index 42H (Bank 0)
W83627DHG Bit 4: A one indicates the high limit of SYSTIN temperature has been exceeded. Bit 3: A one indicates the high or low limit of 3VCC has been exceeded. Bit 2: A one indicates the high or low limit of AVCC has been exceeded.
Page 87: Smi# Mask Register 1 - Index 43H (Bank 0)
W83627DHG 8.33 SMI# Mask Register 1 - Index 43h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits CPUVCORE VIN0 AVCC(Pin95) 3VCC SYSTIN CPUTIN SYSFANIN CPUFANIN0 Bit 7-0: A one disables the corresponding interrupt status bit for the SMI interrupt. (See Interrupt Status Register 1 - Index 41h (Bank 0)) 8.34 SMI# Mask Register 2 - Index 44h (Bank 0)
Page 88: Fan Divisor Register I - Index 47H (Bank 0)
W83627DHG Reserved CPUFANIN1 AUXFANIN1 Reserved Reserved Reserved Reserved CaseOpen Clear Bit 7: CASEOPEN Clear Control. Write 1 to this bit will clear CASEOPEN status. This bit won’t be self cleared, please write 0 after event be cleared. The function is the same as LDA, CR[E6h] bit 5.
Page 89: Serial Bus Address Register - Index 48H (Bank 0)
W83627DHG 1: Pin58(AUXFANIN1) acts as a FAN tachometer input. (Default) 0, Pin58 acts as a FAN control signal, and the output value is set by bit 1. 8.38 Serial Bus Address Register - Index 48h (Bank 0) Register Location: Power on Default Value:...
Page 90: Cpufanout1 Monitor Temperature Source Select Register - Index 4Ah (Bank 0)
W83627DHG 101: Select PECI Agent 4 as AUXFANOUT monitor source. Bit 3: Reserved. Bit 2-0: CPUFANOUT0 Temperature Source Select 000: Select CPUTIN as CPUFANOUT0 monitor source. (Default) 001: Reserved. 010: Select PECI Agent 1 as CPUFANOUT0 monitor source. 011: Select PECI Agent 2 as CPUFANOUT0 monitor source.
Page 91: Fan Divisor Register Ii - Index 4Bh (Bank 0)
W83627DHG 8.41 Fan Divisor Register II - Index 4Bh (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits Reserved Reserved Reserved Reserved ADCOVSEL ADCOVSEL AUXFANIN0 DIV_B0 AUXFANIN0 DIV_B1 Bit 7-6: AUXFANIN0 Divisor bits1-0. Note: Please see Bank0 Index 5Dh , Fan divisor table.
Page 92: Fan In/Out Control Register - Index 4Dh (Bank 0)
W83627DHG 0: SMI# output type is in Two-Times Interrupt mode. (Default) Bit 5: 1: SMI# output type of temperature SYSTIN is One-Time Interrupt mode. 0: SMI# output type is Two-Times Interrupt mode. Bit 4: 1: Disable temperature sensor AUXTIN over-temperature (OVT) output. (Default) 0: Enable AUXTIN OVT output through pin OVT#.
Page 93: Register 50H ~ 5Fh Bank Select Register - Index 4Eh (Bank 0)
Bit 3: Reserved. This bit should be set to zero. Bit 2-0: Bank Select for Index Ports 0x50h~0x5Fh. The three-bit binary value corresponds to the bank number. For example, “010” selects bank2. 8.45 Winbond Vendor ID Register - Index 4Fh (Bank 0) Register Location: Power on Default Value: <15:0>...
Page 94: Reserved Register - Index 50H ~ 55H (Bank 0)
W83627DHG VIDH VIDL Bit 15-8: Vendor ID High-Byte, if Index 4Eh,bit 7 is 1. Default 5Ch. Bit 7-0: Vendor ID Low Byte, if Index 4Eh,bit 7 is 0. Default A3h. 8.46 Reserved Register - Index 50h ~ 55h (Bank 0) 8.47 BEEP Control Register 1 - Index 56h (Bank 0)
Page 95: Beep Control Register 2 - Index 57H (Bank 0)
W83627DHG 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 1: BEEP output control for VIN0 if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 0: BEEP output control for CPUVCORE if the monitored value exceeds the threshold value.
Page 96: Chip Id - Index 58H (Bank 0)
Register Location: Power on Default Value: Attribute: Read Only Size: 8 bits CHIPID Bit 7-0: Winbond Chip ID number. Default C1h. 8.50 Diode Selection Register - Index 59h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits...
Page 97: Reserved Register - Index 5Ah ~ 5Ch (Bank 0)
W83627DHG Bit 4: Diode mode selection for temperature SYSTIN, if Index 5Dh, bit1 is set to 1. 1: CPU-compatible thermal diode. 0: Reserved. Bit 3-2: AUXFANIN1 Divisor, bits 1-0. (See VBAT Monitor Control Register - Index 5Dh (Bank 0)) Bit 1-0: CPUFANIN1 Divisor, bits 1-0. (See VBAT Monitor Control Register - Index 5Dh (Bank 0)) 8.51 Reserved Register - Index 5Ah ~ 5Ch (Bank 0)
Page 98: Critical Temperature And Current Mode Enable Register - Index 5Eh (Bank 0)
W83627DHG Bit 0: 1: Enable battery voltage monitor. When this bit changes from zero to one, it takes one monitor cycle time to update the VBAT reading value register. 0: Disable battery voltage monitor. 8.53 Critical Temperature and Current Mode Enable Register - Index 5Eh (Bank 0)
Page 99: Reserved Register - Index 5Fh (Bank 0)
W83627DHG 8.54 Reserved Register - Index 5Fh (Bank 0) 8.55 CPUFANOUT1 PWM Output Frequency Configuration Register - Index 60h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits PWM_SCALE4 PWM_CLK_SEL4 The register is only meaningful when CPUFANOUT1 is programmed for PWM output.
Page 100: Fan Configuration Register Iii - Index 62H (Bank 0)
W83627DHG (1)If CPUFANOUT1 is programmed for PWM output (Bank0 Index 62h, bit 6 is 0) Bit 7-0: CPUFANOUT1 PWM Duty Cycle.The PWM duty cycle is equal to this eight-bit value, divided by 255, times 100%. FFh creates a duty cycle of 100%, and 00h creates a duty cycle of 0%.
Page 101: Target Temperature Register/Cpufanin1 Target Speed Register - Index 63H (Bank 0)
W83627DHG 8.58 Target Temperature Register/CPUFANIN1 Target Speed Register - Index 63h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits Target Temperature / Target Speed (1)In Thermal Cruise mode or S III mode: MART Bit 7: Reserved.
Page 102: Cpufanout1 Start-Up Value Register - Index 65H (Bank 0)
W83627DHG 8.60 CPUFANOUT1 Start-up Value Register - Index 65h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits CPUFANOUT1 Start-up Value In Thermal Cruise mode, CPUFANOUT1 value increases from zero to this eight-bit register value to provide a minimum value to turn on the fan.
Page 103: Cpufanout0 Maximum Output Value Register - Index 67H (Bank 0)
W83627DHG 8.62 CPUFANOUT0 Maximum Output Value Register - Index 67h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits CPUFANOUT0 Max. Value In S III mode, the CPUFANOUT0 value increases to this value. This value cannot be zero, MART and it cannot be lower than the CPUFANOUT0 Stop value.
Page 104: Cpufanout1 Maximum Output Value Register - Index 69H (Bank 0)
W83627DHG 8.64 CPUFANOUT1 Maximum Output Value Register - Index 69h (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits CPUFANOUT1 Max. Value In S III mode, the CPUFANOUT1 value increases to this value. This value cannot be zero, MART and it cannot be lower than the CPUFANOUT1 Stop value.
Page 105: Sysfanout Critical Temperature Register - Index 6Bh (Bank 0)
W83627DHG 8.66 SYSFANOUT Critical Temperature register - Index 6Bh (Bank 0) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits SYSFANOUT Threshold temperature In Thermal Cruise mode, when the function of SYSFANOUT temperature sensing is enabled, and the monitored temperature exceeds the threshold temperature, the SYSFANOUT will work at full speed.
Page 106: Cpufanout1 Critical Temperature Register - Index 6Eh (Bank 0)
W83627DHG AUXFANOUT Critical temperature In Thermal Cruise mode, when the function of AUXFANOUT temperature sensing is enabled, and the monitored temperature exceeds the threshold temperature, the AUXFANOUT will work at full speed. 8.69 CPUFANOUT1 Critical Temperature Register - Index 6Eh (Bank 0)
Page 107: Cputin Temperature Sensor Temperature (Low Byte) Register - Index 51H (Bank 1)
W83627DHG TEMP<8:1> ° Bit 7-0: Temperature <8:1> of the CPUTIN sensor, The nine-bit value is in units of 0.5 8.71 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1) Register Location: Attribute: Read Only Size: 8 bits Reserved TEMP<0>...
Page 108: Cputin Temperature Sensor Hysteresis (High Byte) Register - Index 53H (Bank 1)
W83627DHG Bit 2: Reserved. This bit should be set to zero. Bit 1：OVT# mode select. 0: Compared mode. (Default) 1: Interrupt mode. Bit 0：0: Monitor CPUTIN. 1: Stop monitoring CPUTIN. 8.73 CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h...
Page 109: Cputin Temperature Sensor Over-Temperature (High Byte) Register - Index 55H (Bank1)97 8.76 Cputin Temperature Sensor Over-Temperature (Low Byte) Register - Index 56H (Bank 1)
W83627DHG 8.75 CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits TOVF<8:1> ° ° Bit 7-0: Over-temperature bits 8-1.The nine-bit value is in units of 0.5 C, and the default is 80 8.76 CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index...
Page 110: Auxtin Temperature Sensor Temperature (High Byte) Register - Index 50H (Bank 2)
W83627DHG 8.77 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2) Register Location: Attribute: Read Only Size: 8 bits TEMP<8:1> ° Bit 7: Temperature <8:1> of the AUXTIN sensor. The nine-bit value is in units of 0.5 8.78 AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h...
Page 111: Auxtin Temperature Sensor Hysteresis (High Byte) Register - Index 53H (Bank 2)
W83627DHG STOP OVTMOD Reserved FAULT FAULT Reserved Reserved Reserved Bit 7-5: Reserved. This bit should be set to zero. Bit 4-3: Number of faults to detect before setting OVT# output. This avoids false tripping due to noise. Bit 2: Reserved. This bit should be set to zero.
Page 112: Auxtin Temperature Sensor Over-Temperature (High Byte) Register - Index 55H (Bank 2)
W83627DHG Reserved THYST<0> ° Bit 7: Hysteresis temperature, bit 0. The nine-bit value is in units of 0.5 Bit 6-0: Reserved. 8.82 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2) Register Location: Power on Default Value:...
Page 113: Interrupt Status Register 3 - Index 50H (Bank 4)
W83627DHG Reserved TOVF<0> ° Bit 7: Over-temperature, bit 0. The nine-bit value is in units of 0.5 Bit 6-0: Reserved. 8.84 Interrupt Status Register 3 - Index 50h (Bank 4) Register Location: Power on Default Value: Attribute: Read Only Size:...
Page 114: Smi# Mask Register 4 - Index 51H (Bank 4)
W83627DHG 8.85 SMI# Mask Register 4 - Index 51h (Bank 4) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits 3VSB VBAT Reserved Reserved TAR3 Reserved Reserved Reserved Bit 7-5: Reserved. Bit 4: A one disables the corresponding interrupt status bit for the SMI interrupt. (See Interrupt Status Register 3 - Index 50h (Bank 4)) Bit 3-2: Reserved.
Page 115: Systin Temperature Sensor Offset Register - Index 54H (Bank 4)
W83627DHG Bit 1: BEEP output control for VBAT if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 0: BEEP output control for 3VSB if the monitored value exceeds the threshold value.
Page 116: Auxtin Temperature Sensor Offset Register - Index 56H (Bank 4)
W83627DHG 8.90 AUXTIN Temperature Sensor Offset Register - Index 56h (Bank 4) Register Location: Power on Default Value: Attribute: Read/Write Size: 8 bits OFFSET<7:0> Bit 7-0: AUXTIN temperature offset value. The value in this register is added to the monitored value so that the reading value is the sum of the monitored value and this offset value.
Page 117: Real Time Hardware Status Register Ii - Index 5Ah (Bank 4)
W83627DHG Bit 4: SYSTIN temperature sensor status. 1: Temperature exceeds the over-temperature value. 0: Temperature is under the hysteresis value. Bit 3: 3VCC Voltage status. 1: 3VCC voltage is over or under the allowed range. 0: 3VCC voltage is in the allowed range.
Page 118: Real Time Hardware Status Register Iii - Index 5Bh (Bank 4)
W83627DHG Bit 4: Case Open status. 1: Case-open is detected and latched. 0: Case-open is not latched. Bit 3: AUXFANIN0 status. 1: Fan speed count is over the threshold value. 0: Fan speed count is in the allowed range. Bit 2: CPUFANIN1 status.
Page 119: Reserved Register - Index 5Ch ~ 5Fh (Bank 4)
W83627DHG Bit 2: Smart Fan of AUXFANIN warning status. 1: Selected temperature has been over the target temperature for three minutes at full fan speed in Thermal Cruise mode. 0: Selected temperature has not reached the warning range. Bit 1: VBAT Voltage status.
Page 120: Serial Peripheral Interface
The data are placed to the LPC bus by the Super I/O (W83627DHG) and returned to the South Bridge. All of the data are read in this manner. By setting the registers shown at Table 9.3, the Super I/O (W83627DHG) supports all the instructions given, such as erase, read, program, to SPI flash.
Page 121 W83627DHG Functions and Definitions The functions and definitions of the 8 bytes are shown in the following table. Table 9.2 SPI Address Map ADDRESS FUNCTION DESCRIPTION Base+0 Commands or instructions of each SPI device Mode execution. Please see the Table 9.3 for the MODE details of each mode.
Page 122 Base+2 ~ Base+3 and parameters to Base+4. Last, write 5X to Base+1. For correct programming, make sure the state of the device is ready and write enabled. * For more details, please see the Programming Guide of the W83627DHG. Publication Release Date: Aug, 22, 2007 -110- Version 1.4...
Page 123: Floppy Disk Controller
10. FLOPPY DISK CONTROLLER 10.1 FDC Functional Description The floppy disk controller (FDC) of the W83627DHG integrates all of the logic required for floppy disk control. The FDC implements a FIFO which provides better system performance in multi-master systems, and the digital data separator supports data rates up to 2 M bits/sec.
Page 124: Data Separator
FIFO manages the host interface bottleneck due to the high speed of data transfer to and from the disk. 10.1.5 FDC Core The W83627DHG FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor, and the result may be a multi-byte transfer back to the microprocessor.
Page 125: Fdc Commands
W83627DHG 10.1.6 FDC Commands Command Symbol Descriptions: Cylinder Number 0 - 256 Data Pattern DIR: Step Direction DIR = 0: step out DIR = 1: step in DS0: Disk Drive Select 0 DS1: Disk Drive Select 1 DTL: Data Length...
Page 126 W83627DHG (1) Read Data PHASE REMARKS Command Command codes DS1 DS0 ---------------------- C ------------------------ Sector ID information prior to command execution ---------------------- H ------------------------ ---------------------- R ------------------------ ---------------------- N ------------------------ -------------------- EOT ----------------------- -------------------- GPL ----------------------- -------------------- DTL ----------------------- Execution...
Page 127 W83627DHG (2) Read Deleted Data PHASE REMARKS Command MT MFM Command codes DS1 DS0 ---------------------- C ------------------------ Sector ID information prior to command execution ---------------------- H ------------------------ ---------------------- R ------------------------ ---------------------- N ------------------------ -------------------- EOT ----------------------- -------------------- GPL ----------------------- -------------------- DTL -----------------------...
Page 128 W83627DHG (3) Read A Track PHASE REMARKS Command Command codes ---------------------- C ------------------------ Sector ID information prior to command execution ---------------------- H ------------------------ ---------------------- R ------------------------ ---------------------- N ------------------------ -------------------- EOT ----------------------- -------------------- GPL ----------------------- -------------------- DTL ----------------------- Execution Data transfer between the FDD and system;...
Page 129 W83627DHG (4) Read ID PHASE REMARKS Command Command codes DS1 DS0 Execution The first correct ID information on the cylinder is stored in the Data Register Result -------------------- ST0 ----------------------- Status information after command execution -------------------- ST1 ----------------------- -------------------- ST2 -----------------------...
Page 130 W83627DHG (6) Version PHASE REMARKS Command Command code Result Enhanced controller (7) Write Data PHASE REMARKS Command Command codes DS1 DS0 ---------------------- C ------------------------ Sector ID information prior to Command execution ---------------------- H ------------------------ ---------------------- R ------------------------ ---------------------- N ------------------------...
Page 131 W83627DHG (8) Write Deleted Data PHASE REMARKS Command Command codes DS1 DS0 ---------------------- C ------------------------ Sector ID information prior to command execution ---------------------- H ------------------------ ---------------------- R ------------------------ ---------------------- N ------------------------ -------------------- EOT ----------------------- -------------------- GPL ----------------------- -------------------- DTL -----------------------...
Page 132 W83627DHG (9) Format A Track PHASE REMARKS Command Command codes DS1 DS0 ---------------------- N ------------------------ Bytes per Sector --------------------- SC ----------------------- Sectors per Cylinder --------------------- GPL --------------------- Gap 3 ---------------------- D ------------------------ Filler Byte Execution ---------------------- C ------------------------ Input Sector Parameters...
Page 133 W83627DHG (11) Sense Interrupt Status PHASE REMARKS Command Command code Result ---------------- ST0 ------------------------- Status information at the end of each seek operation ---------------- PCN ------------------------- (12) Specify PHASE REMARKS Command Command codes | ---------SRT ----------- | --------- HUT ---------- |...
Page 134 W83627DHG (15) Relative Seek PHASE REMARKS Command Command codes DS1 DS0 | -------------------- RCN ---------------------------- | (16) Dumpreg PHASE REMARKS Command Registers placed in FIFO Result ----------------------- PCN-Drive 0-------------------- ----------------------- PCN-Drive 1 ------------------- ----------------------- PCN-Drive 2-------------------- ----------------------- PCN-Drive 3 -------------------...
Page 135 W83627DHG (19) Sense Drive Status PHASE REMARKS Command Command Code DS1 DS0 Result ---------------- ST3 ------------------------- Status information about the disk drive (20) Invalid PHASE REMARKS Command ------------- Invalid Codes ----------------- Invalid codes (no operation- FDC goes to standby state)
Page 136: Register Descriptions
W83627DHG 10.2 Register Descriptions There are several status, data, and control registers in the W83627DHG. These registers are defined below, and the rest of this section provides more details about each one of them. ADDRESS REGISTER OFFSET READ WRITE base address + 0...
Page 137 W83627DHG INDEX#(Bit 2): This bit indicates the value of the INDEX# output. WP#(Bit 1): disk is write-protected disk is not write-protected DIR (Bit 0) This bit indicates the direction of head movement. outward direction inward direction In PS/2 Model 30 mode, the bit definitions for this register are as follows:...
Page 138: Status Register B (Sb Register) (Read Base Address + 1)
W83627DHG WP (Bit 1): disk is not write-protected disk is write-protected DIR# (Bit 0) This bit indicates the direction of head movement. inward direction outward direction 10.2.2 Status Register B (SB Register) (Read base address + 1) Along with the SA register, the SB register is used to monitor several disk interface pins in PS/2 and Model 30 modes.
Page 139 W83627DHG DSC# DSC# Reserved Reserved WE F/F WE F/F RDATA F/F RDATA F/F WD F/F WD F/F DSA# DSA# Reserved Reserved Reserved Reserved RESERVED (Bit 7) RESERVED (Bit 6) DSA# (Bit 5): This bit indicates the status of the DSA# output pin.
Page 140: Digital Output Register (Do Register) (Write Base Address + 2)
W83627DHG 10.2.3 Digital Output Register (DO Register) (Write base address + 2) The Digital Output Register is a write-only register that controls drive motors, drive selection, DRQ/IRQ enable, and FDC reset. The bit definitions are as follows: Drive Select: 00 select drive A...
Page 141: Main Status Register (Ms Register) (Read Base Address + 4)
W83627DHG Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the bits in LD0 CRF2. Which two bits are reflected depends on the last drive selection in the DO register. Floppy Boot drive 1, 0 (Bit 3, 2): These two bits reflect the value of LD0 CRF1, bits 7 and 6.
Page 142 W83627DHG DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET S/W RESET (Bit 7): This bit is the software reset bit. POWER-DOWN (Bit 6): FDC in normal mode FDC in power-down mode PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write precompensation. The following tables show the precompensation values for every combination of these bits.
Page 143: Fifo Register (R/W Base Address + 5)
In addition, data bytes pass through the data register to program or obtain results after a command. In the W83627DHG, this register is disabled after reset. The FIFO can enable it and change its values through the configure command.
Page 144 W83627DHG Status Register 1 (ST1) Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted. NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during execution of write data.
Page 145: Digital Input Register (Di Register) (Read Base Address + 7)
W83627DHG 10.2.8 Digital Input Register (DI Register) (Read base address + 7) The Digital Input Register is an 8-bit, read-only register used for diagnostic purposes. In PC/XT or PC/AT mode, only bit 7 is checked by the BIOS. When the register is read, bit 7 shows the complement of DSKCHG# while the other bits remain in tri-state.
Page 146: Configuration Control Register (Cc Register) (Write Base Address + 7)
W83627DHG DRATE0 DRATE1 NOPREC DMAEN DSKCHG# DSKCHG (Bit 7): This bit indicates the status of the DSKCHG# input. Bit 6-4: These bits are always a logic 0 during a read. DMAEN (Bit 3): This bit indicates the value of DO register, bit 3.
Page 147 W83627DHG In the PS/2 Model 30 mode, the bit definitions are as follows: DRATE0 DRATE1 NOPREC X: Reserved Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2): This bit disables the precompensation function. It can be set by the software.
Page 148: Uart Port
W83627DHG 11. UART PORT 11.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B) The UARTs are used to convert parallel data into serial format for transmission and to convert serial data into parallel format during reception. The serial data format is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one-and-a-half (five-bit format only) or two stop bits.
Page 149 W83627DHG Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or received. (1) If MSBE is set to logical 0, one stop bit is sent and checked. (2) If MSBE is set to logical 1 and the data length is 5 bits, one-and-a-half stop bits are sent and checked.
Page 150 W83627DHG Bit Number Register Address Base Receiver RX Data RX Data RX Data RX Data RX Data RX Data RX Data RX Data Buffer Register BDLAB = 0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5...
Page 151: Uart Status Register (Usr) (Read/Write)
W83627DHG 11.2.2 UART Status Register (USR) (Read/Write) This 8-bit register provides information about the status of data transfer during communication. RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD)
Page 152: Handshake Control Register (Hcr) (Read/Write)
W83627DHG 11.2.3 Handshake Control Register (HCR) (Read/Write) This register controls pins used with handshaking peripherals such as modems and also controls the diagnostic mode of the UART. Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable...
Page 153: Uart Fifo Control Register (Ufr) (Write Only)
W83627DHG Bit 3: TDCD. This bit indicates that the DCD# pin has changed state after HSR was read by the CPU. Bit 2: FERI. This bit indicates that the RI # pin has changed from low to high after HSR was read by the CPU.
Page 154: Interrupt Status Register (Isr) (Read Only)
W83627DHG 11.2.6 Interrupt Status Register (ISR) (Read only) This register reflects the UART interrupt status. 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled Bit 7, 6: These two bits are set to logical 1 when UFR, bit 0 = 1.
Page 155: Interrupt Control Register (Icr) (Read/Write)
W83627DHG 11.2.7 Interrupt Control Register (ICR) (Read/Write) This 8-bit register enables and disables the five types of controller interrupts separately. A selected interrupt can be enabled by setting the appropriate bit to logical 1. The interrupt system can be totally disabled by setting bits 0 through 3 to logical 0.
Page 156: User-Defined Register (Udr) (Read/Write)
W83627DHG Continued. BAUD RATE FROM DIFFERENT PRE-DIVIDER DECIMAL DIVISOR PRE-DIV: 13 PRE-DIV:1.625 PRE-DIV: 1.0 USED TO ERROR PERCENTAGE GENERATE 16X 1.8461M HZ 14.769M HZ 24M HZ CLOCK 2400 19200 31200 3600 28800 46800 4800 38400 62400 7200 57600 93600 9600...
Page 157: Parallel Port
12. PARALLEL PORT 12.1 Printer Interface Logic The W83627DHG parallel port can be attached to devices that accept eight bits of parallel data at standard TTL level. The W83627DHG supports the IBM XT/AT compatible parallel port (SPP), the bi-directional parallel port (BPP), the Enhanced Parallel Port (EPP), and the Extended Capabilities Parallel Port (ECP) on the parallel port.
Page 158: Enhanced Parallel Port (Epp)
W83627DHG Continued HOST CONNECTOR PIN NUMBER OF W83627DHG PIN ATTRIBUTE SLCT nAFD nERR nINIT nSLIN 12.2 Enhanced Parallel Port (EPP) The following table lists the registers used in the EPP mode and identifies the bit map of the parallel port and EPP registers. Some of the registers are used in other modes as well.
Page 159: Data Port (Data Swapper)
W83627DHG 12.2.1 Data Port (Data Swapper) The CPU reads the contents of the printer's data latch by reading the data port. 12.2.2 Printer Status Buffer The CPU reads the printer status by reading the printer status buffer. The bit definitions are as follows:...
Page 160: Epp Address Port
W83627DHG When this bit is logical 1, the parallel port is in input mode (read); when it is logical 0, the parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid and fixed at zero.
Page 161: Epp Pin Descriptions
W83627DHG When any EPP data port is accessed, the contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle.
Page 162: Extended Capabilities Parallel (Ecp) Port
12.3 Extended Capabilities Parallel (ECP) Port This port is software- and hardware-compatible with existing parallel ports, so the W83627DHG parallel port may be used in standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host-to-peripheral) and reverse (peripheral-to-host) directions.
Page 163: Ecp Register And Bit Map
W83627DHG 12.3.1 ECP Register and Bit Map The next two tables list the registers used in the ECP mode and provide a bit map of the parallel port and ECP registers. NAME ADDRESS ECP MODES FUNCTION data Base+000h 000-001 Data Register...
Page 164: Data And Ecpafifo Port
W83627DHG 12.3.2 Data and ecpAFifo Port Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input, and the contents of this register are output to PD0-PD7. During a read operation, ports PD0-PD7 are read and output to the host.
Page 165: Device Control Register (Dcr)
W83627DHG Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input.
Page 166: Tfifo (Test Fifo Mode) Mode = 110
W83627DHG 12.3.7 TFIFO (Test FIFO Mode) Mode = 110 Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO is not transmitted to the parallel port lines. However, data in the tFIFO may be displayed on the parallel port data lines.
Page 167: Ecr (Extended Control Register) Mode = All
W83627DHG 12.3.10 ECR (Extended Control Register) Mode = all This register controls the extended ECP parallel port functions. The bit definitions are follows: empty full service Intr dmaEn nErrIntrEn MODE MODE MODE Bit 7-5: Read/Write. These bits select the mode.
Page 168: Ecp Pin Descriptions
W83627DHG Bit 2: Read/Write Disables DMA and all of the service interrupts. Writing a logical 1 to this bit does not cause an interrupt. Enables one of the following cases of interrupts. When one of the serviced interrupts occurs, this bit is set to logical 1 by the hardware. This bit must be reset to logical 0 to re-enable the interrupts.
Page 169: Ecp Operation
W83627DHG ECP Pin Descriptions , continued. NAME TYPE DESCRIPTION Requests a byte of data from the peripheral when it is asserted. In the forward direction, this signal indicates whether the data lines NautoFd (HostAck) contain ECP address or data. Normal data are transferred when nAutoFd (HostAck) is high, and an 8-bit command is transferred when it is low.
Page 170: Fifo Operation
W83627DHG 12.3.12.3. Data Compression The W83627DHG hardware supports RLE decompression and can transfer compressed data to a peripheral. Odd (RLE) compression is not supported in the hardware, however. In order to transfer data in ECP mode, the compression count is written to ecpAFifo and the data byte is written to ecpDFifo.
Page 171: Keyboard Controller
W83627DHG 13. KEYBOARD CONTROLLER The W83627DHG KBC (8042 with licensed KB BIOS) circuit is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse and can be used with ® compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer.
Page 172: Status Register
W83627DHG 13.3 Status Register The status register is an 8-bit, read-only register at I/O address 64h (Default, PnP programmable I/O address LD5-CR62 and LD5-CR63) that holds information about the status of the keyboard controller and interface. It may be read at any time.
Page 173 W83627DHG Commands, continued COMMAND FUNCTION Test Password Returns 0Fah if Password is loaded Returns 0F1h if Password is not loaded Load Password Load Password until a logical 0 is received from the system Enable Password Enable the checking of keystrokes for a match with the password...
Page 174: Hardware Gatea20/Keyboard Reset Control Logic
W83627DHG 13.5 Hardware GATEA20/Keyboard Reset Control Logic The KBC includes hardware control logic to speed-up GATEA20 and KBRESET. This control logic is controlled by LD5-CRF0 as follows: 13.5.1 KB Control Register KCLKS1 KCLKS0 Reserved Reserved Reserved P92EN HGA20 HKBRST NAME KCLKS1, KCLKS0 These two bits select the KBC clock rate.
Page 175: Port 92 Control Register
W83627DHG 13.5.2 Port 92 Control Register NAME Res. (0) Res. (0) Res. (1) Res. (0) Res. (0) Res. (1) SGA20 PLKBRST SGA20 (Special GATE A20 Control) 1: Drives GATE A20 signal to high. 0: Drives GATE A20 signal to low.
Page 176: Power Management Event
Logical Device A, CR[F2h], bit[0] and is for enabling or disabling the PME function. If this bit is set to “0”, the W83627DHG won’t output any PME signal when any of the wake-up events has occurred and is enabled. The four registers are divided into PME status registers and PME interrupt Note.1...
Page 177: Pson# Logic
W83627DHG 14.1.1 PSON# Logic 14.1.1.1. Normal Operation The PSOUT# signal will be asserted low if the PSIN# signal is asserted low. The PSOUT# signal is held low for as long as the PSIN# is held low. The South Bridge controls the SUSB# signal through the PSOUT# signal.
Page 178: Ac Power Failure Resume
User defines the state before the power failure. (The previous state is set at CRE6[4]. Please see Note 2) Note1. The W83627DHG detects the state before power failure (on or off) through the SUSB# signal and the 3VCC power. The relation is illustrated in the following two figures.
Page 179: Wake Up The System By Keyboard And Mouse
14.2 Wake Up the System by Keyboard and Mouse The W83627DHG generates a low pulse through the PSOUT# pin to wake up the system when it detects a key code pressed or mouse button clicked. The following sections describe how the W83627DHG works.
Page 180: Resume Reset Logic
The RSMRST# (Pin 75) signal is a reset output and is used as the 3VSB power-on reset signal for the South Bridge. When the W83627DHG detects the 3VSB voltage rises to “V1”, it then starts a delay – “t1” before the rising edge of RSMRST# asserting. If the 3VSB voltage falls below “V2”, the RSMRST# de-asserts immediately.
Page 181: Pwrok Generation
The PWROK (Pin 71) signal is an output and is used as the 3VCC power-on reset signal. When the W83627DHG detects the 3VCC voltage rises to “V3”, it then starts a delay – “t2” before the rising edge of PWROK asserting. If the 3VCC voltage falls below “V4”, the PWROK de-asserts immediately.
Page 182: The Relation Among Pwrok/Pwrok2, Atxpgd And Ftprst# - Both For Ube And Ubf Version Only
W83627DHG Logical Device A, CR[E6h], bits 2~1. The following table shows the definitions of Logical Device A, CR[E6h] bits 3 ~1. LOGICAL DEVICE A, DEFINITION CR[E6H] BIT PWROK_DEL (first stage) (VSB) Set the delay time when rising from PWROK_LP to PWROK_ST.
Page 183 W83627DHG Table 14.4 SYMBOL PARAMETER UNIT FTPRST# active to PWROK active Note. 1. The values above are the worst-case results of R&D simulation 2. The length of T level is based on the length of the low level of FTPRST# Additionally, the ATXPGD signal, too, is used to control the generation of PWROK and PWROK2.
Page 184 W83627DHG 3VCC PWROK/PWROK2 are ATXPGD(input) active when both 3VCC PWROK/PWROK2 and ATXPGD are valid are inactive even PWROK/PWROK2 when 3VCC is valid (output) Figure 14.9 Timing and voltage parameters are shown in the following table. SYMBOL PARAMETER MIN. TYP. MAX.
Page 185: Serialized Irq
W83627DHG 15. SERIALIZED IRQ The W83627DHG supports a serialized IRQ scheme. This allows a signal line to be used to report the parallel interrupt requests. Since more than one device may need to share the signal serial SERIRQ signal, an open drain signal scheme is employed. The clock source is the PCI clock. The serialized interrupt is transferred on the SERIRQ signal, one cycle consisting of three frames types: the Start Frame, the IRQ/Data Frame, and the Stop Frame.
Page 186: Irq/Data Frame
W83627DHG 15.2 IRQ/Data Frame Once the Start Frame has been initiated, the W83627DHG must start counting frames based on the rising edge of the start pulse. Each IRQ/Data Frame has three clocks: the Sample phase, the Recovery phase, and the Turn-around phase.
Page 187: Stop Frame
W83627DHG 15.3 Stop Frame After all IRQ/Data Frames have completed, the host controller will terminates SERIRQ with a Stop frame. Only the host controller can initiate the Stop Frame by driving SERIRQ low for 2 or 3 clocks. If the Stop Frame is low for 2 clocks, the Sample mode of next SERIRQ cycle’s Sample mode is the Quiet mode.
Page 188: Watchdog Timer
Watchdog Timer counter and start counting down. The W83627DHG outputs a low signal to the WDTO# pin (pin 77) when a time-out event occurs. In other words, when the value is counted down to zero, the timer stops, and the W83627DHG sets the WDTO# status bit in Logical Device 8, CR[F7h], bit[4], outputting a low signal to the WDTO# pin(pin 77).
Page 189: General Purpose I/O
W83627DHG 17. GENERAL PURPOSE I/O The W83627DHG provides 40 input/output ports that can be individually configured to perform a simple basic I/O function or alternative, pre-defined function. GPIO port 6 is configured through control registers in Logical Device 7, and GPIO ports 2 ~ 5 in Logical Device 9. Users can configure each individual port to be an input or output port by programming respective bit in selection register (0 = output, 1 = input).
Page 190: Vid Inputs And Outputs
18. VID INPUTS AND OUTPUTS The W83627DHG provides eight pins for VID input or output function. The default function is VID input. These pins can be configured to VID output function by setting Logical Device B, CR[F0h], bit 7 to 0.
Page 191: Pci Reset Buffers
W83627DHG 19. PCI RESET BUFFERS The W83627DHG has five copies of LRESET# output buffers. LRESET# is LPC Interface Reset, to which PCI Reset is connected. The five copies of LRESET# in the W83627DHG are designated RSTOUT0#, RSTOUT1#, RSTOUT2#, RSTOUT3# and RSTOUT4#. All of them are powered by a 3VSB power.
Page 192: Configuration Register
W83627DHG 20. CONFIGURATION REGISTER 20.1 Chip (Global) Control Register CR 02h. (Software Reset; Write Only) READ / WRITE DESCRIPTION Reserved. Write “1” Only Software RESET. CR 07h. (Logical Device; Default 00h) READ / WRITE DESCRIPTION R / W Logical Device Number.
Page 193 W83627DHG s: value by strapping CR 24h. (Global Option; Default 0100_0ss0b) READ / WRITE DESCRIPTION Select output type of CPUFANOUT1 R / W CPUFANOUT1 is Push-pull. (Default) CPUFANOUT1 is Open-drain. CLKSEL => Input clock rate selection R / W = 0 The clock input on pin 18 is 24 MHz.
Page 194 W83627DHG CR 25h. (Interface Tri-state Enable; Default 00h) READ / WRITE DESCRIPTION Reserved. R / W UARTBTRI R / W UARTATRI R / W PRTTRI Reserved. R / W FDCTRI. s: value by strapping CR 26h. (Global Option; Default 0s000000b)
Page 195 W83627DHG CR 27h. (Reserved) CR 28h. (Global Option; Default 50h) READ / WRITE DESCRIPTION Reserved. Flash ROM size select = 00 R / W = 01 = 10 4M (Default) = 11 Select to enable/disable decoding of BIOS ROM range 000E xxxxh.
Page 196 W83627DHG CR 2Ah. (SPI Configuration; Default 00h) (VSB Power) READ / WRITE DESCRIPTION Serial Peripheral Interface Configuration bit. (VSB) – These two bits are for UBE and UBF version only = 00 Normal read. SPI clock is 16MHz. = 01 Normal read.
Page 197 W83627DHG CR 2Ch. (Multi-function Pin Selection; Default E2h) (VSB Power) READ / WRITE DESCRIPTION Pin 88 Select R / W = 0 GP34 = 1 RSTOUT4# (Default) Pin 89 Select = 0 GP33 R / W = 1 RSTOUT3# (Default) Note: This bit is ignored when CR2A, bit 1 is High.
Page 198 = 0 WDTO# = 1 GPIO50 CR 2Eh. (Default 00h) READ / WRITE DESCRIPTION R / W Test Mode Bits: Reserved for Winbond. CR 2Fh. (Default 00h) READ / WRITE DESCRIPTION R / W Test Mode Bits: Reserved for Winbond.
Page 199: Logical Device 0 (Fdc)
W83627DHG 20.2 Logical Device 0 (FDC) CR 30h. (Default 01h) READ / WRITE DESCRIPTION Reserved. 0: Logical device is inactive. R / W 1: Activate the logical device. CR 60h, 61h. (Default 03h,F0h) READ / WRITE DESCRIPTION These two registers select FDC I/O base address <100h: FF8h> on 8 R / W bytes boundary.
Page 200 W83627DHG Continued READ / WRITE DESCRIPTION FDC DMA Mode. 0: Burst Mode is enabled R / W 1: Non-Burst Mode. Floppy Mode. 0: Normal Floppy Mode. R / W 1: Enhanced 3-mode FDD. CR F1h. (Default 00h) READ / WRITE DESCRIPTION Boot Floppy.
Page 201 W83627DHG CR F5h. (Default 00h) READ / WRITE DESCRIPTION R / W Same as FDD0 of CR F5h. TABLE A DRIVE RATE TABLE DATA RATE SELECTED DATA RATE SELECT SELDEN DRTS1 DRTS0 DRATE1 DRATE0 1Meg 500K 250K 300K 150K 250K...
Page 202: Logical Device 1 (Parallel Port)
W83627DHG 20.3 Logical Device 1 (Parallel Port) CR 30h. (Default 01h) READ / WRITE DESCRIPTION Reserved. 0: Logical device is inactive. R / W 1: Activate the logical device. CR 60h, 61h. (Default 03h, 78h) READ / WRITE DESCRIPTION These two registers select PRT I/O base address.
Page 203: Logical Device 2 (Uart A)
W83627DHG 20.4 Logical Device 2 (UART A) CR 30h. (Default 01h) READ / WRITE DESCRIPTION Reserved. 0: Logical device is inactive. R / W 1: Activate the logical device. CR 60h, 61h. (Default 03h, F8h) READ / WRITE DESCRIPTION These two registers select Serial Port 1 I/O base address <100h: FF8h> on R / W 8 bytes boundary.
Page 204 W83627DHG CR 70h. (Default 03h) READ / WRITE DESCRIPTION Reserved. R / W These bits select IRQ resource for Serial Port 2. CR F0h. (Default 00h) READ / WRITE DESCRIPTION Reserved. 0: No reception delay when SIR is changed from TX mode to RX mode.
Page 205: Logical Device 5 (Keyboard Controller)
W83627DHG IR MODE IR FUNCTION IRTX IRRX Disable Tri-state High Active pulse 1.6 μS 010* IrDA Demodulation into SINB/IRRX 011* IrDA Active pulse 3/16 bit time Demodulation into SINB/IRRX ASK-IR Inverting IRTX/SOUTB pin Routed to SINB/IRRX Inverting IRTX/SOUTB & 500...
Page 206: Logical Device 6 (Serial Peripheral Interface)
W83627DHG CR 70h. (Default 01h) READ / WRITE DESCRIPTION Reserved. R / W These bits select IRQ resource for KINT. (Keyboard interrupt) CR 72h. (Default 0Ch) READ / WRITE DESCRIPTION Reserved. R / W These bits select IRQ resource for MINT. (PS/2 Mouse interrupt) CR F0h.
Page 207: Logical Device 7 (Gpio6)
W83627DHG 20.8 Logical Device 7 (GPIO6) CR 30h. (Default 00h) READ / WRITE DESCRIPTION Reserved. R / W 0: GPIO6 is inactive. 1: GPIO6 is active. Reserved. CR F4h. (GPIO6 I/O Register; Default FFh) READ / WRITE DESCRIPTION GPIO6 I/O register...
Page 208: Logical Device 8 (Wdto# & Pled)
W83627DHG 20.9 Logical Device 8 (WDTO# & PLED) CR 30h. (Default 00h) READ / WRITE DESCRIPTION Reserved. R / W 0: WDTO# and PLED are inactive. 1: Activate WDTO# and PLED. CR F5h. (WDTO#, PLED and KBC P20 Control Mode Register; Default 00h)
Page 209 W83627DHG CR F6h. (WDTO# Counter Register; Default 00h) READ / WRITE DESCRIPTION Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value into the Watch Dog Counter and start counting down. If CR F7h, bits 7 and 6 are set,...
Page 210: Logical Device 9 (Gpio2, Gpio3, Gpio4, Gpio5)
W83627DHG 20.10 Logical Device 9 (GPIO2, GPIO3, GPIO4, GPIO5) CR 30h. (Default 00h) READ / WRITE DESCRIPTION Reserved. R / W 0: GPIO5 is inactive. 1: GPIO5 is active R / W 0: GPIO4 is inactive. 1: GPIO4 is active.
Page 211 W83627DHG CR E4h. (GPIO2 Data Register; Default 00h) READ / WRITE DESCRIPTION GPIO2 Data register R / W For output ports, the respective bits can be read and written by the pins. For input ports, the respective bits can only be read by the pins. Write Read Only accesses are ignored.
Page 212 W83627DHG CR E9h. (GPIO5 Status Register; Default 00h) READ / WRITE DESCRIPTION GPIO5 Event Status Bit 7-0 corresponds to GP57-GP50, respectively. Read Only 0 : No active edge(rising/falling) has been detected Read-Clear 1 : An active edge(rising/falling) has been detected Reading the status bit clears it to 0.
Page 213 W83627DHG CR F4h. (GPIO4 I/O Register; Default FFh) READ / WRITE DESCRIPTION GPIO4 I/O register R / W 0: The respective GPIO4 PIN is programmed as an output port 1: The respective GPIO4 PIN is programmed as an input port.
Page 214: Logical Device A (Acpi)
W83627DHG CR FEh. (GPIO3 Input Detected Type Register; Default 00h) READ / WRITE DESCRIPTION R / W Reserved. 0: Enable GP35 input de-bouncer R / W 1: Disable GP35 input de-bouncer 0: Enable GP31 input de-bouncer R / W 1: Disable GP31 input de-bouncer...
Page 215 W83627DHG CR E0h. (Default 01h) (VBAT power) READ / WRITE DESCRIPTION DIS_PSIN => Disable the panel switch input to turn on the system power supply. R / W 0: PSIN is wire-AND and connected to PSOUT#. 1: PSIN is blocked and cannot affect PSOUT#.
Page 216 W83627DHG CR E1h. (KBC Wake-Up Index Register; Default 00h) (VSB power) READ / WRITE DESCRIPTION Keyboard wake-up index register. This is the index register of CRE2, which is the access window for the keyboard’s pre-determined key key-combination characters. The first set of R / W wake-up keys is in of 0x00 - 0x0E, the second set 0x30 –...
Page 217 W83627DHG CR E4h. (Default 00h) READ / WRITE DESCRIPTION Disable / Enable to issue a 4s long PSOUT# low pulse when the system returns from power loss state and is supposed to be “off” as described in CRE4[6:5], Logical Device...
Page 218 W83627DHG Continued READ / WRITE DESCRIPTION Reserved. ATXPGD signal to control PWROK and PWROK2 generation 0: Enable. R / W 1: Disable. * This bit is available both for UBE and UBF version CR E6h. (Default 1Ch) BIT READ / WRITE DESCRIPTION ENMDAT =>...
Page 219 W83627DHG CR E7h. (Default 00h) READ / WRITE DESCRIPTION ENKD3 => (VSB) Enable the third set of keyboard wake-up key combination. Its values are accessed through keyboard wake-up index register (CRE1) and keyboard R / W wake-up data register (CRE2) at the index from 40h to 4eh.
Page 220 W83627DHG CR F2h. (Default 7Ch) (VSB Power) READ / WRITE DESCRIPTION Reserved. Enable RSTOUT4# function. R / W 0: Disable RSTOUT4#. 1: Enable RSTOUT4#. Enable RSTOUT3# function. R / W 0: Disable RSTOUT3#. 1: Enable RSTOUT3#. Enable RSTOUT2# function. R / W 0: Disable RSTOUT2#.
Page 221 W83627DHG CR F4h. (Default 00h) READ / WRITE DESCRIPTION Reserved. PME status of the HM IRQ event. R / W-Clear Write 1 to clear this status. PME status of the WDTO# event. R / W-Clear Write 1 to clear this status.
Page 222: Logical Device B (Hardware Monitor)
W83627DHG CR FEh. (GPIO3 Event Route Selection Register; Default 00h) READ / WRITE DESCRIPTION R / W Reserved. 0: Disable GP35 event route to PSOUT#. R / W 1: Enable GP35 event route to PSOUT#. 0: Disable GP31 event route to PSOUT#.
Page 223 W83627DHG CR F0h. (VID Control Register; Default 81h) READ / WRITE DESCRIPTION VID I/O Control R / W 0: VID output mode. 1: VID input mode. VIDAMD input level select R / W 0: VID is GTL level. 1: VID is AMD VRM level.
Page 224: Logical Device C (Peci, Sst)
W83627DHG 20.13 Logical Device C (PECI, SST) CR E0h. (Agent Configuration Register; Default 00h) READ / WRITE DESCRIPTION Agt4EN (Agent 4 Enable Bit) R / W 0: Agent 4 is disabled. 1: Agent 4 is enabled. Agt3EN (Agent 3 Enable Bit) R / W 0: Agent 3 is disabled.
Page 225 W83627DHG CR E2h. (Agent 2 TBase Register; Default 48h) READ / WRITE DESCRIPTION Reserved. Agent 2 TBase must always be a positive value; a negative value will R / W cause abnormal temperature responses. (Note 1) CR E3h. (Agent 3 TBase Register; Default 48h)
Page 226 W83627DHG Continued READ / WRITE DESCRIPTION Reserved Return High Temperature 0: The temperature of each agent is returned from domain 0 or domain 1, R / W which is controlled by CRE0 bit 0~3. 1: Return the highest temperature in domain 0 and domain 1 of individual Agent.
Page 227 W83627DHG CR F1h. (SST Address Register; Default 48h) READ / WRITE DESCRIPTION R / W SST address CR FEh. (PECI Agent Relative Temperature Register; Default 00h) READ / WRITE DESCRIPTION Read Only This register shows the retrieved High Byte raw data from PECI interface.
Page 228: Specifications
W83627DHG 21. SPECIFICATIONS 21.1 Absolute Maximum Ratings SYMBOL PARAMETER RATING UNIT Power Supply Voltage 3VCC -0.5 to 6.5 (3.3V) Input Voltage -0.5 to 3V +0.5 Input Voltage (5V -0.5 to 6 tolerance) VBAT RTC Battery Voltage V 2.2 to 4.0...
Page 229 W83627DHG DC CHARACTERISTICS, continued PARAMETER MAX. UNIT CONDITIONS – TTL-level, bi-directional pin with 24mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage = 24 mA Output High Voltage = -24 mA μA Input High Leakage = 3.3V μA...
Page 230 W83627DHG DC CHARACTERISTICS, continued PARAMETER MAX. UNIT CONDITIONS – 3.3V TTL-level, Schmitt-trigger, bi-directional pin with 24mA source-sink capability 24tsp3 Input Low Threshold Voltage Input High Threshold Voltage Hystersis =3.3V Output Low Voltage = 24 mA Output High Voltage = -24 mA Input High Leakage μA...
Page 231 W83627DHG DC CHARACTERISTICS, continued PARAMETER MAX. UNIT CONDITIONS I/OD16 – TTL–level, Schmitt-trigger, bi-directional pin and open-drain output with 16mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis =3.3V Output Low Voltage = 16 mA Input High Leakage μA...
Page 232 W83627DHG DC CHARACTERISTICS, continued PARAMETER MAX. UNIT CONDITIONS I/OD – CMOS–level, Schmitt-trigger, bi-directional pin with internal pulled-down resistor 12 csd and open-drain output with 12mA sink capability Input Low Threshold Voltage = 3.3 V Input High Threshold Voltage = 3.3 V Hystersis = 3.3 V...
Page 233 W83627DHG DC CHARACTERISTICS, continued PARAMETER MAX. UNIT CONDITIONS – 3.3V output pin with 12mA source-sink capability 12p3 Output Low Voltage = 12 mA Output High Voltage = -12 mA – 3.3V output pin with 24mA source-sink capability 24p3 Output Low Voltage...
Page 234 W83627DHG DC CHARACTERISTICS, continued PARAMETER MAX. UNIT CONDITIONS – TTL-level input pin with internal pulled-up resistor Input Low Voltage Input High Voltage μA Input High Leakage = 3.3 V μA Input Low Leakage = 0 V – TTL–level, Schmitt-trigger input pin Input Low Threshold Voltage = 3.3 V...
Page 235 W83627DHG DC CHARACTERISTICS, continued PARAMETER MAX. UNIT CONDITIONS – CMOS-level input pin with internal pulled-up resistor Input High Voltage Input High Leakage μA = 3.3V Input Low Leakage μA = 0 V – CMOS–level, Schmitt-trigger input pin Input Low Threshold Voltage = 3.3V...
Page 236 W83627DHG DC CHARACTERISTICS, continued PARAMETER MAX. UNIT CONDITIONS ® – Bi-direction pin with source capability of 6 mA and sink capability of 1 mA for INTEL PECI Input Low Voltage 0.275Vtt 0.5Vtt Input High Voltage 0.55Vtt 0.725Vtt Output Low Voltage 0.25Vtt...
Page 237: Ac Characteristics
W83627DHG 21.3 AC CHARACTERISTICS 21.3.1 AC Power Failure Resume Timing 1. Logical Device A, CR[E4h] bit7 = “0” and CR[E4h] bits[6:5] are selected to “OFF” state (“OFF” means always being turned off or the previous state is off) 3VCC PSOUT#...
Page 238 W83627DHG 2. Logical Device A, CR[E4h] bit7 = “0” and CR[E4h] bits[6:5] are selected to “ON” state (“ON” means always being turned on or the previous state is on) Publication Release Date: Aug, 22, 2007 -226- Version 1.4...
Page 239 W83627DHG 3. Logical Device A, CR[E4h] bit7 = “1” and CR[E4h] bits[6:5] are selected to “OFF” state (“OFF” means always being turned off or the previous state is off) 3VCC PSOUT# T ≒ 4S PSON# SUSB# RSMRST# 3VSB ACLOSS Publication Release Date: Aug, 22, 2007 -227- Version 1.4...
Page 240 W83627DHG 4. Logical Device A, CR[E4h] bit7 = “1” and CR[E4h] bits[6:5] are selected to “ON” state (“ON” means always being turned on or the previous state is on) 3VCC PSOUT# PSON# SUSB# RSMRST# 3VSB ACLOSS Publication Release Date: Aug, 22, 2007 -228- Version 1.4...
Page 241 3VCC SUSB# To ensure that VCC does not fall faster than VSB in various ATX Power Supplies, the W83627DHG adds the option of “user define mode” for the pre-defined state before AC power failure. BIOS can set the pre-defined state to be “On” or “Off”. According to this setting, the system chooses the state after the AC power recovery.
Page 242: Vsbgate# Timing - For Ube And Ubf Version Only
W83627DHG Logical Device A, CR E6h Power loss Last State Flag. (VBAT) R / W 0: ON 1: OFF 21.3.2 VSBGATE# Timing – for UBE and UBF Version Only VSBGATE# drives low only when SUSB# is active and VSBGATE# is reset to high...
Page 243: Clock Input Timing
W83627DHG 21.3.3 Clock Input Timing 48MHZ / 24MHZ PARAMETER UNIT Cycle to cycle jitter 300/500 Duty cycle 48MHZ / 24MHZ PARAMETER DESCRIPTION UNIT Clock cycle time 20.8 / 41.7 Clock high time/low time 9 / 19 10 / 21 Clock rising time/falling time (0.4V~2.4V)
Page 244: Peci And Sst Timing
W83627DHG 21.3.4 PECI and SST Timing SST / PECI Logic - 1 Minimum t Maximum t Next-bit Previous bit SST / PECI Logic - 0 Minimum t Maximum t Previous bit Next-bit SYMBOL UNITS Client 0.495 μs Originator 0.495 × t ×...
Page 245: Spi Timing
W83627DHG 21.3.5 SPI Timing DESCRIPTION SYMBOL Enable to first clock falling 25ns 35ns Disable after last clock rising 40ns 50ns Output hold time Input setup time Input hold time Publication Release Date: Aug, 22, 2007 -233- Version 1.4...
Page 246: Smbus Timing
W83627DHG 21.3.6 SMBus Timing SMBCLK HIGH SU:DAT SU:STO HD:STA SU:STA HD:DAT SMBDAT SYMBOL PARAMETER MIN. MAX.: UNITS Bus Free Time between Stop and Start Condition Hold time after (Repeated) Start Condition. After this period, the HD:STA first clock is generated...
Page 247: Floppy Disk Drive Timing
W83627DHG 21.3.7 Floppy Disk Drive Timing FDC: Data rate = 1MB, 500KB, 300KB, 250KB/sec. TYP. PARAMETER SYM. MIN. MAX. UNIT (NOTE 1) 1.0/1.6 DIR# setup time to STEP# µS /2.0/4.0 24/40 DIR# hold time from STEP# µS /48/96 6.8/11.5 7/11.7 7.2/11.9...
Page 248: Uart/Parallel Port
W83627DHG DIR# STEP# INDEX# RDATA# 21.3.8 UART/Parallel Port TEST PARAMETER SYMBOL MIN. MAX. UNIT CONDITIONS Baud Delay from Stop to Set Interrupt 9/16 SINT Rate 1000 Delay from IOR Reset Interrupt RINT Delay from Initial IRQ Reset to Transmit Baud...
Page 249 W83627DHG UART Receiver Timing Receiver Timing START (RECEIVER INPUT DATA) DATA BITS (5-8) PARITY STOP TSINT (INTERNAL SIGNAL) TSTI IRQ# (INTERNAL SIGNAL. READ RECEIVER BUFFER REGISTER) UART Transmitter Timing SOUT START (SERIAL OUT) START STOP DATA BITS (5-8) PARITY (1-2)
Page 250: Parallel Port Mode Parameters
W83627DHG 21.3.8.1. Modem Control Timing MODEM Control Timing START IOW# (INTERNAL SIGNAL, WRITE MCR) TMWO TMWO RTS#, DTR# CTS#, DSR#, DCD# TSIM TSIM TRIM TRIM (INTERNAL SIGNAL) IOR# (INTERNAL SIGNAL READ MSR) TSIM 21.3.9 Parallel Port Mode Parameters PARAMETER SYM.
Page 251: Parallel Port
W83627DHG 21.3.10 Parallel Port 21.3.10.1. Parallel Port Timing INIT, STROBE AUTOFD, SLCTIN PD<0:7> IRQ (SPP) (EPP or ECP) nFAULT (ECP) ERROR (ECP) 21.3.10.2. EPP Data or Address Read Cycle Timing Parameters PARAMETER SYM. MIN. MAX. UNIT WAIT Asserted to WRITE Deasserted...
Page 252 W83627DHG EPP Data or Address Read Cycle Timing Parameters, continued PARAMETER SYM. MIN. MAX. UNIT PD Hi-Z to Command Asserted Asserted to Command Asserted WAIT Deasserted to Command Deasserted Time out PD Valid to WAIT Deasserted μS PD Hi-Z to WAIT Deasserted...
Page 253 W83627DHG EPP Data or Address Read Cycle Timing Parameters, continued PARAMETER SYM. MIN. MAX. UNIT WAIT Deasserted to Command Deasserted Time out PD Valid to WAIT Deasserted μS PD Hi-Z to WAIT Deasserted 21.3.10.3. EPP Data or Address Read Cycle (EPP Version 1.9) EPP Data or Address Read Cycle (EPP Version 1.9)
Page 254 W83627DHG 21.3.10.4. EPP Data or Address Read Cycle (EPP Version 1.7) EPP Data or Address Read Cycle (EPP Version 1.7) STB# / WRITE PD<0:7> ADDRSTB DATASTB BUSY / WAIT Publication Release Date: Aug, 22, 2007 -242- Version 1.4...
Page 255 W83627DHG 21.3.10.5. EPP Data or Address Write Cycle Timing Parameters PARAMETER SYM. MIN. MAX. UNIT PBDIR Low to WRITE Asserted WAIT Asserted to WRITE Asserted WAIT Asserted to WRITE Change WAIT Asserted to PD Invalid PD Invalid to Command Asserted...
Page 256 W83627DHG EPP Data or Address Write Cycle Timing Parameters, continued PARAMETER SYM. MIN. MAX. UNIT μS Time out Command Deasserted to WAIT Asserted IOW Deasserted to WRITE Deasserted and PD invalid WRITE to Command Asserted 21.3.10.6. EPP Data or Address Write Cycle (EPP Version 1.9) EPP Data or Address Write Cycle (EPP Version 1.9)
Page 257 W83627DHG 21.3.10.7. EPP Data or Address Write Cycle (EPP Version 1.7) EPP Data or Address Write Cycle (EPP Version 1.7) STB# / WRITE PD<0:7> DATAST ADDRSTB BUSY / WAIT 21.3.10.8. Parallel Port FIFO Timing Parameters PARAMETER SYMBOL MIN. MAX. UNIT...
Page 258 W83627DHG 21.3.10.9. Parallel FIFO Timing PD<0:7> STB# BUSY 21.3.10.10. ECP Parallel Port Forward Timing Parameters PARAMETER SYMBOL MIN. MAX. UNIT nAUTOFD Valid to nSTROBE Asserted PD Valid to nSTROBE Asserted BUSY Deasserted to nAUTOFD Changed BUSY Deasserted to PD Changed...
Page 259 W83627DHG 21.3.10.11. ECP Parallel Port Forward Timing nAUTOFD PD<0:7> STB# BUSY 21.3.10.12. ECP Parallel Port Reverse Timing Parameters PARAMETER SYMBOL MIN. MAX. UNIT PD Valid to nACK Asserted nAUTOFD Deasserted to PD Changed nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted...
Page 260: Kbc Timing Parameters
W83627DHG 21.3.10.13. ECP Parallel Port Reverse Timing PD<0:7> nACK nAUTOFD 21.3.11 KBC Timing Parameters SYMBOL DESCRIPTION MIN. MAX. UNIT Address Setup Time from WRB Address Setup Time from RDB WRB Strobe Width RDB Strobe Width Address Hold Time from WRB...
Page 261 W83627DHG KBC Timing Parameters, continued SYMBOL DESCRIPTION MIN. MAX. UNIT μS Duration of CLK inactive μS Duration of CLK active Time from inactive CLK transition, used to time when μS the auxiliary device sample DATA μS Time of inhibit mode μS...
Page 262 W83627DHG 21.3.11.2. Read Cycle Timing A2, CSB ACTIVE D0 ~ D7 DATA OUT 21.3.11.3. Send Data to K/B CLOCK (KCLK) SERIAL DATA (KDAT) START STOP 21.3.11.4. Receive Data from K/B CLOCK (KCLK) SERIAL DATA (T1) START STOP Publication Release Date: Aug, 22, 2007 -250- Version 1.4...
Page 263: Gpio Timing Parameters
W83627DHG 21.3.11.5. Input Clock CLOCK 21.3.11.6. Send Data to Mouse MCLK MDAT START STOP 21.3.11.7. Receive Data from Mouse MCLK MDAT START STOP 21.3.12 GPIO Timing Parameters SYMBOL PARAMETER MIN. MAX. UNIT Write data to GPIO update 300(Note 1) SWITCH pulse width msec Note: Refer to Microprocessor Interface Timing for Read Timing.
Page 264 W83627DHG 21.3.12.1. GPIO Write Timing GPIO Write Timing diagram A0 – A15 VALID D0-7 VALID GPIO 10-17 PREVIOUS STATE VALID GPIO 20-25 tWGO Publication Release Date: Aug, 22, 2007 -252- Version 1.4...
Page 265: Lpc Timing
W83627DHG 21.4 LPC Timing SYMBOL DESCRIPTION MIN. MAX. UNIT Output Valid Delay Float Delay LAD[3:0] Setup Time LAD[3:0] Hold Time LFRAME# Setup Time LFRAME# Hold Time Publication Release Date: Aug, 22, 2007 -253- Version 1.4...
Page 266: Top Marking Specification
W83627DHG 606G9C28201234UB 1st line: Winbond logo 2nd line: part number: W83627DHG (Pb-free package) 3rd line: tracking code 606G9C28201234UB 606: packages made in '06, week 06 G: assembly house ID; G means GR, A means ASE, etc. 9: code version; 9 means code 009 C: IC revision;...
Page 267: Package Specification
W83627DHG 23. PACKAGE SPECIFICATION Dimension in mm Dimension in inch Symbol 0.25 0.35 0.45 0.010 0.014 0.018 2.57 2.72 2.87 0.101 0.107 0.113 0.10 0.20 0.30 0.004 0.008 0.012 0.10 0.15 0.20 0.004 0.006 0.008 13.90 14.00 14.10 0.547 0.551 0.555...
Page 268 Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

Winbond W83627DHG Manual

1 General Description

2 Features

3 Block Diagram

4 Pin Layout

5 Pin Description

6 Configuration Register Access Protocol

7 Hardware Monitor

8 Hardware Monitor Register Set

9 Serial Peripheral Interface

10 Floppy Disk Controller

11 Uart Port

12 Parallel Port

13 Keyboard Controller

14 Power Management Event

15 Serialized Irq

16 Watchdog Timer

17 General Purpose I/O

18 VID Inputs and Outputs

19 Pci Reset Buffers

20 Configuration Register

21 Specifications

22 Top Marking Specification

23 Package Specification

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