Performance/Throughput - Analog Devices ADSP-BF535 Blackfin Hardware Reference Manual

Flag Set on Both Edges Register (FIO_BOTH)
For all bits, when enabled for edge sensitivity, 0 - Single edge, 1 - Both edges.
0xFFC0 2418
PF15 Both Edges
PF14 Both Edges
PF13 Both Edges
PF12 Both Edges
PF11 Both Edges
PF10 Both Edges
PF9 Both Edges
PF8 Both Edges
Figure 15-11. Flag Set on Both Edges Register
When a given
Sensitivity register, setting the
register to Both edges results in an interrupt being generated on both the
rising and falling edges. This register has no effect on
defined as level sensitive.

Performance/Throughput

The pins are synchronized to the system clock (
PFx
ured as outputs, the programmable flags can transition once every 4
system clock cycles.
When configured as inputs, the overall system design should take into
account the potential latency between the core and the system clock.
Changes in the state of
being detectable by the processor. When configured for level-sensitive
interrupt generation, there is a minimum latency of 4
the time the flag is asserted and the time that program flow is interrupted.
When configured for edge-sensitive interrupt generation, an additional
ADSP-BF535 Blackfin Processor Hardware Reference
15 14 13 12 11 10 9
0 0 0 0 0 0 0
pin has been set to edge-sensitive in the Flag Interrupt
PFx
PFx
pins have a latency of 3
PFx
Programmable Flags
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
pin's bit in the Flag Set on Both Edges
0
0
Reset = 0x0000
PF0 Both Edges
PF1 Both Edges
PF2 Both Edges
PF3 Both Edges
PF4 Both Edges
PF5 Both Edges
PF6 Both Edges
PF7 Both Edges
pins that are
PFx
). When config-
SCLK
cycles before
SCLK
cycles between
SCLK
15-11