Performance/Throughput For Memdma; Dma Abort Conditions - Analog Devices ADSP-BF535 Blackfin Hardware Reference Manual

DMA Abort Conditions

Performance/Throughput for MemDMA

Performance and throughput numbers for the MemDMA controller can
be found in "DAB Performance" on page
Note that reads from EBIU lower performance because of the higher
latency of off-chip memory reads versus writes. Also, throughput is
reduced for partial bus-width transfers (that is, specifying 8- or 16-bit
DMA transfer widths instead of 32-bit transfer widths). Bus arbitration
induces additional latency.
Note the Memory DMA architecture achieves highest throughput on
block copies between external SDRAM and internal memory. L1-to-L2
transfer throughput is less, because only the DAB bus is employed.
The Memory DMA controller performs a burst transfer across the DAB
bus to fill the FIFO, then a burst transfer across the DAB bus to empty the
FIFO in a serialized fashion. Likewise, external-to-external block copies
are also serialized across the EAB bus.

Note that DMA descriptor list fetches always occur across the DAB
bus.
DMA Abort Conditions
These conditions cause a DMA abort:
• The processor clears the DMA Enable bit during active DMA
processing.
• The DMA channel does not relinquish the descriptor block back to
the processor, nor does it write back error status information. No
interrupt is generated.
9-44 ADSP-BF535 Blackfin Processor Hardware Reference
7-11.