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5.6.1.3
5.6.2
5.6.2.1
5.6.2.2
5.6.2.2.1
5.6.2.2.2
5.6.2.2.3
5.6.2.3
5.6.2.4
5.6.2.5
5.6.2.5.1
5.6.2.5.2
5.6.2.5.3
5.6.2.6
5.6.2.7
5.6.2.7.1
5.6.2.7.2
5.6.2.8
5.6.2.8.1
5.6.2.8.2
5.6.2.8.3
5.6.2.8.4
5.6.2.8.5
5.6.2.8.6
5.6.2.8.7
5.6.2.8.8
5.6.2.8.9
5.6.2.8.10
5.6;2.8.11
5.6.2.8.12
5.6.2.8.13
5.6.2.8.14
5.6.2.8.15
5.6.2.8.16
5.6.3
5.6.3.1
5.6.3.2
5.6.3.3
5.7
5.7.1
5.7.1.1
5.7.1.2
x
TABLE OF CONTENTS (Continued)
Title
Page
Number
On-Chip Hardware Breakpoint Overview ............................................. 5-64
Background Debug Mode ........................................................................... 5-65
Enabling BDM ........................................................................................... 5-65
BDM Sources ............................................................................................ 5-66
External BKPT Signal .......................................................................... 5-66
BGND Instruction .................................................................................. 5-66
Double Bus Fault. ................................................................................. 5-66
Entering BDM ............................................................................................ 5-66
Command Execution ................................................................................ 5-67
BDM Registers ........................................................................................... 5-67
Fault Address Register (FAR) ............................................................. 5-67
Return Program Counter (RPC) ......................................................... 5-67
Current Instruction Program Counter (PCC) .................................... 5-67
Returning from BDM ................................................................................. 5-68
Serial Interlace .......................................................................................... 5-68
CPU Serial Logic .................................................................................. 5-69
Development System Serial Logic .................................................... 5-71
Command Set ........................................................................................... 5-73
Command Format ................................................................................. 5-73
Command Sequence Diagram .......................................................... 5-74
Command Set Summary ..................................................................... 5-75
Read AID Register (RAREG/RDREG) ................................................ 5-76
Write AID Register (WAREGIWDREG) .............................................. 5-77
Read System Register (RSREG) ........................................................ 5-77
Write System Register (WSREG) ....................................................... 5-78
Read Memory Location (READ) ......................................................... 5-79
Write Memory Location (WRITE) ........................................................ 5-79
Dump Memory Block (DUMP) ............................................................ 5-80
Fill Memory Block (FILL) ...................................................................... 5-82
Resume Execution (GO) ...................................................................... 5-83
Call User Code (CALL) ........................................................................ 5-83
Reset Peripherals (RST) ...................................................................... 5-85
No Operation (NOP) ............................................................................. 5-85
Future Commands ................................................................................ 5-86
Deterministic Opcode Tracking .................................................................. 5-86
Instruction Fetch (IFETCH) .................................. , .................................... 5-86
Instruction Pipe (IPIPE) ............................................................................ 5-87
Opcode Tracking during Loop Mode .................................................... 5-88
Instruction Execution Timing ........................................................................... 5-88
Resource Scheduling .............................................................................. , ... 5-88
Microsequencer ........................................................................................ 5-89
Instruction Pipeline ................................................................................... 5-89
MC68340 USER'S MANUAL
MOTOROLA
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