Main(Pre/Rec) Schematic Diagram - JVC GR-D370UC Schematic Diagrams

MAIN(PRE/REC) SCHEMATIC DIAGRAM

MAIN(PRE/REC)
0 1
HID3
HID
TO CPU PBH
RECH
MONI_CHG
TL3501
TO MAIN IF(CN102) ENV_OUT
TO MAIN IF(CN102),
ATFI
PARAGON
ATF_GAIN
TO PARAGON
REC_ADJ
REC_CTL
VREF_1.1
TO PARAGON AGC_OUT
VRB_AGC
VRB_ATF
TO MAIN IF(CN102),
ATFI
PARAGON
REF_CLK
TO PARAGON
REC_DATA
REC_CLK
R3516
L3502 NQLC32M-100X
0Ω
REG_4.8V
L3505
OPEN
L3501 NQR0602-001X
REG_3.1V
L3503 NQR0602-001X
TO PARAGON,REG REG_2.5V
GND
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
48 47 46 45 44 43 42 41
C3517
0.01 LOGIC
PB_OUT
49
C3527
DC Servo
220p
AGC_IN
50
C3518
0.01 AGC_CTL
51
AGC_DET
52
C3519
0.001
PB_GND
53
Typ:-1.3dB
AGC_OUT
54 LPF AGC
C3520
Typ:7.8dB
0.01
AGC_BUFF_IN
55
C3521
0.1 REG_1.1V
56 REG BIAS
REC
AGC_BUFF_OUT
10.3dB
57
VRB_AGC
58
REG
C3522
4.7
MAIN_GND
59
ATF_GAIN
60
C3523
0.01
VCA_OUT
10dB
VCA
61
BPF
C3524 Typ:24dB
0.01
ATF_IN
62 BIAS
F.F.
C3525
4.7 VRB_ATF
63 REG
ATF_OUT F0 AUTO
64
1 2 3 4 5 6 7 8
R3517
56k
R3518
6.2k
(No.YF124)2-17 2-18(No.YF124)
R3519 R3520
30k 2.7k
IC3501
JCY0132
40 39 38 37 36 35 34 33
HEAD_GND
32
Dumping
DX3
31
X3
30
30dB
Y3
29
DY3
28
10dB 10dB HEAD_GND
27
R3507
DX2 240
26
X2
25
30dB
Y2
24
R3506
DY2 240
23
HEAD_GND
22
R3505
DX1 240
REC_MONI
21
X1
20
30dB
Y1
19
R3504
240
DY1
18
HEAD_GND
17
For Shield Case Positioning
9 10 11 12 13 14 15 16
yf124_y20399001a_rev0.1
GND
1F
1S
GND
TO MAIN IF(CN3501)
GND
2F
2S
GND
R3521
0