Yamaha 01x Service Manual page 30

O1X
SGH603064F-62F (XV973A00) REC2 (Gate Array)
PIN
NAME I/O
NO.
1 RA1 I
2 RB1 I
Encoder input
3 RA2 I
4 RB2 I
5 V Ground
SS
6 RA3 I
7 RB3 I
Encoder input
8 RA4 I
9 RB4 I
10 V Ground
SS
11 RA5 I
12 RB5 I
Encoder input
13 RA6 I
14 RB6 I
15 V Ground
SS
16 RA7 I
17 RB7 I
Encoder input
18 RA8 I
19 RB8 I
20 A0 I
21 A1 I Address bus
22 A2 I
23 V Ground
SS
24 RDN I Read
25 CSN I Chip select
26 V Power supply +5V
DD
27 ASN I Address strobe
28 A3N I Address bus
29 SEL I Bus select
30 NC
31 NC Not used
32 NC
MD8408B (XZ762A00) PHY (Physical Layer)
PIN
NAME I/O
NO.
1 LREQ I Link request
2 DVDD - Digital power supply
3 SCLK O 49.152MHz link system clock
4 DVSS - Digital ground
5 CTL0 I/O
PHY-Link interface control signals
6 CTL1 I/O
7 DVDD - Digital power supply
8 D0 I/O
9 D1 I/O
PHY-Link interface data signals
10 D2 I/O
11 D3 I/O
12 DVSS - Digital ground
13 D4 I/O
14 D5 I/O
PHY-Link interface data signals
15 D6 I/O
16 D7 I/O
17 DVDD -
Digital power supply
18 DVDD -
19 TEST0 I
Test mode control terminals
20 TEST1 I
21 DVSS - Digital ground
22 DVDD - Digital power supply
23 DVSS - Digital ground
External capacitor connection terminal for
24 Purb I
power-up reset
25 AGND - Analog ground
26 NC -
Non connection
27 NC -
28 AVDD1 - Analog power supply 1
29 XEXT I/O For crystal connections. Connection
30 XTAL I/O terminals for quartz crystal oscillators.
31 AGND - Analog ground.
Analog power supply 1
32 AVDD1 -
A terminal for Cable Power Status detection
33 CPS I
34 AGND - Analog ground
30
FUNCTION
FUNCTION
PIN
NAME I/O
NO.
33 D0 O
Data bus
34 D1 O
35 V Ground
SS
36 D2 O
Data bus
37 D3 O
38 V Ground
SS
39 D4 O
Data bus
40 D5 O
41 V Ground
SS
42 D6 O
Data bus
43 D7 O
44 V Ground
SS
45 NC
Not used
46 NC
47 RA9 I
48 RB9 I
49 RA10 I
50 RB10 I
51 RA11 I
52 RB11 I Encoder input
53 RA12 I
54 RB12 I
55 RA13 I
56 RB13 I
57 RA14 I
58 V Power supply +5V
DD
59 RB14 I
60 RA15 I
61 RB15 I Encoder input
62 RA16 I
63 RB16 I
64 V Ground
SS
PIN
NAME I/O
NO.
35 AVDD1 - Analog power supply 1
36 TpBias1 O
A cable bias output terminal
37 TpBias0 O
38 TpB1n I/O A negative-phase-sequence I/O terminal
39 TpB1p I/O A positive-phase-sequence I/O terminal
40 TpA1n I/O A negative-phase-sequence I/O terminal
41 TpA1p I/O A positive-phase-sequence I/O terminal
42 TpB0n I/O A negative-phase-sequence I/O terminal
43 TpB0p I/O A positive-phase-sequence I/O terminal
44 TpA0n I/O A negative-phase-sequence I/O terminal
45 TpA0p I/O A positive-phase-sequence I/O terminal
46 AGND - Analog ground
47 AVDD2 - Analog power supply 2
48 DVSS - Digital ground
These pin define the initial value of the disable bits in the
49 Disabled1 I
PHY port status page after a hardware reset, and the
condition of the terminal of the level is reflected.
50 Disabled0 I
51 S200 I Phy Speed Control signal
52 LDSEL I Timing setting terminal for the PHY-Link interface
53 DVDD - Digital power supply
54 En_Accel I This bit defines the initial value of the
Enab_accel bit after a hardware reset
This bit defines the initial value of the
55 En_Multi I
Enab_multi bit after hardware reset
56 SR I Suspend/Resume function control signal
57 DIRECT I Defines operation mode setting terminal for
the PHY-Link interface
58 DVSS - Digital ground
59 LinkOn O Link-On signal output
60 PC2 I
61 PC1 I Power Class
62 PC0 I
Configuration management capable setting terminal
63 CMC I
64 LPS I Link power status
DM: IC402
FUNCTION
MLN2: IC010
FUNCTION