Sanyo CE29FFV2-F Service Manual page 17

• PHI-2 detector and Sandcastle generator: The PHI-2 detector performs a stable picture. It synchronises the
horizontal oscillator with the horizontal flyback signal (pin 41, FBISO) to generate the horizontal output (pin
40, HOUT). . The components associated with the PHI-2 are connected to the pin 42 (PH2LF). The picture
phase is adjusted via I2C (HOR SHIFT in the service menu). The flyback input pin 41 (FBISO) is combined
with the sandcastle output and provides a three level sandcastle signal. The levels are: 2V " vertical retrace;
3V" horizontal retrace; 5.3V "Burstkey.
• Horizontal output (pin 40, HOUT): It is a open collector type and the duty cycle in normal condition is 45%
high and 55% low. A built in slow start/stop circuit ensures a smooth start/stop behaviour of the line
deflection. Also during switching off via stand by the RGB drive is set to maximum to discharge the EHT
CRT capacitance.
• Coincidence detector
• Vertical sync separator
• Vertical divider
14.3 Geometry
• Vertical sawtooth generator: it delivers the reference signals for vertical and horizontal geometry processor.
An accurate reference current is used to charge the external capacitor during vertical scan. The resistor R426
in pin 52 (IREF) determines this reference current. It is a Metal Film resistor with 1% tolerance in order to
provide a temperature stabilisation and lower dispersion. The ramp capacitor (C425) is connected to pin 51
(VCS). It is a polycarbon one in order to provide temperature stabilisation.
• Vertical geometry processor: it performs the sawtooth signal and it has a differential current output in pins 47
(VDRA) and 46 (VDRB) for a DC coupled vertical output stage (drive). Control functions accessible via I2C
are VERT SLOPE, VERT AMPL, S-CORREC, VERT SHIFT (see service menu).
• Horizontal geometry processor (E/W drive): it has a single-ended current output for E-W drive (pin 45 EWD).
This current is amplified and applied to the diode modulator of the horizontal deflection. The adjustments are
accessible via I2C (EW AMPLIT, PARABOLA, CORNER PAR, TRAPEZIUM in the service menu).
• EHT tracking (pin 50, EHTO): this tracking makes the picture size independent of EHT variations due to the
beam current.
14.4 Filters and video switches
• Video signal selection: the input selector has CVBS_INT(pin 13), CVBS_EXT (pin 17), CVBS/Y (pin11) and
CHROMA (pin 10) as inputs which can be selected via I2C bus. The selected video signal is present at pin 38
(CVBSO).
• Filter calibration: it is an auto-tuning loop which calibrates every field retrace. The filters are the chrominance
bandpass and the chrominance trap.
• Chrominance signal processing: this circuit keeps constant the colour saturation level.
• Luminance signal processing: the selected video signal is supplied to the chrominance trap. The output signal
is supplied to the peaking and coring stages. Both are controlled via I2C bus. The output (pin 28 LUMOUT) is
fed through a band pass filter (L409, R439 and C440) as internal luminance signal (pin 27 LUMIN).
14.5 Colour decoder
• PLL/VCXO: The PLL operates during the burstkey period. In the lock condition the VCXO reference signal
(X400 in pin 35) and the burstkey become synchronous. An optimum transient response can be chosen with
the loop filter connected to pin 36 (DET). The reference output (4,43MHz in pin 33) can be used for comb
filter applications.
• PAL/NTSC Demodulation: The reference signals from the VCXO are supplied to the HUE phase rotator; its
outputs are supplied to the (R-Y) and (B-Y) demodulators. The (B-Y)/(R-Y) baseband signals are filtered and
supplied via the PAL/SECAM switch to the internal baseband delay line. The signals from the delay line are
RYO (pin 30) and BYO (pin 29).
• SECAM Demodulation: It is realised with a PLL type demodulator. The SECAM reference voltage is
generated at pin 16 (SECPLL). The demodulated signal is distributed to the (R-Y) and (B-Y) amplifiers and
via de PAL/SECAM switch to the baseband delay line.
• Automatic system manager: it can identify PAL/SECAM/NTSC colour standards. The different possibilities
are controlled by the I2C bus.
14.6 RGB Processing
• (R-Y)/(B-Y) processing/matrixing: The amplitude of this signals (pins 32 (RYI) and 31 (BYI)) is controlled via
the I2C bus (colour saturation) and also this signals are supplied to dynamic skin control. After the R-Y and
B-Y matrixing, the output signals are added with the luminance signal in order to generate the internal RGB
signals.
• RGB selector: it is controlled by the FB signal in signal 26 (RGBIN). The external RGB signals are present in
pins 23 (RI), 24 (GI) and 25 (BI). The RGB selector output is fed to then RGB control.
Service Manual MS CE25FV2-E
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