Sharp UP-600 Service Manual page 46

15. TCP/IP STACK
The LAN of the UP-600 uses as the protocol Ethernet, which supports
TCP/IP.
The interface with the TCP/IP board is achieved through 2 interrupt
signals and dual-port RAM.
The decode of dual-port RAM is located in the following space:
DP-RAM: F20000H - F2FFFFH (max. 64 KB)
The interruption from the TCP/IP is allocated as follows:
EXINTO: INTSW (SLAVE WRITE interrupt) bit 6 of 00FF81H
EXINT1: INTSR (SLAVE READ interrupt) bit 0 of 00FF80H
<TCP/IP connector terminals>
Signal Name Pin No.
+5V 2
+5V 4
A14 6
A12 8
HWR 10
A10 12
A0 14
A2 16
A4 18
A6 20
A8 22
D7 24
D5 26
D3 28
D1 30
LRES 32
INTSW 34
- 36
GND 38
GND 40
16. RS232
Two standard RS232 channels are compatible with the ER-A5RS.
However, while the ER-A5RS uses the IRQ2 terminal of the CPU for
interruption of the RS232, the UP-600 cannot use the IRQ1 terminal
instead of it. (The IRQ2 terminal is used for IR as the SCK1 terminal.)
The standard RS232 is fixed to the logic channels 1 and 8. Use the
channels 2, 3, 4, 5, 6 and 7 for the ER-A5RS.
17. MCR
This paragraph describes the MCR option (UP-E13MR) control de-
fined by the UP-600 hardware architecture.
3 channels of the serial port (interchangeable with 8251) built in the
MPCA9 are used. 3 tracks of data are read simultaneously. (UP-
E13MR)
Pin No. Signal Name
1 +5V
3 +5V
5 A15
7 A13
9 DPCS
11 A11
13 RD
15 A1
17 A3
19 A5
21 A7
23 A9
25 D6
27 D4
29 D2
31 D0
33 INTSR
35 -
37 GND
39 GND
1) CPU INTERFACE
The CPU interface for the USART (8251) and magnetic card reader
(MCM-21) in the UP-600 system is shown below.
Integrated as MPCA8
in the UP-600 system.
CPU
MPCA7
RCVRDY1
INTMCR
ICI INTMCR
RCVRDY2
Signal description
RCP1 TRACK 1 CLOCK PULSE
RDD1 TRACK 1 DATA SIGNAL
RCP2 TRACK 2 CLOCK PULSE
RDD2 TRACK 2 DATA SIGNAL
RCP3 TRACK 3 CLOCK PULSE
RCD3 TRACK 3 DATA SIGNAL
CLS1 TRACK 1 CARD DETECTION SIGNAL
CLS2 TRACK 2 CARD DETECTION SIGNAL
CLS3 TRACK 3 CARD DETECTION SIGNAL
RCVRDY1 TRACK 1 DATA RECEIVING SIGNAL
RCVRDY2 TRACK 2 DATA RECEIVING SIGNAL
RCVRDY3 TRACK 3 DATA RECEIVING SIGNAL
INTMCR INTERRUPT SIGNAL OR-SYNTHESIZED from
RCVRDY and SYNC input
2 chip select signals for the 8251 are generated inside MPCA8.
2) MCR INTERFACE
The operating timing of the MCR interface signals is given below.
(1) Example of timing
CLS1/CLS2
CLS3
RCP1/RCP2
RCP3
RDD1/RDD2
RDD3
(2) Detailed timing (relation between DATA and CLOCK PULSE)
RCP1/RCP2
RCP3
RDD1/RDD2 "0"
RDD3
Approx. 16µ s
The "NULL" CODE is basically written prior to the opening code. The
opening code detection algorithm is considered because data may
become corrupt before and after the CARD detection signal due to a
worn magnet stripe.
8251 x 2
RCP1
RCVCLK1
RCP1
RDD1
RCVDT1
RCP2
RCVCLK2
RDD2
RCVDT2
CLS1
/DSR1
CLS2
/DSR2 CLS2
RCP3
RCVCLK3
RCVRDY1
RDD3
RCVDT3
CLS3
/DSR3
RCVRDY2
RCVRDY3
CLS1,
CLS2
SYNC
"1" "1"
Min. 5µ s