Ni-579X Configuration Design Library - National Instruments NI 5791R User Manual And Specifications

Creating a Host VI
1. In the Project Explorer window, right-click My Computer and select New»VI to open
a blank VI.
2. Select Window»Show Block Diagram to open the VI block diagram.
3. Add the Open FPGA VI Reference function from the FPGA Interface palette to the block
diagram.
4. Right-click the Open FPGA VI Reference function and select Configure Open FPGA
VI Reference.
5. In the Configure Open FPGA VI Reference dialog box, select VI in the Open section.
6. In the Select VI dialog box, select your project under your device and click OK.
7. Click OK in the Configure Open FPGA VI Reference dialog box. The target name
appears under the Open FPGA VI Reference function in the block diagram.
8. Open the FPGA Interface palette.
9. Add any Read/Write Control or Invoke Method nodes necessary to configure and
communicate with your FPGA VI.
10. Add the Close FPGA VI Reference function to your block diagram.
11. Wire the FPGA VI Reference function to the Close FPGA VI Reference function.
12. Save and close the VI.
13. Save the project.
Run the Host VI
1. Open the front panel of your host VI.
2. Click the Run button to run the VI.

NI-579x Configuration Design Library

The NI-579x Configuration Design Library consists of host and FPGA VIs that provide an
interface to configure the hardware on the NI 5791.
The library allows you to perform the following actions:
• Configure the mixers
• Configure the RF signal path, including attenuators, amplifiers, and filters
• Read from and write to the EEPROM
• Configure the reference level for the Rx channel and the output power for the Tx channel
• Configure the clocks
• Reinitialize the CLIP
• Query for CLIP errors
The NI-579x Configuration Design Library relies on the Register Bus Design Library. The
Register Bus provides a packet-based configuration interface which exposes all of the address
spaces of the configurable chips and subsystems of the adapter module, without requiring
hundreds of controls and indicators on your FPGA VI front panel.
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