Changed Retentive Behavior For Cpus With Firmware >= V2.1.0; Fms/Cps With Separate Mpi Address In The Central Rack Of A Cpu 315-2 Pn/Dp / Cpu 317 - Siemens Simatic S7-300 Technical Data Manual

Cpu 31xc and cpu 31x
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A.1.12
Changed retentive behavior for CPUs with firmware >= V2.1.0
Changed retentive behavior for CPUs with firmware >= V2.1.0
For data blocks for these CPUs
• you can set the retentive response in the block properties of the DB.
• Using SFC 82 "CREA_DBL" -> Parameter ATTRIB, NON_RETAIN bit, you can specify if
A.1.13
FMs/CPs with separate MPI address in the central rack of a CPU 315-2 PN/DP /
CPU 317

FMs/CPs with separate MPI address in the central rack of a CPU 315-2 PN/DP / CPU 317

All CPUs, except CPU 315-2 PN/DP, CPU 317
and CPU 318-2 DP
If there are FM/CPs with their own MPI address in
the central rack of an S7-300, then they are in the
exact same CPU subnet as the CPU MPI station.
When exchanging your existing CPU with a CPU 315-2 PN/DP / CPU 317, you therefore
need to:
• replace the CPU in your STEP 7 project with the CPU 315-2 PN/DP / CPU 317.
• Reconfigure the OPs. The control and the destination address must be reassigned (= the
• Reconfigure the project data for FM/CP to be loaded to the CPU.
This is required for the FM/CP in this rack to remain "available" to the OP/PG.
CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05
the actual values of a DB should be maintained at POWER OFF/ON or STOP-RUN
(retentive DB) or if the start values should be read from the load memory (non-retentive
DB).
MPI address of the CPU 315-2 PN/DP / CPU 317 and the slot of the respective FM)
A.1 Information about upgrading to a CPU 31xC or CPU 31x
CPU 315-2 PN/DP, CPU 317 and CPU 318-2 DP
If there are FM/CPs with their own MPI address
in the central rack of an S7-300, then the CPU
forms its own communication bus via the
backplane bus with these FM/CPs, which are
separated from the other subnets.
The MPI address of such an FM/CP is no longer
relevant for the stations on other subnets. The
communication to the FM/CP is made via the MPI
address of the CPU.
Appendix
A-9

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