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One of two debugging modes. When debugging is performed in halt mode,
Halt mode
the core stops when it encounters a watchpoint or breakpoint, and is
isolated from the rest of the system. See also
See
ICE
A mathematical quantity that when applied to itself under a given binary
Idempotent
operation equals itself.
In-circuit emulator
An
hardware and software. Debuggable ARM processors such as the
ARM720T processor have extra hardware to assist this process.
See also
Interrupt request.
IRQ
Joint Test Action Group
The name of the organization that developed standard IEEE 1149.1. This
standard defines a boundary-scan architecture used for in-circuit testing of
integrated circuit devices.
See
JTAG
This register holds the address of the next instruction after a branch with
Link register
link instruction.
Little-endian memory
Memory organization where the most significant byte of a word is at a
higher address than the least significant byte.
See
LR
A complex logic block with a defined interface and behavior. A typical VLSI
Macrocell
system will comprise several macrocells (such as an ARM7TDMI-S core, an
ETM7, and a memory block) plus application-specific logic.
Memory Management Unit
Allows control of a memory system. Most of the control is provided through
translation tables held in memory.
See
MMU
ARM720T CORE CPU MANUAL
In-circuit emulator.
In-Circuit Emulator
(ICE), is a device that aids the debugging of
EmbeddedICE-RT.
Joint Test Action Group
Link register
Memory Management Unit
EPSON
Monitor mode
.
Glossary
.
Glossary-3
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