Fujitsu MHG2102AT - Mobile 10 GB Hard Drive Product Manual
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Fujitsu MHG2102AT - Mobile 10 GB Hard Drive Product Manual

Fujitsu MHG2102AT - Mobile 10 GB Hard Drive Product Manual

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C141-E070-02EN
MHG2102AT, MHH2064AT,
MHH2048AT, MHH2032AT
DISK DRIVES
PRODUCT MANUAL

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  • Page 1 C141-E070-02EN MHG2102AT, MHH2064AT, MHH2048AT, MHH2032AT DISK DRIVES PRODUCT MANUAL...
  • Page 2 “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully. FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.
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  • Page 4: Revision History

    Revision History (1/1) Edition Date Revised section (*1) Details (Added/Deleted/Altered) 1998-11-20 — — 1999-04 1-2, 1-4 to 1-7, 2-2 to 2-4, 3-5 to 3-14, 4-2, 4-3, 5-32, 5-34, 6-7 revised. *1 Section(s) with asterisk (*) refer to the previous edition when those were deleted. C141-E070-02EN...
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  • Page 6 Preface This manual describes the MHG Series and MHH Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the ATA interface. This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems.

  • Page 7: Operating Environment

    Preface Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: This indicates a hazarous situation could result in minor or moderate personal injury if the user does...
  • Page 8 “Disk drive defects” refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
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  • Page 10: Important Alert Items

    Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. Also, damage to the predate or other property, may occur if the user does not perform the procedure correctly.
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  • Page 12: Manual Organization

    Manual Organization MHG2102AT, MHH2064AT • Device Overview MHH2032AT • Device Configuration • Installation Conditions DISK DRIVE • Theory of Device Operation PRODUCT MANUAL • Interface (C141-E070) • Operations <This manual> MHG2102AT, MHH2064AT • Maintenance and Diagnosis MHH2032AT • Removal and Replacement Procedure DISK DRIVE MAINTENANCE MANUAL (C141-F034)
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  • Page 14: Table Of Contents

    Contents CHAPTER 1 Device Overview................ 1-1 Features 1.1.1 Functions and performance 1.1.2 Adaptability 1.1.3 Interface Device Specifications 1.2.1 Specifications summary 1.2.2 Model and product number Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate 1-10 Media Defects 1-10 CHAPTER 2 Device Configuration..............
  • Page 15 Contents CHAPTER 3 Installation Conditions..............3-1 Dimensions Mounting Cable Connections 3.3.1 Device connector 3.3.2 Cable connector specifications 3-10 3.3.3 Device connection 3-10 3.3.4 Power supply connector (CN1) 3-11 Jumper Settings 3-11 3.4.1 Location of setting jumpers 3-11 3.4.2 Factory default setting 3-12 3.4.3 Master drive-slave drive setting 3-12...
  • Page 16 Contents 4.6.1 Read/write preamplifier (PreAMP) 4.6.2 Write circuit 4-10 4.6.3 Read circuit 4-12 4.6.4 Digital PLL circuit 4-13 Servo Control 4-14 4.7.1 Servo control circuit 4-14 4.7.2 Data-surface servo format 4-18 4.7.3 Servo frame format 4-18 4.7.4 Actuator motor control 4-19 4.7.5 Spindle motor control 4-20...
  • Page 17 Contents 5.5.2 Phases of operation 5-81 5.5.2.1 Ultra DMA burst initiation phase 5-81 5.5.2.2 Data transfer phase 5-82 5.5.2.3 Ultra DMA burst termination phase 5-82 5.5.3 Ultra DMA data in commands 5-83 5.5.3.1 Initiating an Ultra DMA data in burst 5-83 5.5.3.2 The data in transfer 5-84...
  • Page 18 Contents CHAPTER 6 Operations ................. 6-1 Device Response to the Reset 6.1.1 Response to power-on 6.1.2 Response to hardware reset 6.1.3 Response to software reset 6.1.4 Response to diagnostic command Address Translation 6.2.1 Default parameters 6.2.2 Logical address Power Save 6.3.1 Power save mode 6.3.2 Power commands 6-11...
  • Page 19 Contents Illustrations Figures Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on Figure 2.1 Disk drive outerview (the MHG Series and MHH Series) Figure 2.2 Configuration of disk media heads Figure 2.3 1 drive system configuration Figure 2.4 2 drives configuration Figure 3.1 Dimensions (MHG/MHH series) Figure 3.2 Orientation (Sample: MHG2102AT) Figure 3.3 Mounting frame structure...
  • Page 20 Contents Figure 5.4 Protocol for command abort 5-75 Figure 5.5 WRITE SECTOR(S) command protocol 5-76 Figure 5.6 Protocol for the command execution without data transfer Figure 5.7 Normal DMA data transfer 5-79 Figure 5.8 An example of generation of parallel CRC 5-93 Figure 5.9 Ultra DMA termination with pull-up or pull-down 5-94...
  • Page 21 Contents Table 3.1 Surface temperature measurement points and standard values Table 3.2 Cable connector specifications 3-10 Table 4.1 Self-calibration execution timechart Table 4.2 Write precompensation algorithm 4-10 Table 5.1 Signal assignment on the interface connector Table 5.2 I/O registers Table 5.3 Command code and parameters 5-14 Table 5.4...

  • Page 22: Device Overview

    CHAPTER 1 Device Overview Features Device Specifications Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate Media Defects Overview and features are described in this chapter, and specifications and power requirement are described. The MHG Series and MHH Series are 2.5-inch hard disk drives with built-in disk controllers.

  • Page 23: Features

    Device Overview 1.1 Features 1.1.1 Functions and performance The fillowing features of the MHG Series and MHH Series are described. (1) Compact The MHG2102AT has 3 disks, and its height is 12.5 mm (0.492 inch). The MHH2064AT, MHH2048AT and MHH2032AT have 1 disk or 2 disks of 65 mm (2.5 inches) diameter, and its height is 9.5 mm (0.374 inch).

  • Page 24: Interface

    1.1 Features 1.1.3 Interface (1) Connection to interface With the built-in ATA interface controller, the disk drives (the MHG Series and MHH Series) can be connected to an ATA interface of a personal computer. (2) 512-KB data buffer The disk drives (the MHG Series and MHH Series) uses a 512-KB data buffer to transfer data between the host and the disk media.

  • Page 25: Device Specifications

    Device Overview 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specfications of the disk drives (MHG2102AT/MHH2064AT/ MHH2048AT/MHH2032AT). Table 1.1 Specifications (1/2) MHG2102AT MHH2064AT MHH2048AT MHH2032AT Format Capacity (*1) 10.0 GB 6.4 GB 4.3 GB 3.2 GB Number of Heads Number of Cylinders (User) 11,173 Bytes per Sector...

  • Page 26: Model And Product Number

    1.3 Power Requirements Under the CHS mode (normal BIOS specification), formatted capacity, number of cylinders, number of heads, and number of sectors are as follows. Table 1.1 Specifications (2/2) Model Formatted Capacity No. of Cylinder No. of Heads No. of Sectors MHG2102AT 8,455.20 MB 16,383...

  • Page 27: Figure 1.1 Current Fluctuation (Typ.) At +5V When Power Is Turned On

    Device Overview (3) Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation. Table 1.3 Current and power dissipation Typical RMS Current Typical Power (*3) MHG Series MHH Series MHG Series MHH Series Spin up (*1) 0.9 A 0.9 A 4.5 W 4.5 W...

  • Page 28: Environmental Specifications

    1.4 Environmental Specifications (5) Power on/off sequence The voltage detector circuits (the MHG Series and MHH Series) monitor +5 V. The circuits do not allow a write signal if either voltage is abnormal. These prevent data from being destroyed and eliminates the need to be concerned with the power on/off sequence.

  • Page 29: Acoustic Noise

    Device Overview 1.5 Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Acoustic noise specification Item Specification Sound Pressure • Idle mode (DRIVE READY) 30 dBA typical at 1 m Note: Measure the noise from the cover top surface. 1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification.

  • Page 30: Reliability

    1.7 Reliability 1.7 Reliability (1) Mean time between failures (MTBF) Conditions of 300,000 h Power-on time 250H/month or less 3000H/years or less Operating time 20% or less of power-on time CSS operations 50/day or less Total 50,000 or less Power on/off 1/day or more needed.

  • Page 31: Error Rate

    Device Overview 1.8 Error Rate Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media. (1) Unrecoverable read error Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 10 times when reading...

  • Page 32: Chapter 2 Device Configuration

    CHAPTER 2 Device Configuration Device Configuration System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate. C141-E070-01EN...

  • Page 33: Device Configuration

    Device Configuration 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter. MHG21xxAT MHH20xxAT Figure 2.1 Disk drive outerview (the MHG Series and MHH Series)

  • Page 34: Figure 2.2 Configuration Of Disk Media Heads

    2.1 Device Configuration Head Head Head MHG2102AT MHH2064AT MHH2048AT MHH2032AT Figure 2.2 Configuration of disk media heads (3) Spindle motor The disks are rotated by a direct drive Hall-less DC motor. (4) Actuator The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat.

  • Page 35: System Configuration

    Device Configuration 2.2 System Configuration 2.2.1 ATA interface Figures 2.3 and 2.4 show the ATA interface system configuration. The drive has a 44-pin PC AT interface connector and supports the PIO transfer at 16.6 MB/s (ATA-3, Mode 4), the DMA transfer at 16.6 MB/s (ATA-3, Multiword mode 2) and also the U-DMA at 33.3 MB/s (ATA-3, Mode 2).
  • Page 36 2.2 System Configuration HA (host adaptor) consists of address decoder, driver, and receiver. ATA is an abbreviation of “AT attachment”. The disk drive is conformed to the ATA-4 interface. At high speed data transfer (PIO mode 3, mode 4, or DMA mode 2 U-DMA mode 2), occurence of ringing or crosstalk of the signal lines (AT bus) between the HA and the disk drive may be a great cause of the obstruction of system reliability.
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  • Page 38: Installation Conditions

    CHAPTER 3 Installation Conditions Dimensions Mounting Cable Connections Jumper Settings This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives. C141-E070-01EN...

  • Page 39: Dimensions

    Installation Conditions 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. Figure 3.1 Dimensions (MHG series) (1/2) C141-E070-01EN...
  • Page 40 3.1 Dimensions Figure 3.1 Dimensions (MHH series) (2/2) C141-E070-01EN...

  • Page 41: Mounting

    Installation Conditions 3.2 Mounting (1) Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. gravity (a) Horizontal –1 (b) Horizontal –1 gravity (c) Vertical –1 (d) Vertical –2 gravity (e) Vertical –3 (f) Vertical –4 Figure 3.2 Orientation (Sample: MHG2102AT) C141-E070-01EN...

  • Page 42: Figure 3.3 Mounting Frame Structure

    3.2 Mounting (2) Frame The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to SG. Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3. The tightening torque must be 5 kgcm.

  • Page 43: Figure 3.4 Location Of Breather

    Installation Conditions Because of breather hole mounted to the HDD, do not allow this to close during mounting. Locating of breather hole is shown as Figure 3.4 in both MHG series and MHH series. For breather hole of Figure 3.4, at least, do not allow its around 3 to block.

  • Page 44: Figure 3.5 Surface Temperature Measurement Points (Sample: Mhg2102At)

    3.2 Mounting (4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be considered to prevent the DE surface temperature from exceeding 60 C.

  • Page 45: Figure 3.6 Service Area (Sample: Mhg2102At)

    Installation Conditions (5) Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. Mounting screw hole Cable connection Mounting screw hole Figure 3.6 Service area (Sample: MHG2102AT) Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers.

  • Page 46: Cable Connections

    3.3 Cable Connections 3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.7 shows the locations of these connectors and terminals. Connector, setting pins Figure 3.7 Connector locations (Sample: MHG2102AT) C141-E070-02EN...

  • Page 47: Cable Connector Specifications

    Installation Conditions 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications Name Model Manufacturer ATA interface and power Cable socket 89361-144 BERG supply cable (44-pin type) (44-pin type) For the host interface cable, use a ribbon cable. A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines.

  • Page 48: Power Supply Connector (Cn1)

    3.4 Jumper Settings 3.3.4 Power supply connector (CN1) Figure 3.9 shows the pin assignment of the power supply connector (CN1). Figure 3.9 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.10 shows the location of the jumpers to select drive configuration and functions.

  • Page 49: Factory Default Setting

    Installation Conditions 3.4.2 Factory default setting Figure 3.11 shows the default setting position at the factory. Open Figure 3.11 Factory default setting 3.4.3 Master drive-slave drive setting Master device (device #0) or slave device (device #1) is selected. Open Short Open Open (a) Master drive...

  • Page 50: Csel Setting

    3.4 Jumper Settings 3.4.4 CSEL setting Figure 3.13 shows the cable select (CSEL) setting. Open Short Note: The CSEL setting is not depended on setting between pins Band D. Figure 3.13 CSEL setting Figure 3.14 and 3.15 show examples of cable selection using unique interface cables.

  • Page 51: Figure 3.15 Example (2) Of Cable Select

    Installation Conditions Figure 3.15 Example (2) of Cable Select 3-14 C141-E070-02EN...

  • Page 52: Theory Of Device Operation

    CHAPTER 4 Theory of Device Operation Outline Subassemblies Circuit Configuration Power-on Sequence Self-calibration Read/write Circuit Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.

  • Page 53: Outline

    Theory of Device Operation 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method. 4.2 Subassemblies The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).

  • Page 54: Spindle

    4.2 Subassemblies Head Head Head MHG2102AT MHH2064AT MHH2048AT MHH2032AT Figure 4.1 Head structure 4.2.3 Spindle The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 4,200 rpm 1%.

  • Page 55: Circuit Configuration

    Theory of Device Operation 4.3 Circuit Configuration Figure 4.2 shows the disk drive circuit configuration. (1) Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC). The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.

  • Page 56: Figure 4.2 Circuit Configuration

    4.3 Circuit Configuration 16 bit Figure 4.2 Circuit Configuration C141-E070-01EN...

  • Page 57: Power-On Sequence

    Theory of Device Operation 4.4 Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.

  • Page 58: Self-Calibration

    4.5 Self-calibration Figure 4.3 Power-on operation sequence 4.5 Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM tarque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents (1) Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution.

  • Page 59: Execution Timing Of Self-Calibration

    Theory of Device Operation The forces are compensated by adding the measured value to the specified current value to the power amplifier. This makes the stable servo control. To compensate torque varing by the cylinder, the disk is divided into 8 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration.

  • Page 60: Command Processing During Self-Calibration

    4.6 Read/write Circuit Table 4.1 Self-calibration execution timechart Time elapsed Time elapsed (accumulated) At power-on Initial calibration About 5 minutes About 5 minutes About 5 minutes About 10 minutes About 10 minutes About 20 minutes About 10 minutes About 30 minutes About 15 minutes About 45 minutes About 15 minutes...

  • Page 61: Write Circuit

    Theory of Device Operation signal (WUS) when a write error occurs due to head short-circuit or head disconnection. The Pre AMP sets the write current and bias current which flows through MR devices. 4.6.2 Write circuit The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent to the encoder circuit in the RDC.

  • Page 62: Figure 4.4 Read/Write Circuit Block Diagram

    4.6 Read/write Circuit Figure 4.4 Read/write circuit block diagram C141-E070-01EN 4-11...

  • Page 63: Read Circuit

    Theory of Device Operation 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This clock signal is converted into the NRZ data by the 16/17 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

  • Page 64: Digital Pll Circuit

    4.6 Read/write Circuit (3) Flash digitizer circuit This circuit is 10-tap sampled analog transversal filter circuit that cosine-equalizes the head read signal to the partial response class 4 (EPR4) waveform. (4) Viterbi detection circuit The sample hold waveform output from the flash digitizer circuit is sent to the Viterbi detection circuit.

  • Page 65: Servo Control

    Theory of Device Operation 4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.
  • Page 66 4.7 Servo Control The major internal operations are listed below. Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied. Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0).

  • Page 67: Figure 4.7 Physical Sector Servo Configuration On Disk Surface

    Theory of Device Operation Servo frame (60 servo frames revolution) Diameter CYL-n (n: even number) direction Circumference direction Erase: DC erase area Figure 4.7 Physical sector servo configuration on disk surface 4-16 C141-E070-01EN...
  • Page 68 4.7 Servo Control (2) Servo burst capture circuit The servo burst capture circuit reproduces signals (position signals) that indicate the head position from the servo data on the data surface. SERVO A, SERVO B, SERVO C and SERVO D burst signals shown in Figure 4.8 followed the servo mark, cylinder gray and index information are output from the servo area on the data surface via the data head.

  • Page 69: Data-Surface Servo Format

    Theory of Device Operation 4.7.2 Data-surface servo format Figure 4.7 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.7 are described below. (1) Inner guard band The head is in contact with the disk in this space when the spindle starts turning or stops, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.

  • Page 70: Actuator Motor Control

    4.7 Servo Control (1) Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. (2) Servo mark This area gererates a timing for demodulating the gray code and position- demodulating the servo A to D by detecting the servo mark. (3) Gray code (including index bit) This area is used as cylinder address.

  • Page 71: Spindle Motor Control

    (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.
  • Page 72 4.7 Servo Control d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection. e) The MPU is waiting for a PHASE signal.
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  • Page 74: Chapter 5 Interface

    CHAPTER 5 Interface Physical Interface Logical Interface Host Commands Command Protocol Ultra DMA Feature Set Timing This chapter gives details about the interface, and the interface commands and timings. C141-E070-01EN...

  • Page 75: Physical Interface

    Interface 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. DIOW-: I/O WRITE STOP: STOP DURING ULTRA DMA DATA BURSTS D IOR-: I/O READ H D M A R D Y : DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE: DATA STROBE DURING ULTRA DMA DATA OUT BURSTS INTRQ: INTERRUPT REQUEST...

  • Page 76: Signal Assignment On The Connector

    5.1 Physical Interface 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal Pin No. Signal MSTR MSTR/ENCSEL unused ENCSEL (KEY) (KEY) RESET– DATA7 DATA8 DATA6...
  • Page 77 Interface [signal] [I/O] [Description] ENCSEL This signal is used to set master/slave using the CSEL signal (pin 28). Pins B and D Open: Sets master/slave using the CSEL signal is disabled. Short: Sets master/slave using the CSEL signal is enabled. MSTR- MSTR, I, Master/slave setting Pin A, B, C, D open: Master setting...
  • Page 78 5.1 Physical Interface [signal] [I/O] [Description] IOCS16- This signal indicates 16-bit data bus is addressed in PIO data transfer. This signal is an open collector output. When IOCS16- is not asserted: 8 bit data is transferred through DATA0 to DATA7 signals. When IOCS16- is asserted: 16 bit data is transferred through DATA0 to DATA15 signals.

  • Page 79: Logical Interface

    Interface [signal] [I/O] [Description] DMARQ This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system (at reading) or from the host system (at writing). The direction of data transfer is controlled by the DIOR and DIOW signals.

  • Page 80: I/O Registers

    5.2 Logical Interface 5.2.1 I/O registers Communication between the host system and the device is done through input- output (I/O) registers of the device. These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to DA2 from the host system. Table 5.2. shows the coding address and the function of I/O registers.

  • Page 81: Command Block Registers

    Interface 5.2.2 Command block registers (1) Data register (X’1F0’) The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or DMA mode. (2) Error register (X’1F1’) The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.
  • Page 82 5.2 Logical Interface [Diagnostic code] X’01’: No Error Detected. X’02’: HDC Register Compare Error X’03’: Data Buffer Compare Error. X’05’: ROM Sum Check Error. X’80’: Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration.
  • Page 83 Interface (6) Cylinder Low register (X’1F4’) The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indcates LBA bits 15 to 8.
  • Page 84 5.2 Logical Interface (9) Status register (X’1F7’) The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid.
  • Page 85 Interface - Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault (write fault) condition has been detected. If a write fault is detected during command execution, this bit is latched and retained until the device accepts the next command or reset.

  • Page 86: Control Block Registers

    5.3 Host Commands 5.2.3 Control block registers (1) Alternate Status register (X’3F6’) The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.

  • Page 87: Command Code And Parameters

    Interface When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host system writes to the command register, the correct device operation is not guaranteed. 5.3.1 Command code and parameters Table 5.3 lists the supported commands, command code and the registers that needed parameters are written.
  • Page 88 5.3 Host Commands Table 5.3 Command code and parameters (2 of 2) Command code (Bit) Parameters used Command name FR SC SN CY DH IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SMART SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD...

  • Page 89: Command Descriptions

    Interface Necessary to set parameters under the LBA mode. Not necessary to set parameters (The parameter is ignored if it is set.) May set parameters The device parameter is valid, and the head parameter is ignored. The command is addressed to the master device, but both the master device and the slave device execute it.
  • Page 90 5.3 Host Commands CM: Command register FR: Features register DH: Device/Head register ST: Status register CH: Cylinder High register ER: Error register CL: Cylinder Low register L: LBA (logical block address) setting bit SN: Sector Number register DV: Device address. bit SC: Sector Count register x, xx: Do not care (no necessary to set) Note:...
  • Page 91 Interface Command block registers contain the cylinder, the head, and the sector addresses of the sector (in the CHS mode) or the logical block address (in the LBA mode) where the error occurred, and remaining number of sectors of which data was not transferred.
  • Page 92 5.3 Host Commands The implementation of the READ MULTIPLE command is identical to that of the READ SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE MODE command are transferred without intervening interrupts. In the READ MULTIPLE command operation, the DRQ bit of the Status register is set only at the start of the data block, and is not set on each sector.

  • Page 93: Figure 5.2 Execution Example Of Read Multiple Command

    Interface Figure 5.2 Execution example of READ MULTIPLE command At command issuance (I/O registers setting contents) (CM) (DH) Start head No. /LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR)
  • Page 94 5.3 Host Commands (3) READ DMA (X’C8’ or X’C9’) This command operates similarly to the READ SECTOR(S) command except for following events. The data transfer starts at the timing of DMARQ signal assertion. The device controls the assertion or negation timing of the DMARQ signal. The device posts a status as the result of command execution only once at completion of the data transfer.
  • Page 95 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. /LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
  • Page 96 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Start head No. /LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) R = 0 with Retry...
  • Page 97 Interface The data stored in the buffer, and CRC code and ECC bytes are written to the data field of the corresponding sector(s). Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector addresses of the last sector written.
  • Page 98 5.3 Host Commands (6) WRITE MULTIPLE (X’C5’) This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command.
  • Page 99 Interface At command issuance (I/O registers setting contents) (CM) (DH) Start head No. /LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read) (ST)
  • Page 100 5.3 Host Commands A host system can select the following transfer mode using the SET FEATURES command. 1) Single word DMA transfer mode 0 to 2 2) Multiword DMA transfer mode 0 to 2 3) Ultra DMA transfer mode 0 to 2 At command issuance (I/O registers setting contents) (CM) (DH)
  • Page 101 Interface After all sectors are verified, the last interruption (INTRQ for command termination) is generated. At command issuance (I/O registers setting contents) (CM) (DH) Start head No. /LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No.
  • Page 102 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Note: Also executable in LBA mode. (10) SEEK (X’7x’, x : X’0’...

  • Page 103: 1F7 (Cm)

    Interface At command issuance (I/O registers setting contents) (CM) (DH) Head No. /LBA [MSB] (CH) Cylinder No. [MSB] / LBA (CL) Cylinder No. [LSB] / LBA (SN) Sector No. / LBA [LSB] (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH)

  • Page 104: 1F6 (Dh) Dv

    5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Max. head No. (CH) (CL) (SN) (SC) Number of sectors/track (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) Max. head No. (CH) (CL) (SN) (SC)
  • Page 105 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 6) Word Value Description...
  • Page 106 5.3 Host Commands Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 6) Word Value Description 23-26 – Firmware revision (ASCII code, 8 characters, left) 27-46 Set by a device Model name (ASCII code, 40 characters, left) X’8010’...
  • Page 107 Interface Table 5.4 Information to be read by IDENTIFY DEVICE command (3 of 6) Word Value Description X’4008’ Support of command sets *11 X’4000’ Support of command sets/function Valid of command sets/function *12 Valid of command sets/function *13 X’4000’ Default of command sets/function X’xx07’...
  • Page 108 5.3 Host Commands Table 5.4 Information to be read by IDENTIFY DEVICE command (4 of 6) Bit 9, 8: Always 1 *4 Word 51: PIO data transfer mode Bit 15-8: PIO data transfer mode X’02’=PIO mode 2 Bit 7-0: Undefined *5 Word 53: Enable/disable setting of word 54-58 and 64-70 Bit 15-3: Reserved...
  • Page 109 Interface Table 5.4 Information to be read by IDENTIFY DEVICE command (5 of 6) Bit 2: ATA-2 supported = 1 Bit 1: ATA-1 supported = 1 Bit 0: Undefined *10 WORD 82 Bit 15: Undefined Bit 14: '1' = Supports the NOP command. Bit 13: '1' = Supports the READ BUFFER command.
  • Page 110 5.3 Host Commands Table 5.4 Information to be read by IDENTIFY DEVICE command (6 of 6) *12 WORD 85 Bits 15-9 : Same definition as WORD 82. Bit 8 : '1' = Enables the SERVICE interrupt. Bit 7: '1' = Enables the release interrupt. Bit 6: '1' = Enables the read cache function.
  • Page 111 Interface (13) IDENTIFY DEVICE DMA (X’EE’) When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command. At command issuance (I/O registers setting contents) (CM) (DH) (CH)
  • Page 112 5.3 Host Commands Table 5.5 Features register values and settable modes Features Register Drive operation mode X’02’ Enables the write cache function. X’03’ Transfer mode depends on the contents of the Sector Count register. (Details are given later.) X’05’ Enables the advanced power management function. X’55’...

  • Page 113: (Sc)

    Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) xx or transfer mode (FR) [See Table 5.5] At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information The host sets X’03’...
  • Page 114 5.3 Host Commands Single word DMA transfer mode X 00010 000 (X’10’: Mode 0) 00010 001 (X’11’: Mode 1) 00010 010 (X’12’: Mode 2) Multiword DMA transfer mode X 00100 000 (X’20’: Mode 0) 00100 001 (X’21’: Mode 1) 00100 010 (X’22’: Mode 2) Ultra DMA transfer mode X 01000 000 (X’40’: Mode 0) 01000 001 (X’41’: Mode 1)
  • Page 115 Interface When the SET MULTIPLE MODE command operation is completed, the device clears the BSY bit and generates an interrupt. At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) Sector count/block (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH)
  • Page 116 5.3 Host Commands Word 47 Bit 7-0 = 10: Maximum number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE MULTIPLE commands are 16 (fixed). Word 59 = 0000: The READ MULTIPLE and WRITE MULTIPLE commands are disabled.

  • Page 117: 1F1 (Fr)

    Interface At command issuance (I/O registers setting contents) (CM) (DH) Max head/LBA [MSB] (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) Max head/LBA [MSB]...
  • Page 118 5.3 Host Commands At command completion (I/O registers contents to be read) (ST) Status information (DH) Max head/LBA [MSB] (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (ER) Error information (18) EXECUTE DEVICE DIAGNOSTIC (X’90’) This command performs an internal diagnostic test (self-diagnosis) of the device.
  • Page 119 Interface Table 5.6 Diagnostic code Code Result of diagnostic X’01’ No error detected. X’03’ Data buffer compare error X’05’ ROM sum check error X’8x’ Failure of device 1 attention: The device responds normally to this command without excuting internal diagnostic test. At command issuance (I/O registers setting contents) (CM) (DH)
  • Page 120 5.3 Host Commands (19) READ LONG (X’22’ or X’23’) This command operates similarly to the READ SECTOR(S) command except that the device transfers the data in the requested sector and the ECC bytes to the host system. The ECC error correction is not performed for this command. This command is used for checking ECC function by combining with the WRITE LONG command.
  • Page 121 Interface (20) WRITE LONG (X’32’ or X’33’) This command operates similarly to the READ SECTOR(S) command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium. The device does not generate ECC bytes by itself. The WRITE LONG command supports only single sector operation.
  • Page 122 5.3 Host Commands (21) READ BUFFER (X’E4’) The host system can read the current contents of the sector buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up the sector buffer for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt.
  • Page 123 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (23) IDLE (X’97’ or X’E3’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode.
  • Page 124 5.3 Host Commands Sector Count register value Point of timer [X’00’] 30 minutes 1 to 3 [X’01’ to X’03’] 15 seconds 4 to 240 [X’04’ to X’F0’] (Value 5) seconds 241 to 251 [X’F1’ to X’FB’] 30 minutes [X’FC’] 21 minutes [X’FD’] 30 minutes 254 to 255 [X’FE’...
  • Page 125 Interface (24) IDLE IMMEDIATE (X’95’ or X’E1’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the automatic power-down function. At command issuance (I/O registers setting contents) (CM) X’95’...
  • Page 126 5.3 Host Commands Under the standby mode, the spindle motor is stopped. Thus, when the command involving a seek such as the READ SECTOR(s) command is received, the device processes the command after driving the spindle motor. attention: The automatic power-down is excuted if no command is coming for 30 min.
  • Page 127 Interface At command issuance (I/O registers setting contents) (CM) X’94’ or X’E0’ (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (27) SLEEP (X’99’ or X’E6’) This command is the only way to make the device enter the sleep mode.
  • Page 128 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) X’99’ or X’E6’ (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (28) CHECK POWER MODE (X’98’...
  • Page 129 Interface At command issuance (I/O registers setting contents) (CM) X’98’ or X’E5’ (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) X’00’ ,X’80’ or X’FF’ (ER) Error information (29) SMART (X’B0) This command performs operations for device failure predictions according to a...
  • Page 130 5.3 Host Commands Table 5.7 Features Register values (subcommands) and functions (1 of 2) Features Resister Function X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host.
  • Page 131 Interface Table 5.7 Features Register values (subcommands) and functions (2 of 2) Features Resister Function X’DA’ SMART Return Status: When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values.
  • Page 132 5.3 Host Commands At command completion (I-O registers setting contents) (ST) Status information (DH) (CH) Key-failure prediction status (C2h-2Ch) (CL) Key-failure prediction status (4Fh-F4h) (SN) (SC) (ER) Error information The attribute value information is 512-byte data; the format of this data is shown below.
  • Page 133 Interface Table 5.9 Format of insurance failure threshold value data Byte Item Data format version number Attribute 1 Attribute ID Insurance failure threshold 04 to 0D Threshold 1 Reserved (Threshold of attribute 1) 0E to 169 Threshold 2 to (The format of each threshold value is the same as threshold 30 that of bytes 02 to 0D.) 16A to 17B Reserved...
  • Page 134 5.3 Host Commands Attribute ID Attribute name Number of power-on-power-off times 13 to 198 (Reserved) Ultra ATA CRC error rate Write error rate 201 to 255 (Unique to vendor) Status Flag Meaning If this bit 1, it indicates that if the attribute exceeds the threshold, it is the attribute covered by the drive warranty.
  • Page 135 Interface Bit 7: If this bit is 1, it indicates that the automatic off-line data collection function is enabled. Status Byte Meaning Off-line data collection is not started. Off-line data collection has been completed normally. Off-line data collection is in progress. Off-line data collection has been suspended by a command interrupt.
  • Page 136 5.3 Host Commands Check sum Two’s complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning. Insurance failure threshold The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure.
  • Page 137 Interface Table 5.10 Contents of security password Word Contents Control word Bit 0: Identifier 0 = Compares the user passwords. 1 = Compares the master passwords. Bits 1 to 15: Reserved 1 to 16 Password (32 bytes) 17 to 255 Reserved At command issuance (I-O register contents)) (CM)
  • Page 138 5.3 Host Commands At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (32) SECURITY ERASE UNIT (F4h) This command erases all user data. This command also invalidates the user password and releases the lock function.
  • Page 139 Interface At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (33) SECURITY FREEZE LOCK (F5h) This command puts the device into FROZEN MODE. The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE.
  • Page 140 5.3 Host Commands READ DMA WRITE DMA SECURITY DISABLE PASSWORD READ LONG WRITE LONG SECURITY FREEZE LOCK READ MULTIPLE WRITE MULTIPLE SECURITY SET PASSWORD READ SECTORS WRITE SECTORS WRITE VERIFY At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR)
  • Page 141 Interface (34) SECURITY SET PASSWORD (F1h) This command enables a user password or master password to be set. The host transfers the 512-byte data shown in Table 1.2 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data.
  • Page 142 5.3 Host Commands Table 5.12 Relationship between combination of Identifier and Security level, and operation of the lock function Indentifier Level Description User High The specified password is saved as a new user password. The lock function is enabled after the device is turned off and then on.
  • Page 143 Interface Issuing this command in FROZEN MODE returns the Aborted Command error. At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (36) FLUSH CACHE (E7) This command is used to order to write every write cache data stored by the...

  • Page 144: Error Posting

    5.3 Host Commands At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information 5.3.3 Error posting Table 5.7 lists the defined errors that are valid for each command. Table 5.13 Command code and parameters (1 of 2) Command name Error register (X’1F1’)
  • Page 145 Interface Table 5.13 Command code and parameters (2 of 2) Command name Error register (X’1F1’) Status register (X’1F7’) INDF ABRT TK0NF DRDY RECALIBRATE SEEK INITIALIZE DEVICE PARAMETERS IDENTIFY DEVICE IDENTIFY DEVICE DMA SET FEATURES SET MULTIPLE MODE SET MAX ADDRESS READ NATIVE MAX ADDRESS EXECUTE DEVICE DIAGNOSTIC READ LONG...

  • Page 146: Command Protocol

    5.4 Command Protocol 5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0.

  • Page 147: Figure 5.3 Read Sector(S) Command Protocol

    Interface words, the host should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the DRQ status by resetting. Figure 5.3 shows an example of READ SECTOR(S) command protocol, and Figure 5.4 shows an example protocol for command abort. Figure 5.3 Read Sector(s) command protocol Note: For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to...

  • Page 148: Data Transferring Commands From Host To Device

    5.4 Command Protocol sector in multiple-sector reading. If the timing to read the Status register does not meet above condition, normal data transfer operation is not guaranteed. When the host new command even if the device requests the data transfer (setting in DRQ bit), the correct device operation is not guaranteed.
  • Page 149 Interface b) The host writes a command code in the Command register. The drive sets the BSY bit of the Status register. c) When the device is ready to receive the data of the first sector, the device sets DRQ bit and clears BSY bit. d) The host writes one sector of data through the Data register.

  • Page 150: Commands Without Data Transfer

    5.4 Command Protocol Note: For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 50 s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred.

  • Page 151: Other Commands

    Interface Figure 5.6 Protocol for the command execution without data transfer 5.4.4 Other commands READ MULTIPLE SLEEP WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands READ DMA WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issurance.
  • Page 152 5.4 Command Protocol When the command execution is completed, the device clears both BSY and DRQ bits and asserts the INTRQ signal. Then, the host reads the Status register. g) The host resets the DMA channel. Figure 5.7 shows the correct DMA data transfer protocol. Figure 5.7 Normal DMA data transfer C141-E070-01EN 5-79...

  • Page 153: Ultra Dma Feature Set

    Interface 5.5 Ultra DMA Feature Set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only.
  • Page 154 5.5 Ultra DMA Feature Set Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends the its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command.
  • Page 155 Interface g) Ultra DMA data in burst The device should not invert the state of this signal in the period from the moment of STOP signal negation or HDMARDY-signal assertion to the moment of inversion of the first STROBE signal. 5.5.2.2 Data transfer phase a) The Data transfer phase is defined as the period from The Ultra DMA burst initiation phase to Ultra DMA burst termination phase.
  • Page 156 5.5 Ultra DMA Feature Set Once the transmitting side has outputted the ending request, the output state of STROBE signal should not be changed unless the receiving side has confirmed it. Then, if the STROBE signal is not in asserted state, The transmitting side should assert the STROBE signal.
  • Page 157 Interface 9) The host shall negate STOP and assert HDMARDY- within t after asserting DMACK-. After negating STOP and asserting HDMARDY-, the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device (i.e., after the first data word has been received).
  • Page 158 5.5 Ultra DMA Feature Set 3) The device shall resume an Ultra DMA burst by generating a DSTROBE edge. b) Host pausing an Ultra DMA data in burst 1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.
  • Page 159 Interface 7) If DSTROBE is negated, the device shall assert DSTROBE within t after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra DMA burst is terminated.
  • Page 160 5.5 Ultra DMA Feature Set 5) The host shall assert STOP no sooner than t after negating HDMARDY-. The host shall not negate STOP again until after the Ultra DMA burst is terminated. 6) The device shall negate DMARQ within t after the host has asserted STOP.
  • Page 161 Interface 5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.7 and 5.6.4.2 for specific timing requirements): 1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.
  • Page 162 5.5 Ultra DMA Feature Set HSTROBE edge no more frequently than t for the selected Ultra DMA Mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2 t for the selected Ultra DMA mode. 3) The host shall not change the state of DD (15:0) until at least t after generating an HSTROBE edge to latch the data.
  • Page 163 Interface 5.5.4.4 Terminating an Ultra DMA data out burst a) Host terminating an Ultra DMA data out burst The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.10 and 5.6.4.2 for specific timing requirements): 1) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.
  • Page 164 5.5 Ultra DMA Feature Set b) Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.11 and 5.6.4.2 for specific timing requirements): 1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.
  • Page 165 Interface 13) The host shall neither negate STOP nor HSTROBE until at least t after negating DMACK-. 14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t after negating DMACK. 5.5.5 Ultra DMA CRC rules The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.
  • Page 166 5.5 Ultra DMA Feature Set Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynominal where DD0 is shifted in first and DD15 is shifted in last.
  • Page 167 Interface 5.5.6 Series termination required for Ultra DMA Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA Modes. The following table describes recommended values for series termination at the host and the device. Table 5.15 Recommended series termination for Ultra DMA Signal Host Termination...
  • Page 168 5.6 Timing 5.6 Timing 5.6.1 PIO data transfer Figure 5.10 shows of the data transfer timing between the device and the host system. C141-E070-01EN 5-95...
  • Page 169 Interface Figure 5.10 Data transfer timing 5-96 C141-E070-01EN...
  • Page 170 5.6 Timing 5.6.2 Single word DMA data transfer Figure 5.11 show the single word DMA data transfer timing between the device and the host system. Figure 5.11 Single word DMA data transfer timing (mode 2) C141-E070-01EN 5-97...
  • Page 171 Interface 5.6.3 Multiword DMA data transfer Figure 5.12 shows the multiword DMA data transfer timing between the device and the host system. Delay time from DIOR-/DIOW- assertion to DMARQ negation Figure 5.12 Multiword DMA data transfer timing (mode 2) 5-98 C141-E070-01EN...
  • Page 172 5.6 Timing 5.6.4 Transfer of Ultra DMA data Figures 5.13 to 5.22 define the timings concerning every phase for the Ultra DMA Burst. Table 5.16 includes the timing for each Ultra DMA mode. 5.6.4.1 Starting of Ultra DMA data In Burst The timing for each Ultra DMA mode is included in 5.6.4.2.
  • Page 173 Interface 5.6.4.2 Ultra DMA data burst timing requirements Table 5.16 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 MODE 2 COMMENT (in ns) (in ns) (in ns) Cycle time (from STROBE edge to STROBE edge) Two cycle time (from rising edge to next rising edge or from falling edge to next falling edge of STROBE)
  • Page 174 5.6 Timing Table 5.16 Ultra DMA data burst timing requirements (2 of 2) NAME MODE 0 MODE 1 MODE 2 COMMENT (in ns) (in ns) (in ns) Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of DMARDY) Ready-to-pause time (that recipient shall wait to initiate pause after negating DMARDY-)
  • Page 175 Interface 5.6.4.3 Sustained Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.
  • Page 176 5.6 Timing 5.6.4.4 Host pausing an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t after HDMARDY- is negated.
  • Page 177 Interface 5.6.4.5 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
  • Page 178 5.6 Timing 5.6.4.6 Host terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
  • Page 179 Interface 5.6.4.7 Initiating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 5.18 Initiating an Ultra DMA data out burst 5-106 C141-E070-01EN...
  • Page 180 5.6 Timing 5.6.4.8 Sustained Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.
  • Page 181 Interface 5.6.4.9 Device pausing an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t after DDMARDY- is negated.
  • Page 182 5.6 Timing 5.6.4.10 Host terminating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
  • Page 183 Interface 5.6.4.11 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
  • Page 184 5.6 Timing 5.6.5 Power-on and reset Figure 5.11 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Power-on Reset RESET – (2) Master and slave devices are present (2-drives configulation) PDIAG- negation Figure 5.23 Power on Reset Timing C141-E070-01EN 5-111...
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  • Page 186: Chapter 6 Operations

    CHAPTER 6 Operations Device Response to the Reset Address Translation Power Save Defect Management Read-Ahead Cache Write Cache C141-E070-01EN...

  • Page 187: Device Response To The Reset

    Operations 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1).
  • Page 188 6.1 Device Response to the Reset 31 sec. 30 sec. Figure 6.1 Response to power-on C141-E070-01EN...

  • Page 189: Response To Hardware Reset

    Operations 6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confirms assertion of the DASP- signal.

  • Page 190: Response To Software Reset

    6.1 Device Response to the Reset 6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 15 seconds to see if the slave device has completed the self-diagnosis successfully.

  • Page 191: Response To Diagnostic Command

    Operations 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self- diagnosis successfully.

  • Page 192: Address Translation

    6.2 Address Translation 6.2 Address Translation When the IDD receives any command which involves access to the disk medium, the IDD always implements the address translation from the logical address (a host-specified address) to the physical address (logical to physical address translation).

  • Page 193: Logical Address

    Operations 6.2.2 Logical address (1) CHS mode Logical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, and physical sector (PS) 1 and is assigned by calculating the number of sectors per track that is specified by the INITIALIZE DEVICE PARAMETERS command.

  • Page 194: Power Save

    6.3 Power Save (2) LBA mode Logical address assignment in the LBA mode starts from physical cylinder 0, physical head 0, and physical sector 1. If the last sector in a zone of a physical head is used, the track is switched and the next LBA is assigned to the initial sector in the same zone of the subsequent physical head.
  • Page 195 Operations Standby mode Sleep mode The drive moves from the Active mode to the idle mode by itself. Regardless of whether the power down is enabled, the device enters the idle mode. The device also enters the idle mode in the same way after power-on sequence is completed.

  • Page 196: Defect Management

    6.4 Defect Management When one of following commands is issued, the command is executed normally and the device is still stayed in the standby mode. Reset (hardware or software) STANDBY command STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMETERS command CHECK POWER MODE command (4) Sleep mode The power consumption of the drive is minimal in this mode.

  • Page 197: Spare Area

    Operations 6.4.1 Spare area Following two types of spare area are provided for every physical head. 1) Spare cylinder for sector slip: used for alternating defective sectors at formatting in shipment (4 cylinders) 2) Spare cylinder for alternative assignment: used for automatic alternative assignment at read error occurrence. (4 cylinders) 6.4.2 Alternating defective sectors The two alternating methods described below are available:...
  • Page 198 6.4 Defect Management (2) Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when the alternate assignment is specified in the FORMAT TRACK command or when the automatic alternate processing is performed at read error occurrence.

  • Page 199: Read-Ahead Cache

    Operations 6.5 Read-Ahead Cache After read command which involes read data from the disk medium is completed, the read-ahead cache function reads the subsequent data blocks automatically and stores the data to the data buffer. When the next command requests to read the read-ahead data, the data can be transferred from the data buffer without accessing the disk medium.
  • Page 200 6.5 Read-Ahead Cache READ SECTOR (S) READ MULTIPLE READ DMA When caching operation is disabled by the SET FEATURES command, no caching operation is performed. (2) Data that are object of caching operation Follow data are object of caching operation. 1) Read-ahead data read from the medium to the data buffer after completion of the command that are object of caching operation.

  • Page 201: Usage Of Read Segment

    Operations READ MULTIPLE WRITE SECTOR(S) WRITE MULTIPLE WRITE VERIFY SECTOR(S) 3) Caching operation is inhibited by the SET FEATURES command. 4) Issued command is terminated with an error. 5) Soft reset or hard reset occurs, or power is turned off. 6) The device enters the sleep mode.
  • Page 202 6.5 Read-Ahead Cache 2) Transfers the requested data that already read to the host system with reading the requested data from the disk media. Stores the read-requested data upto this point Empty area Read-requested data 3) After reading the requested data and transferring the requested data to the host system had been completed, the disk drive stops command execution without performing the read-ahead operation.
  • Page 203 Operations 1) At receiving the sequential read command, the disk drive sets the DAP and HAP to the start address of the segment and reads the requested data from the load of the segment. Mis-hit data Empty area 2) The disk drive transfers the requested data that is already read to the host system with reading the requested data.
  • Page 204 6.5 Read-Ahead Cache b. Sequential hit When the previously executed read command is the sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive transfers the hit data in the buffer to the host system.
  • Page 205 Operations 4) Finally, the cache data in the buffer is as follows. Read-ahead data Start LBA Last LBA Non-sequential command immediately after sequential command When a sequential read command (first read) has been executed, the first read operation should be stopped if a non-sequential read command has been received and then, ten or more of the non-sequential read commands have been received.
  • Page 206 6.5 Read-Ahead Cache 3) The cache data for next read command is as follows. Cache data Start LBA Last LBA 6.5.3.4 Partially hit A part of requested data including a lead sector are stored in the data buffer. The disk drive starts the data transfer from the address of the hit data corresponding to the lead sector of the requested data, and reads remaining requested data from the disk media directly.

  • Page 207: Write Cache

    Operations 3) The cache data for next read command is as follows. Cache data Start LBA Last LBA 6.6 Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is physically sequent the data of previous command and random write operation is performed.
  • Page 208 6.6 Write Cache The drive uses a cache data of the last write command as a read cache data. When a read command is issued to the same address after the write command (cache hit), the read operation to the disk medium is not performed. If an error occurs during the write operation, the device retries the processing.
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  • Page 210 Glossary Actuator Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head. AT bus A bus between the host CPU and adapter board ATA (AT Attachment) standard The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors.
  • Page 211 Glossary MTBF Mean time between failures. The MTBF is calculated by dividing the total operation time (total power-on time) by the number of failures in the disk drive during operation. MTTR Mean time to repair. The MTTR is the average time required for a service person to diagnose and repair a faulty drive.
  • Page 212 Glossary Status The status is a piece of one-byte information posted from the drive to the host when command execution is ended. The status indicates the command termination state. Voice coil motor. The voice coil motor is excited by one or more magnets. In this drive, the VCM is used to position the heads accurately and quickly.
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  • Page 214: Acronyms And Abbreviations

    Acronyms and Abbreviations Hard disk drive ABRT Abored command Automatic idle control IDNF ID not found AMNF Address mark not found IRQ14 Interrupt request 14 AT attachment American wire gage Light emitting diode Bad block detected BIOS Basic input-output system Mega-byte MB/S Mega-byte per seconds...
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  • Page 216 Index 1-drive connection 2-4 CHS mode 6-8 2-drive connection 2-5 Circuit configuration 4-4, 4-5 8/8 GCR 4-10 Circulation filter 2-4, 4-3 8/9 GCR decoder 4-13 Combination of Identifier and Security level 5-69 Command block register 5-8 Command code 5-14, 5-71 Acceleration mode 4-21 Command description 5-16 Acoustic noise 1-7...
  • Page 217 Index Data that is object of caching operation Format of insurance failure threshold value 6-15 data 5-60 Data transfer rate 4-13 Frame 3-4 Data transferring command 5-73, 5-75 Frequency characteristics of programmable Data transfer timing 5-81 filter 4-12 DE 2-4 Full hit 6-20 Default parameter 6-7 Functions and performance 1-2...
  • Page 218 Index Power on timing 5-80 Power on timing 5-84 Master 1-3 Power requirement 1-5 Master drive setting 3-10 Power save 6-9 Master password 5-68 Power save mode 1-2, 6-9 Mean time between failures 1-8 Power supply connector 3-11 Mean time to repair 1-8 PreAMP 4-9 Media defect 1-9 Programmable filter 4-12...
  • Page 219 Index SEEK 5-29 STANDBY IMMEDIATE 5-53 Seek operation 4-20 Standby mode 6-10 Seek to specified cylinder 4-15 Start, spindle motor 4-15 Self-calibration 4-7 Start mode 4-20 Self-calibration content 4-7 Status at completion of command execution Self-diagnosis 1-3 Sensing and compensating for external force Status flag 5-62 Status register 5-11 Sequential command 6-17...
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  • Page 221 List any errors or suggestions for improvement. Page Line Contents Please send this form to the address below. We will use your comments in planning future editions. Address: Fujitsu Learning Media Limited 22-7 Minami-Ooi 6-Chome Shinagawa-Ku Tokyo 140-0013 JAPAN Fax: 81-3-5762-8073...
  • Page 222 MHG2102AT, MHH2064AT, MHH2048AT, MHH2032AT DISK DRIVES C141-E070-02EN PRODUCT MANUAL MHG2102AT, MHH2064AT, MHH2048AT, MHH2032AT DISK DRIVES C141-E070-02EN PRODUCT MANUAL...

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