Logic Analyzer Connector J15 Pin Assignments - Motorola M68MPB916R1 User Manual

Table 4-8. Logic Analyzer Connector J14 Pin Assignments (continued)
Pin
9 – 15
16 – 19
20
Table 4-9. Logic Analyzer Connector J15 Pin Assignments
Pin
1 – 3
4 – 8
9, 10
11, 12
13, 14
15, 16
17
18, 19
20
M68MPB16R1UM/D
Freescale Semiconductor, Inc.
Mnemonic
IRQ1 – IRQ7 TARGET INTERRUPT REQUEST 1 - 7 – Active-low
input signals from the target that asynchronously
provides an interrupt priority level to the CPU. IRQ1
has the lowest priority, IRQ7 has the highest.
PF1 – PF7 PORT F (bits 1 - 7) – General purpose Iinput/output
lines.
SPARE No connection
GND GROUND
Mnemonic
SPARE No connection
GND GROUND
CPWM19, CONFIGURABLE PULSE WIDTH MODULATION
CPWM18 SUBMODULE 19 and 18 – creates a variable pulse
width output signal at a wide range of frequencies.
CTS16A,
CONFIGURABLE TIMER SINGLE-ACTION
CTS16B
CHANNEL 16 A and B – I/O signals that function as
single-action capture/compare channels for the CTM.
CTS14A, CONFIGURABLE TIMER SINGLE-ACTION
CTS14B CHANNEL 14 A and B – I/O signals that function as
single-action capture/compare channels for the CTM.
CTS12A, CONFIGURABLE TIMER SINGLE-ACTION
CTS12B CHANNEL 12 A and B – I/O signals that function as
single-action capture/compare channels for the CTM.
CTS10B CONFIGURABLE TIMER SINGLE-ACTION
CHANNEL 10 B – I/O signals that function as single-
action capture/compare channels for the CTM.
SPARE No connection
GND GROUND
For More Information On This Product,
Go to: www.freescale.com
MEVB SUPPORT INFORMATION
Signal
Signal
4-9 9