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The Search Address
Mark
signal drops at the
end of the gap.
This applies a constant
enable to the high resolution channel and
all zero-cross pulses get through to the FF.
This terminates the Amplitude Enable func-
tion and removes the Level Detector as a
possible source of error during the actual
reading of data.
Phase Lock Oscillator Circuit
The phase lock oscillator (PLO) circuit
(Figure 3-51) provides a clock signal to the
data separator so that it may determine if
the data pulses from the data latch are
MFM
Clock or
MFM
Data.
To do this, the PLO must
synchronize its frequency to the frequency
of the data coming from the disk.
PLO frequency is controlled by the Comparator
FF.
Basically, the
FF
is set by data
and
cleared by the oscillator pulses.
Therefore,
if the oscillator is too slow, the FF will
be set more than it is cleared because data
frequency exceeds oscillator frequency.
Fre-
quency synchronization is attained when data
and oscillator frequencies are identical.
The FF is then set 50% of the time.
The
nominal data frequency is 6.44 MHz with the
oscillator running at twice the data fre-
quency (12.88 MHz).
The FF is set by one of three signals:
1.
OS, which is Early Data.
2.
X,
which is delayed OS.
3. Y Enable, which is used when data will
not be available in time to set the
Comparator FF.
The
osc~llator
output is divided into four
1/4-cell phases: Pl, P2, P3, and P4.
The X
or Os pulses can set the FF only if they
occur in the Pl, P2, or P3 periods.
Except
in cases of abnormal peak shift, the Compara-
tor
FF
is set during Pl or P2.
The
FF
is
unconditionally cleared at P4 time.
In a pattern of all "l's·, OS sets the FF.
An
all nO's· pattern causes it to be set by
X
pulses.
Synchronization shifts between
OS and
X
pulses depending upon the data pat-
tern being read.
During a data pattern in
which OS or
X
will not occur during Pl or P2
time (for example, in a "10" pattern) Y
Enable acts as a fake data pulse to set the
FF
to maintain reasonable,frequency control.
The Comparator FF output is integrated and
used as a control voltage to the voltage-
controlled oscillator in the PLO.
With the
FF set, the oscillator tends to speed up;
with the FF cleared, it slows down.
The
multivibrator output is, therefore, not
completely symmetrical.
A
~ivide-by-two
83318200
A
flip-flop (9/2) provides the required sym-
metrical output by triggering off of the neg-
ative-going edge of the PLO output.
Note that the PLO functions as long as the
data latch is operational.
Only
the
Read
Enable signal need be up.
Fast Start
Fast start increases loop gain to assist in
rapid frequency synchronization.
This func-
tion is enabled by a Read command.
Note that
Read Header does not directly provide Fast
Start.
With delay Y806 timing out for 5
microseconds, the following events occur:
1. Greater current is provided to a circuit
internal to the control voltage genera-
tor.
The control voltage to the multi-
vibrator, which is normally 0.65v peak-
to-peak, is doubled.
2. DS and Y Enable pulses are inhibited.
Only
X
pulses are presented to the Com-
parator FF.
This ensures correct phase
synchronization.
Fast Start must be
enabled only during a sync pattern of
zeros.
3. P4 pulses are narrowed to about 1/8-cell
time to permit incoming data ta dominate
the Comparator FF.
4. Fast Start is applied to SERDES control
to control Data Good.
Delay Y808 is used for address mark
~tkms.
With Read Enable up, this single-shot re-
mains in the continuously-triggered condition.
A
Read command cannot generate a Resync Pulse
to initiate Fast Start.
As explained in the
SERDES discussion, data cannot be recognized
until the trailing edge of Fast Start.
How-
'ever, no flux transitions occur during the
address mark gap: therefore, there are no
X
or OS pulses.
Y808 times out if about two
bytes (each byte equals about 1.24 micro-
seconds) occur without
X
or OS pulses.
The
first ·0" of the first zeros byte retriggers
Y80S; Y806 fires to initiate Fast Start.
Data Separator Circuit
The Data Separator circuit {Figure 3-52}
separates the data "l's" from the clock. The
circuit-consists of the Data Window FF, Data
Sense FF, Data and Clock register FFs, the
Data Strobe circuit, and various delays and
gates.
The data windOW, Shift pulses, and Reset
pulses are derived from the 9/2 output of
the Phase Lock Oscillator circuit.
The data
window width is adjustable for maximum data
discrimination by means of a tapped delay
3-97
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