Toshiba TC9349AFG Manual page 62

I/O port 3 is a CMOS I/O port. Pins P3-0 to P3-2 are also used as the serial interface and pin P3-3 is also used as a pulse
counter input pin. These pins can be set to pull-up or pull-down state and to the break function.
(→ Refer to the sections on Serial interface and Pulse counter.)
I/O ports 4 and 5 are CMOS I/O ports. Pins P4-0 and P4-1 are also used as external interrupt input pins. Pin P4-1 is also
used as the PLL inhibit input pin. Pin P4-2 is also used as the buzzer output pin. Pins P4-3 and P5-0 to P5-3 are also used as
the electronic volume pins. Pins P4-0 to P4-3 can be set to the break function.
(→ Refer to the sections on External interrupt, Back-up, Buzzer output and Volume.)
I/O port 6 is a N-ch open-drain I/O port. Voltage can be applied up to the V
6-bit A/D converter analog input, and can be set to the break function.
(→ Refer to the sections on A/D converter.)
I/O port 8 is an N-ch open-drain I/O port. Voltage can be applied up to 5.5 V. Pin P8-0 is also used as the doubler voltage
detection input pin for the DC-DC converter of VT. Pin P8-1 is also used as the clock output pin for the DC-DC converter
of VT. Pins P8-1 to P8-3 are also used as the serial interface. These pins can be set to the break function.
(→ Refer to the sections on the DC-DC converter of VT and Serial interface.)
I/O port 9 consists of the N-ch open-drain pin (P9-0) and the CMOS pins (P9-1 and P9-2). P9-0 is also used as the Tr
output pin for LPF. Pin P9-1 is also used as the MUTE output pin. P9-2 is also used as the clock output pin for the DC-DC
converter. In addition, pin P9-2 is pulled down to serve as the test mode input pin when pin RESET is at the "L" level.
This pin must be in the open state or at the "L" level during test mode input.
(→ Refer to the sections on MUTE output, DC-DC converter of VT and Phase comparator.)
I/O ports 10 to 16 are CMOS I/O ports, and also serve as the LCD driver output pins. Pins P16-2 and P16-3 are also used
as high-speed oscillators. (→ Refer to the sections on the LCD driver and System clock control circuit.)
The exclusive input port is the IN input pin of IFin input combination. The IN input can be switched by the program.
The two phase comparator output pins can be used as the exclusive output ports (OT1/OT2). These pins output any of
three values; an "H" level that is the V
The I/O circuit of 41 pins at I/O ports 3, 4, 5, 8, 9 and 10 to 16 uses the V
applied up to 3 V, and a stable output current can be obtained because the output is not heavily reliant on the V
power supply. Pin IN2 of I/O port 6 can accept voltage up to the V
V pin level
PLL
Note: When setting individual pins as input/output ports, refer to the corresponding sections on the
Dual-purpose Function.
Note: The "H" level of OT1/OT2 output is the V
Note: The IN input at the input-only port uses the V
× 0.2 or lower. When the VPLL power supply is turned off with the tuner off, IN input
the "L" level is V
PLL
becomes unfixed. The input level for the other pins is V
or lower at the "L" level.
Note: After a system reset, pin MUTE/P9-1 is set to the MUTE output and all the other input and output pins
are set to the I/O port input or high impedance. The MUTE output becomes the "L" level during system
reset, and becomes the "H" level after release.
Note: When the clock stop instruction is executed, the "L" level is outputted at all the pins that have been set to
the I/O port ouput. After the clock stop is released, the previous state is outputted.
pin level, "L" level and High impedance.
DB
DB
level. All the other CMOS I/O ports output the V
DB
power supply. The "H" level is V
PLL
DD
62
TC9349AFG
pin level. This port is also used for the
DB
(3 V) power supply pin. Voltage can be
LCD
pin level and pin IN can accept voltage up to the
× 0.8 or higher and
PLL
× 0.8 or higher at the "H" level and V
pin
DD
level.
DD
× 0.2
DD
2006-02-24