Board - Motorola R-20010 Maintenance Manual

loop and attenuates the reference-frequency compo-
nent coming from the phase detector. The 3-dB band-
width of the 34.3-MHz PLL is 5 Hz. The loop filter
incorporates a lead-lag network (R8, R73, and C85) to
reduce the resistor values of Rl-R4. This allows for a
faster loop-lock time. Diodes CR14 and CR15 help the
operational amplifier (US) slew the large-value capac-
itor (C85) . The output of the loop filter tunes the VCO
frequency to the value needed to maintain phase Jock.
17.2.4.5.3 VCO and Amplifier
The 34.3-MHz VCO (Ql) is a Colpitts-type oscillator
that resonates CR2, CR3, ClO, Cll, C47, and C68 with
the inductance of transformer Tl. Capacitor C68 is
adjusted to provide a tuning voltage of 8 to lOV at TPl
when the loop is locked. Transistor Q8 is the VCO ON/
OFF switch, which is controlled by PLL IC Ul via the
SW2 output. The amplifier (Q2) following the VCO
provides an output of +7 dB. This signal is atten-
uated by R37 and R38 before going to the two-modu-
lus pre-scaler, U3.
17.2.4.6 Offset Selection
The 45 MHz offset is generated by routing the 34.3
MHz PLL output through a pin diode switch, CR17,
(which is controlled by SWl on U2) to the mixer UlO.
Here the 34.3 MHz signal is mixed with the LO OFF-
SET signal. The output ofUlO is routed to the output
portJ6.
To generate the 39 MHz offset, the 6 MHz signal is
mixed with the 34.3 MHz signal at U9 to generate 28.3
MHz. This signal is t hen mixed with the LO OFFSET
signal at UlO. The 34.3 MHz signal is prevented from
mixing directly at UlO by the pin diode switch, CR17.
To generate the 55 MHz offset, the 10 MHz signal is
mixed with the 34.3 MHz signal at U9 to generate 44.3
MHz. This signal is then mixed with the LO OFFSET
signal at UlO. The 34.3 MHz signal is prevented from
mixing directly at UlO by the pin diode switch, CR17.
To generate the 0 to 10 MHz offset, mixer U9 mixes
the 34.3 MHz PLL output with the 35 to 45 MHz PLL
17-6
output. The mixer output is low pass filtered to obtain
the difference product. The signal is then amplified
and applied to the LO OFFSET mixer UlO where it is
mixed with the LO OFFSET signal.
17.2.4.7 Modulation
FM modulation of the Duplex Generator is accom-
plished by directly modulating the VCO in the 34.3-
MHz PLL. The sensitivity of this input port is adjusted
by R69 to 5 kHz/V. The frequency response of the
modulation input is 1 Hz to 20 kHz.
17.2.4.8 Board Control
The enhanced Duplex Generator board is con-
trolled by the
PLL
ICs Ul and U2, which use the RF
control bus coming from the Processor Interface board
(All) and a signal from the Front Panel Interface
board (A15).
The PLL ICs each use a data word comprised of the
last 19 bits of the RF data bus. The first time this word
is sent, data is latched to the 34.3 MHz PLL by DATA
LATCH 2. The second time the word is sent, data is
latched to the 35 to 45 MHz PLL by DATA LATCH.
The first two bits of each word control the two output
switches SWl and SW2, as shown in Table 17-2. The
next ten bits control the divide-by-Nand the last seven
bits control the divide-by-A.
Table 17-2. Switch Control
Switch Position Condition
I I
U1 U2
SW1 SW2 SW1 SW2
1 1 1 1 0-10 MHz Offset
0 1 1 1 39 MHz Offset
0 1 0 1
45 MHz Offset
0 1 1 0 55 MHz Offset
0 0
1
0
Duplex Off