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SECTION 15.
FRONT-PANEL INTERFACE BOARD (A15)
15.1
DESCRIPTION
The
Front-Panel
Interface
board
provides
two
sys-
tem
func
tions.
The
first
of
these
is
to interface the
sys-
t
em's
Processor board
(AI4
)
with
other
system
modules:
primarily the
Receiver board
(A8),
the
Front-
Panel
Interface
board
itself,
the
RF Input
module
(A
I
7), and the
Front Panel
(AI8).
The
second
func-
tion
is to
provide
an
analog
interface between
I
)
exter-
nal
signals
or
internal-
modulation/demodulation
signals
and 2)
the basic
measurement
functions
in
the
System
Ana
lyzer,
the
DVM,
t he
scope,
and the fre-
quency
counter.
A
block
diagram
of
the
Front-Panel Interface board
is
shown
at
the end
of this
section
in
Figure
I5-
I
,
a
schematic
in
Figure
I
5-2,
and
the
printed
wiring
board
assembly
and
parts
list
in Figure
I5-3.
15.1.1 PROCESSOR-CONTROL INTERFACE
Control
information
for
the front
panel
is
carried
by
the AF DATA
BUS
in
4-bit
groups.
Information
that
the microprocessor
reads
from
t
he
Front-Panel
Inter-
face includes
encoded
data
from
the RF
ATTN
O-I30
and
hor izontal SWP SEL
inputs,
data
from
the
verti-
cal
RNG
SEL
INPUTS,
and
data from other
miscel-
laneous
inputs.
Information
that the
microprocessor
!\ends
to
the Front-Panel Interface
includes data
that
controls
the input
switches (Q2,
Q3,
Q6), the
range
attenuator
(Q4,
Q5,
Q7, Q8), and
the
LEDs
on
the
front
panel.
Data
is
transferred to the AF
DATA
BUS
by
3-state
input
buff"
e
rs
UI3,
UI
7,
UI
9, and U20, and
it is
trans-
fer red
from
the
AF DATA
BUS
by latches U8
and
U9.
The
microprocessor
sequentially
addresses
each
buffer
and
latch
through
the
AF
ADD BUS and
address
decoder
U21.
Data
is transferred
to/from the selected
latch/buff"
e
r while the
AF
BUS
EN
2 signal is
low.
15.1.2
ANALOG
INTERFACE
The
analog
outputs
of the
Front-Panel
Interface
are
drive
n
by fou
r
amplifiers:
the
scope-vertical
pre-
amplifier
(U3,
Q9,
Ql3,
QI4),
the DVM
buffer
ampli-
fier
(U5, U6, U4B),
t he frequency-counter
pre-ampli
-
fier
(Ql2,
U7) and the scope-horizontal pre-amplifier
(U4A)
. Circuits
for
input
selection
(K2-K4,
Q2, Q3,
Q6),
the
range
attenuator
(K5-K8,
Q4,
Q5,
Q7,
Q8),
and
15-1
the unity-gain buffer
amplifier
(QI
)
drive t
he
inputs
of
the
first
three
amplifiers.
The
input to t he
scope-
horizontal
pre-amplifier
comes
directly
from
the edge-
card
connector.
15.2
THEORY
OF OPERATION
15.2.1 PROCESSOR-CONTROL
INTERFACE
15.2.1.1
AF
Bus
Information
is
carried between
the
microprocessor
and
the F
ront-Panel
Interface
by
the
AF
Bus.
It
con-
sists of
a
4-bit,
tri-state data
bus
(AF
DATA
BUS
0-3)
and
a
4-bit
address bus
(AF
ADD
BUS
0-3).
When
AF
BUS
EN 2
is
asserted
low,
the
input/output (I/0)
function
of
the AF DATA
BUS
lines
is
determined
by
the address
on
the
AF
ADD
BUS lines.
Depending on
that
address, address
decoder
U2I
can
select
the fol-
lowing I/0
devices:
1)
data
buffers
UI3, UI7,
UI9, and
U20; 2)
data
latches U8
and
U9;
and
data
latches
A18U6, AI8U7,
and
AI8U8.
A
summary of
the
functions of
the
AF DATA
BUS
lines
for
each state
of t he
AF
ADD
BUS
is given
in
Table
I
5-
1.
15.2.1.2
LED Control
T he
AF BUS ADDRESSES
0,
I
,
and
2
control
the
output to
the
display, function, and
modulation
LEDs
on
the Front-Panel
Display
board
(Al8Al).
Latch-
selects
LSO,
LSI,
and
LS2 are
asserted low
to
latch
the
data that
is
present on t he
AF
ADD
BUS.
T hese
latch-
selects
and
the
AF DATA BUS
are
connected
to
the
Display board (AI8Al) via
JI and a
ribbon
cable
assembly.
Table
15-2 shows
which
LED
is
selected
when the
state
of
the AF DATA BUS
is
as
shown and the appro-
priate
latch-select (LSO,
LSI, or
LS2)
is
strobed
low.
15.2.1
.3 Range-Attenuator
Control
(ATTN
X1, X0.1,
X0.01
,
X0.001)
Location
3
of the
AF
BUS accesses
outputs
which
control
the range attenuator. Table
I
5-3 shows
the
allowable
states of these
four control
bits,
and
the
function of
those
states.
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