Figure 34. System Implementation Of The Two Dma Controllers (Stm32F42Xxx And Stm32F43Xxx) - ST STM32F405 Reference Manual

DMA controller (DMA)
Figure 34. System implementation of the two DMA controllers (STM32F42xxx and
DMA controller 2
DMA controller 1
1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case of the DMA2
controller, thus only DMA2 streams are able to perform memory-to-memory transfers.
10.3.2 DMA transactions
A DMA transaction consists of a sequence of a given number of data transfers. The number
of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are software-
programmable.
Each DMA transfer consists of three operations:
•
A loading from the peripheral data register or a location in memory, addressed through
the DMA_SxPAR or DMA_SxM0AR register
•
A storage of the data loaded to the peripheral data register or a location in memory
addressed through the DMA_SxPAR or DMA_SxM0AR register
•
A post-decrement of the DMA_SxNDTR register, which contains the number of
transactions that still have to be performed
306/1749
DMA request
MAPPING
STM32F43xxx)
Bus Matrix
DCODE
(AHB multilayer)
ICODE
RM0090 Rev 18
Flash
memory
112 KB SRAM
16 KB SRAM
64 KB SRAM
AHB1 peripherals
AHB-APB
APB2
APB2
bridge2
peripherals
(dual AHB)
AHB-APB
APB1
APB1
bridge1
peripherals
(dual AHB)
AHB2 peripherals
External memory
controller (FMC)
RM0090
MS30438V1