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GigaDevice Semiconductor GD32H737 User Manual

Arm cortex-m7 32-bit mcu

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GigaDevice Semiconductor Inc.

GD32H737/757/759

®

Arm

Cortex

-M7 32-bit MCU

®

User Manual

Revision 1.0

(May. 2023)

Table of Contents

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Page 1 GigaDevice Semiconductor Inc. GD32H737/757/759 ® Cortex -M7 32-bit MCU ® User Manual Revision 1.0 (May. 2023)
Page 2: Table Of Contents
GD32H737/757/759 User Manual Table of Contents Table of Contents ......................2 List of Figures ......................38 List of Tables ........................ 52 1. System and memory architecture ................ 59 -M7 processor ..................59 ® ® 1.1. Cortex System architecture ....................60 1.2.
Page 3 GD32H737/757/759 User Manual 1.8.18. FPU interrupt enable register (SYSCFG_FPUINTEN) ............99 1.8.19. SRAM configuration register 0 (SYSCFG_SRAMCFG0) ........... 100 1.8.20. SRAM configuration register 1 (SYSCFG_SRAMCFG1) ........... 101 1.8.21. TIMERx configuration register 0 (SYSCFG_TIMERxCFG0, x=0, 7) ........101 1.8.22. TIMERx configuration register 1 (SYSCFG_TIMERxCFG1, x=0, 7) ........104 1.8.23.
Page 4 GD32H737/757/759 User Manual 2.3.2. RAMECCMU monitor x control register (RAMECCMU_MxCTL) ........131 2.3.3. RAMECCMU monitor x status register (RAMECCMU_MxSTAT) ........132 2.3.4. RAMECCMU monitor x failing address register (RAMECCMU_MxFADDR) ..... 133 2.3.5. RAMECCMU monitor x failing data low register (RAMECCMU_MxFDL) ......134 2.3.6.
Page 5 GD32H737/757/759 User Manual 3.4.17. Option byte status register 1 (FMC_OBSTAT1_EFT) ............174 3.4.18. Option byte status register 1 (FMC_OBSTAT1_MDF) ............175 3.4.19. NO-RTDEC area register (FMC_NODEC) ................. 176 3.4.20. AES IV register (FMC_AESIVx_EFT) (x = 0…2) ..............176 3.4.21. AES IV register (FMC_AESIVx_MDF) (x = 0…2) ............... 177 3.4.22.
Page 6 GD32H737/757/759 User Manual 5.4.6. Parameter register (PMU_PAR) ..................217 6. Reset and clock unit (RCU) ................. 219 Reset control unit (RCTL) ..................219 6.1. 6.1.1. Overview ..........................219 6.1.2. Function overview ....................... 219 Clock control unit (CCTL) ..................220 6.2.
Page 7 GD32H737/757/759 User Manual 6.3.33. PLL2 register (RCU_PLL2) ....................290 6.3.34. Clock configuration register 1 (RCU_CFG1) ..............292 6.3.35. Clock configuration register 2 (RCU_CFG2) ..............294 6.3.36. Clock configuration register 3 (RCU_CFG3) ..............296 6.3.37. PLL all configuration register (RCU_PLLALL) ..............298 6.3.38.
Page 8 GD32H737/757/759 User Manual 8.6.2. Event enable register 0 (EXTI_EVEN0) ................336 8.6.3. Rising edge trigger enable register 0 (EXTI_RTEN0) ............336 8.6.4. Falling edge trigger enable register 0 (EXTI_FTEN0) ............337 8.6.5. Software interrupt event register 0 (EXTI_SWIEV0) ............337 8.6.6.
Page 9 GD32H737/757/759 User Manual 9.5.25. Trigger selection for TIMER1_ETI register (TRIGSEL_TIMER1ETI) ......... 369 9.5.26. Trigger selection for TIMER2_ETI register (TRIGSEL_TIMER2ETI) ......... 370 9.5.27. Trigger selection for TIMER3_ETI register (TRIGSEL_TIMER3ETI) ......... 371 9.5.28. Trigger selection for TIMER4_ETI register (TRIGSEL_TIMER4ETI) ......... 371 9.5.29.
Page 10 GD32H737/757/759 User Manual 10.3.12. Analog configuration for ADC ..................... 393 10.3.13. Input filtering ........................394 Register definition ....................397 10.4. 10.4.1. Port control register (GPIOx_CTL, x=A...H, J, K) ............... 397 10.4.2. Port output mode register (GPIOx_OMODE, x=A…H, J, K) ..........399 10.4.3.
Page 11 GD32H737/757/759 User Manual 12.4. Register definition ....................423 12.4.1. Control register (TRNG_CTL) ..................... 423 12.4.2. Status register (TRNG_STAT) .................... 425 12.4.3. Data register (TRNG_DATA)....................426 12.4.4. Health tests configure register (TRNG_HTCFG) ..............426 Cryptographic Acceleration Unit (CAU) ............428 Overview ....................... 428 13.1.
Page 12 GD32H737/757/759 User Manual 14.4.3. Hash mode .......................... 463 14.4.4. HMAC mode ........................463 HAU suspended mode ..................463 14.5. 14.5.1. Transfer data by CPU ......................464 14.5.2. Transfer data by DMA ......................464 HAU interrupt ......................465 14.6. 14.6.1. Input FIFO interrupt ......................465 14.6.2.
Page 13 GD32H737/757/759 User Manual 16.3.6. Switch-buffer mode ......................500 16.3.7. Transfer operation ....................... 501 16.3.8. Transfer finish ........................502 16.3.9. Channel configuration ......................503 Interrupts ......................504 16.4. 16.4.1. Flag ............................. 505 16.4.2. Exception ..........................505 16.4.3. Error ............................ 506 16.4.4.
Page 14 GD32H737/757/759 User Manual 17.4.12. Channel x control register 1 (MDMA_CHxCTL1) ............... 544 17.4.13. Channel x mask address register (MDMA_CHxMADDR) ..........545 17.4.14. Channel x mask data register (MDMA_CHxMDATA) ............546 DMA request multiplexer (DMAMUX) .............. 547 Overview ....................... 547 18.1.
Page 15 GD32H737/757/759 User Manual Analog-to-digital converter (ADC) ..............578 Overview ....................... 578 20.1. Characteristics ..................... 578 20.2. Pins and internal signals ..................579 20.3. Function overview ....................580 20.4. 20.4.1. Foreground calibration function ..................580 20.4.2. Dual clock domain architecture ................... 581 20.4.3.
Page 16 GD32H737/757/759 User Manual 20.7.13. Routine sequence register 7 (ADC_RSQ7) ................. 611 20.7.14. Routine sequence register 8 (ADC_RSQ8) ................ 612 20.7.15. Routine data register (ADC_RDATA) .................. 613 20.7.16. Oversample control register (ADC_OVSAMPCTL) ............613 20.7.17. Watchdog 1 Channel Selection Register (ADC_WD1SR) ..........615 20.7.18.
Page 17 GD32H737/757/759 User Manual 21.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) ....637 21.4.12. DAC_OUT0 data output register (OUT0_DO) ..............637 21.4.13. DAC_OUT1 data output register (OUT1_DO) ..............638 21.4.14. DAC Status register 0 (DAC_STAT0) ................. 638 21.4.15. DAC calibration Register (DAC_CALR) ................639 21.4.16.
Page 18 GD32H737/757/759 User Manual 23.3.17. RTC power saving mode management ................667 23.3.18. RTC interrupts ........................668 Register definition ....................669 23.4. 23.4.1. Time register (RTC_TIME) ....................669 23.4.2. Date register (RTC_DATE) ....................669 23.4.3. Control register (RTC_CTL) ....................670 23.4.4.
Page 19 GD32H737/757/759 User Manual General level4 timer (TIMERx, x=15,16) .............. 924 24.4. 24.4.1. Overview ..........................924 24.4.2. Characteristics ........................924 24.4.3. Block diagram ........................924 24.4.4. Function overview ....................... 925 24.4.5. Register definition(TIMERx, x=15,16) ................. 942 Basic timer (TIMERx, x=5,6,50,51) ............... 968 24.5.
Page 20 GD32H737/757/759 User Manual 25.4.9. Interrupt status clear register (USART_INTC) ..............1017 25.4.10. Receive data register (USART_RDATA) ................1018 25.4.11. Transmit data register (USART_TDATA) ................1019 25.4.12. USART coherence control register (USART_CHC)............1019 25.4.13. USART FIFO control and status register (USART_FCS) ..........1020 Inter-integrated circuit interface (I2C) ............
Page 21 GD32H737/757/759 User Manual SPI function overview ..................1065 27.3. 27.3.1. SPI block diagram ......................1065 27.3.2. SPI signal description ....................... 1065 27.3.3. SPI clock timing and data format ..................1067 27.3.4. SPI clock delay mode ....................... 1068 27.3.5. RxFIFO and TxFIFO ......................1070 27.3.6.
Page 22 GD32H737/757/759 User Manual 28.3.1. OSPIM block diagram ......................1122 28.3.2. OSPIM matrix........................1122 28.4. Register definition ....................1123 28.4.1. Port configuration register (OSPIM_PCFGx) (x = 0, 1) ............. 1123 Octal-SPI interface(OSPI) ................1125 29.1. Overview ......................1125 29.2. Characteristics ....................1125 29.3.
Page 23 GD32H737/757/759 User Manual 29.10.17. Wrap timing configuration register (OSPI_WPTIMCFG) ........... 1151 29.10.18. Wrap instruction register (OSPI_WPINS) ................1152 29.10.19. Wrap alternate byte register (OSPI_WPALTE) ..............1152 29.10.20. Write transfer configuration register (OSPI_WTCFG) ............1153 29.10.21. Write timing configuration register (OSPI_WTIMCFG) ............1155 29.10.22.
Page 24 GD32H737/757/759 User Manual 31.7.10. Cropping window size register (DCI_CWSZ) ..............1179 31.7.11. DATA register (DCI_DATA) ....................1179 TFT-LCD interface (TLI) .................. 1180 Overview ......................1180 32.1. Characteristics ....................1180 32.2. Block diagram ..................... 1180 32.3. Signal description ....................1181 32.4.
Page 25 GD32H737/757/759 User Manual Receiver of Sony/Philips Digtial Interface (RSPDIF) ........1201 Overview ......................1201 33.1. Characteristics ....................1201 33.2. Function overview ....................1201 33.3. 33.3.1. RSPDIF block diagram ..................... 1201 33.3.2. S/PDIF protocol......................... 1203 33.3.3. RSPDIF ..........................1205 33.3.4. RSPDIF synchronization process ..................1210 33.3.5.
Page 26 GD32H737/757/759 User Manual 34.3.17. DMA interface ........................1261 34.3.18. Enable/Disable ........................1261 34.3.19. Error flags ......................... 1261 34.3.20. Interrupts ........................... 1264 34.4. Register definition ....................1265 34.4.1. Synchronize configuration register (SAI_SYNCFG) ............1265 34.4.2. Block x configuration register0 (SAI_BxCFG0) (x = 0,1) ..........1265 34.4.3.
Page 27 GD32H737/757/759 User Manual 35.7.6. Background memory base address register (IPA_BMADDR) .......... 1306 35.7.7. Background line offset register (IPA_BLOFF)..............1306 35.7.8. Foreground pixel control register (IPA_FPCTL) ............... 1307 35.7.9. Foreground pixel value register (IPA_FPV) ..............1308 35.7.10. Background pixel control register (IPA_BPCTL) ............... 1309 35.7.11.
Page 28 GD32H737/757/759 User Manual Programming sequence..................1366 36.5. 36.5.1. Card identification ......................1366 36.5.2. Boot operation........................1367 36.5.3. No data commands ......................1370 36.5.4. Single block or multiple block write ................... 1370 36.5.5. Single block or multiple block read ................... 1371 36.5.6.
Page 29 GD32H737/757/759 User Manual 37.4.2. Typical Usage Sequence ....................1406 37.5. Register definition ....................1408 37.5.1. Control register (MDIO_CTL) .................... 1408 37.5.2. Received frame information register (MDIO_RFRM) ............1408 37.5.3. Received data register (MDIO_RDATA) ................1409 37.5.4. Received address register (MDIO_RADDR) ..............1409 37.5.5.
Page 30 GD32H737/757/759 User Manual Block diagram ....................1480 40.3. Function overview ....................1481 40.4. 40.4.1. LPDTS internal signals ..................... 1481 40.4.2. Operating modes ......................1481 40.4.3. Temperature measurement principles ................1481 40.4.4. Sampling time ........................1482 40.4.5. Trigger input ........................1483 40.4.6.
Page 31 GD32H737/757/759 User Manual Function overview ....................1503 42.3. 42.3.1. Mailbox descriptor ......................1504 42.3.2. Rx FIFO descriptor ......................1509 42.3.3. Communication modes ..................... 1515 42.3.4. Power saving modes ......................1516 42.3.5. Data transmission ......................1517 42.3.6. Data reception........................1521 42.3.7.
Page 32 GD32H737/757/759 User Manual 42.5.26. Pretended Networking mode received wakeup mailbox x identifier register (CAN_PN_RWMxI)(x=0..3) ......................1567 42.5.27. Pretended Networking mode received wakeup mailbox x data 0 register (CAN_PN_RWMxD0)(x=0..3) ......................1567 42.5.28. Pretended Networking mode received wakeup mailbox x data 1 register (CAN_PN_RWMxD1)(x=0..3) ......................
Page 33 GD32H737/757/759 User Manual 43.4.18. MAC address 2 high register (ENET_MAC_ADDR2H) ............ 1645 43.4.19. MAC address 2 low register (ENET_MAC_ADDR2L) ............1646 43.4.20. MAC address 3 high register (ENET_MAC_ADDR3H) ............ 1646 43.4.21. MAC address 3 low register (ENET_MAC_ADDR3L) ............1647 43.4.22. MAC flow control threshold register (ENET_MAC_FCTH) ..........1647 43.4.23.
Page 34 GD32H737/757/759 User Manual Comparator (CMP) ..................1679 44.1. Overview ......................1679 Characteristic ..................... 1679 44.2. Function overview ....................1679 44.3. 44.3.1. CMP clock and reset ......................1680 44.3.2. CMP I/O configuration....................... 1680 44.3.3. CMP output blanking......................1681 44.3.4. CMP register write protection ................... 1682 44.3.5.
Page 35 GD32H737/757/759 User Manual Real-time decryption (RTDEC) ............... 1735 46.1. Overview ......................1735 46.2. Characteristics ....................1735 Function overview ....................1735 46.3. 46.3.1. RTDEC real-time decryption introduction ................. 1736 46.3.2. RTDEC real-time decryption introduction ................. 1736 46.3.3. Decryption with AES-128 in counter mode ............... 1738 46.3.4.
Page 36 GD32H737/757/759 User Manual 47.4.2. FAC X1 buffer configure register (FAC_X1BCFG) ............1767 47.4.3. FAC Y buffer configure register (FAC_YBCFG) ..............1768 47.4.4. FAC Parameter configure register (FAC_PARACFG) ............1769 47.4.5. FAC Control register (FAC_CTL) ..................1769 47.4.6. FAC Status register (FAC_STAT) ..................1771 47.4.7.
Page 37 GD32H737/757/759 User Manual 49.6. Interrupts ......................1804 49.7. Register definition ....................1807 49.7.1. USBHS global registers ....................1807 49.7.2. Host control and status registers ..................1836 49.7.3. Device control and status registers .................. 1850 49.7.4. Power and clock control register (USBHS_PWRCLKCTL) ..........1879 Appendix ......................
Page 38: List Of Figures
GD32H737/757/759 User Manual List of Figures -M7 processor ............60 ® Figure 1-1. The structure of the Cortex Figure 1-5. The system architecture of GD32H7xx devices ........... 62 Figure 1-2. Bus matrix Region 0 ....................63 Figure 1-3. Bus matrix Region 1 ....................64 Figure 1-4.
Page 39 GD32H737/757/759 User Manual Figure 10-1. Basic structure of a standard I/O port bit ............389 Figure 10-2. Input configuration ....................390 Figure 10-3. Output configuration ................... 391 Figure 10-4. Analog configuration ..................392 Figure 10-5. Alternate function configuration ................ 392 Figure 10-6.
Page 40 GD32H737/757/759 User Manual Figure 18-3. Event generation....................551 Figure 19-1. Block diagram of JTAG unit ................568 Figure 20-1. ADC module block diagram ................580 Figure 20-2. Single operation mode ..................583 Figure 20-3. Continuous operation mode ................584 Figure 20-4. Scan operation mode, continuous disable ............585 Figure 20-5.
Page 41 GD32H737/757/759 User Manual Figure 24-19. Channel x output PWM with (CHxVAL < CHxCOMVAL_ADD) ...... 709 Figure 24-20. Channel x output PWM with (CHxVAL = CHxCOMVAL_ADD) ...... 709 Figure 24-21. Channel x output PWM with (CHxVAL > CHxCOMVAL_ADD) ...... 709 Figure 24-22. Channel x output PWM with CHxVAL or CHxCOMVAL_ADD exceeds CARL .............................
Page 42 GD32H737/757/759 User Manual Figure 24-58. Input capture logic .................... 812 Figure 24-59. Output compare logic (x=0,1,2,3) ..............813 Figure 24-60. Output-compare under three modes ............... 814 Figure 24-61. Timing chart of EAPWM ..................815 Figure 24-62. Timing chart of CAPWM ..................815 Figure 24-63.
Page 43 GD32H737/757/759 User Manual Figure 24-98. Channel x output PWM duty cycle changing with CHxCOMVAL_ADD ..877 Figure 24-99. CHx_O output with a pulse in edge-aligned mode (CHxOMPSEL =2’b00) .. 878 Figure 24-100. Complementary output with dead-time insertion ........882 Figure 24-101. BREAK0 function logic diagram ..............883 Figure 24-102.
Page 44 GD32H737/757/759 User Manual Figure 25-9. Break frame occurs during idle state ..............991 Figure 25-10. Break frame occurs during a frame ..............991 Figure 25-11. Example of USART in synchronous mode ............. 992 Figure 25-12. 8-bit format USART synchronous waveform (CLEN = 1) ......992 Figure 25-13.
Page 45 GD32H737/757/759 User Manual Figure 27-6. NSS interlaced pulses timing diagram (MSSD[3:0] = 0011 (3 x Tclk), MDFD = 0011 (3 x Tclk)) ........................ 1075 Figure 27-7. A typical full-duplex connection ..............1076 Figure 27-8. A typical simplex connection (Master: Receive, Slave: Transmit) ....1077 Figure 27-9.
Page 46 GD32H737/757/759 User Manual Figure 27-33. LSB justified standard timing diagram (DTLEN = 01, CHLEN = 1, CKPL = 0) ............................1093 Figure 27-34. LSB justified standard timing diagram (DTLEN = 01, CHLEN = 1, CKPL = 1) ............................1093 Figure 27-35. LSB justified standard timing diagram (DTLEN = 00, CHLEN = 1, CKPL = 0) ............................
Page 47 GD32H737/757/759 User Manual Figure 29-4 OSPI command format in quad mode ............... 1129 Figure 29-5 CSN and SCK behavior ..................1131 Figure 30-1. Schematic diagram of CPDM ................1158 Figure 30-2. CPDM delay line length configuration flowchart ..........1159 Figure 30-3. CPDM output clock phase configuration flowchart ........1160 Figure 31-1.
Page 48 GD32H737/757/759 User Manual ............................1249 Figure 34-17. Four microphones, under different slot widths, BxDATA register data format ............................1251 Figure 34-18. Dual microphones, under different slot widths, BxDATA register data format ............................1251 Figure 34-19 AC'97 slot partition ................... 1253 Figure 34-20 AC'97 tag definition ..................
Page 49 GD32H737/757/759 User Manual Figure 37-4. MDIO slave communication process .............. 1407 Figure 38-1. The EXMC block diagram ................. 1416 Figure 38-2. EXMC memory banks ..................1418 Figure 38-3. Four regions of bank0 address mapping ............1419 Figure 38-4. NAND address mapping ................... 1420 Figure 38-5.
Page 50 GD32H737/757/759 User Manual Figure 42-2. Transmitter delay ....................1534 Figure 42-3. CAN bit time ....................... 1537 Figure 43-1. ENET module block diagram ................1573 Figure 43-2. MAC / Tagged MAC frame format ..............1575 Figure 43-3. Station management interface signals ............1577 Figure 43-4.
Page 51 GD32H737/757/759 User Manual Figure 48-1. HWSEM diagram ....................1774 Figure 48-2. HWSEM state machine ..................1775 Figure 48-3. First try lock success ..................1777 Figure 48-4. Second try lock success................... 1778 Figure 48-5. Second try lock fail .................... 1778 Figure 48-6. HWSEM interrupt logic ..................1778 Figure 49-1.
Page 52: List Of Tables
GD32H737/757/759 User Manual List of Tables Table 1-1. The interconnection relationship of the interconnect matrix ......61 Table 1-2. Memory map of GD32H7xx devices ................ 65 Table 1-3. Configuration of ITCM/DTCM/AXI SRAM ..............74 Table 1-4. Boot mode selection ....................75 Table 1-5.
Page 53 GD32H737/757/759 User Manual Table 15-11. Mode 7 description ....................483 Table 15-12. Mode 8 description ....................484 Table 15-13. Recommended scaling factors in mode 8 ............484 Table 15-14. Mode 9 description ....................484 Table 15-15. Recommended scaling factors in mode 9 ............485 Table 16-1.
Page 54 GD32H737/757/759 User Manual Table 24-7. Counting direction in different quadrature decoder signals ......721 Table 24-8. the counter operation in in non-quadrature decoder mode 1 ......723 Table 24-9. Examples of slave mode ..................725 Table 24-10.The Composite PWM pulse width ..............816 Table 24-11.
Page 55 GD32H737/757/759 User Manual Table 31-7. Memory view in half-word padding mode ............1169 Table 31-8. Status/Error flags ....................1169 Table 32-1. Pins of display interface provided by TLI ............1181 Table 32-2. Supported pixel formats ..................1183 Table 32-3. Status flags ......................1185 Table 32-4.
Page 56 GD32H737/757/759 User Manual Table 36-2. SDIO operation modes for SD & SD I/O card ........... 1327 Table 36-3. SDIO operation modes for e•MMC card ............1327 Table 36-4. SDIO internal input/output singnals ..............1328 Table 36-5. SDIO pins functions .................... 1329 Table 36-6.
Page 57 GD32H737/757/759 User Manual Table 38-2. SDRAM mapping ....................1422 Table 38-3. NOR flash interface signals description ............1422 Table 38-4. PSRAM non-muxed signal description ............. 1423 Table 38-5. EXMC bank 0 supports all transactions ............1423 Table 38-6. NOR / PSRAM controller timing parameters ............ 1425 Table 38-7.
Page 58 GD32H737/757/759 User Manual (DFM=0) ..........................1612 Table 43-8. Supported time stamp snapshot with PTP register configuration ....1657 Table 44-1. CMP inputs and outputs summary ..............1681 Table 45-1. HPDF pins definition ................... 1692 Table 45-2. HPDF internal signal ................... 1693 Table 45-3.
Page 59: System And Memory Architecture
GD32H737/757/759 User Manual System and memory architecture The devices of GD32H7xx series are 32-bit general-purpose microcontrollers based on the ® ® ® ® Cortex -M7 processor. The Arm Cortex -M7 processor includes 64-bit AMBA4 AXI, 32-bit AHB peripheral (AHBP) port, 32-bit AHB slave (AHBS) port for external master to access memories and APB interface for CoreSight debug components.
Page 60: System Architecture
GD32H737/757/759 User Manual  Nested Vectored Interrupt Controller (NVIC)  Flash Patch and Breakpoint (FPB)  Data Watchpoint and Trace (DWT)  Instrumentation Trace Macrocell (ITM)  Embedded Trace Macrocell (ETM)  JTAG or SWD Debug Port  Trace Port Interface Unit (TPIU) ...
Page 61: Table 1-1. The Interconnection Relationship Of The Interconnect Matrix
GD32H737/757/759 User Manual relationship of the interconnect matrix is shown in Table 1-1. The interconnection matrix. In the following table, “1” indicates the relationship of the interconnect corresponding master is able to access the corresponding slave through the interconnect matrix, while the blank means the corresponding master cannot access the corresponding slave through the interconnect matrix.
Page 62: Figure 1-5. The System Architecture Of Gd32H7Xx Devices
GD32H737/757/759 User Manual Figure 1-2. The system architecture of GD32H7xx devices Powered By LDO (0.9V) TPIU SW/JTA G I-Cache AHBP 32KB D-Cache DTCM 32KB ITCM ARM Cortex-M7 RAM share d Processor Fmax: 600MHz AXI SRAM AXIM Flash Memory Powered By V...
Page 63: Bus Matrix Region 0
GD32H737/757/759 User Manual Bus matrix Region 0 1.2.1. The 64-bit AXI bus matrix Region 0 is shown in Figure 1-3. Bus matrix Region Figure 1-3. Bus matrix Region 0 64-bit AXI bus matrix Region 0 Cortex-M7 AHBP to Region 1...
Page 64: Bus Matrix Region 2
GD32H737/757/759 User Manual Figure 1-4. Bus matrix Region 1 32-bit AHB bus matrix Ethernet Ethernet DMA0 DMA1 SDIO1 USBHS0 USBHS1 Region 1 MAC0 MAC1 AHBP to Region 1 AHB Master interface APB Master interface Region 0 to Region 1 Slave interface...
Page 65: Memory Map
GD32H737/757/759 User Manual 1.3. Memory map ® ® The Arm Cortex -M7 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. Table 1-2. Memory map of GD32H7xx devices shows the memory map of the GD32H7xx series devices, including Code, SRAM, peripheral, and other pre-defined regions.
Page 66 GD32H737/757/759 User Manual Pre-defined Address Peripherals Regions Reserved 0x5800 6C00 - 0x5800 6FFF LPDTS 0x5800 6800 - 0x5800 6BFF 0x5800 5800 - 0x5800 67FF Reserved 0x5800 5400 - 0x5800 57FF Reserved 0x5800 4C00 - 0x5800 53FF FWDGT 0x5800 4800 - 0x5800 4BFF...
Page 67 GD32H737/757/759 User Manual Pre-defined Address Peripherals Regions 0x5006 1000 - 0x50FF FFFF Reserved 0x5006 0C00 - 0x5006 0FFF Reserved 0x5006 0800 - 0x5006 0BFF Reserved 0x5006 0400 - 0x5006 07FF Reserved 0x5006 0000 - 0x5006 03FF Reserved 0x5005 0400 - 0x5005 FFFF...
Page 68 GD32H737/757/759 User Manual Pre-defined Address Peripherals Regions 0x4003 3000 - 0x4003 7FFF Reserved 0x4003 0000 - 0x4003 2FFF Reserved 0x4002 C000 - 0x4002 FFFF Reserved 0x4002 BC00 - 0x4002 BFFF 0x4002 B000 - 0x4002 BBFF ENET1 0x4002 A000 - 0x4002 AFFF...
Page 69 GD32H737/757/759 User Manual Pre-defined Address Peripherals Regions 0x4001 8000 - 0x4001 83FF Reserved(APB2) 0x4001 7C00 - 0x4001 7FFF Reserved 0x4001 7800 - 0x4001 7BFF Reserved 0x4001 7400 - 0x4001 77FF Reserved 0x4001 7000 - 0x4001 73FF HPDF 0x4001 6C00 - 0x4001 6FFF...
Page 70 GD32H737/757/759 User Manual Pre-defined Address Peripherals Regions 0x4000 DC00 - 0x4000 DFFF Reserved 0x4000 D800 - 0x4000 DBFF Reserved 0x4000 D400 - 0x4000 D7FF Reserved 0x4000 D000 - 0x4000 D3FF Reserved 0x4000 CC00 - 0x4000 CFFF Reserved 0x4000 C800 - 0x4000 CBFF...
Page 71 GD32H737/757/759 User Manual Pre-defined Address Peripherals Regions 0x4000 1000 - 0x4000 13FF TIMER5 0x4000 0C00 - 0x4000 0FFF TIMER4 0x4000 0800 - 0x4000 0BFF TIMER3 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x3880 1000 - 0x3FFF FFFF...
Page 72 GD32H737/757/759 User Manual Pre-defined Address Peripherals Regions 0x1FFF 7800 - 0x1FFF 7A0F Reserved 0x1FFF 7400 - 0x1FFF 77FF Reserved 0x1FFF 7000 - 0x1FFF 73FF Reserved 0x1FFF 0000 - 0x1FFF 6FFF Reserved 0x1FFE C010 - 0x1FFE FFFF Reserved 0x1FFE C000 - 0x1FFE C00F...
Page 73: On-Chip Sram Memory
GD32H737/757/759 User Manual On-chip SRAM memory 1.3.1. The devices of GD32H7xx series contain up to 512KB of on-chip SRAM (AXI SRAM), 4KB of backup SRAM and up to 512KB RAM shared by ITCM/DTCM/AXI SRAM. All of AHB SRAM support byte, half-word (16 bits), and word (32 bits) accesses. The on-chip SRAM (AXI SRAM) support byte, half-word (16 bits), word (32 bits) and double words (64 bits) accesses.
Page 74: Figure 1-7. Block Digram Of Ram Shared By Itcm/Dtcm/Axi Sram
GD32H737/757/759 User Manual 512KB of RAM can be used by ITCM or DTCM or AXI SRAM, which can be configured through ITCM_SZ_SHRRAM and DTCM_SZ_SHRRAM bits in option byte status register 1 register, as described in Table 1-3. Configuration of ITCM/DTCM/AXI SRAM.
Page 75: On-Chip Flash Memory Overview
GD32H737/757/759 User Manual 1000 1001 1001 0000 1001 0111 1001 1000 1001 1001 1010 0000 On-chip flash memory overview 1.3.2. The devices provide high density on-chip flash memory, which is organized as follows:  Up to 3840KB of main flash memory ...
Page 76: System Configuration Controller (Syscfg)
GD32H737/757/759 User Manual Table 1-5. Details of Boot mode BOOT_ADDRESS SPC[7:0] (configured in BOOT_MODE Boot from BOOT_ADDRx(x = 0,1)) XXXX SECURITY BOOT 0x9000_0000 USER BOOT OSPI0 0x7000_0000 USER BOOT OSPI1 Protection 0x0800_0000~max user level high USER BOOT BOOT_ADDRESS flash other...
Page 77: Timer Break Input Lock
GD32H737/757/759 User Manual 1.6. Timer break input lock When internal SRAM/FMC ECC error, LVD or CPU core lockup occurs, this function allows to disable TIMER output. Refer to Lockup control register (SYSCFG_LKCTL) for details. 1.7. AXI interconnect matrix (AXIIM) ®...
Page 78: Table 1-6. Configuration Of Asibs
GD32H737/757/759 User Manual The configurations of ASIB and AMIB are shown in Table 1-6. Configuration of ASIBs Table 1-7. Configuration of AMIBs. Table 1-6. Configuration of ASIBs ASIB Protocol Bus width Read issuing Write issuing Master interface INI 0 AHB-lite...
Page 79: System Configuration Registers
GD32H737/757/759 User Manual 1.8. System configuration registers SYSCFG base address: 0x5800 0400 Peripheral mode configuration register (SYSCFG_PMCFG) 1.8.1. Address offset: 0x004 Reset value: 0x0F00 0000 This register has to be accessed by word (32-bit). PC3SWO PC2SWO PA1SWO PA0SWO ENET0_P ENET1_P...
Page 80 GD32H737/757/759 User Manual This bit selects the Ethernet PHY interface. 0: MII is selected 1: RMII is selected ENET1_PHY_SEL Ethernet1 PHY interface selection This bit selects the Ethernet PHY interface. 0: MII is selected 1: RMII is selected 21:8 Reserved Must be kept at reset value.
Page 81: Exti Sources Selection Register 0 (Syscfg_Extiss0)
GD32H737/757/759 User Manual 1: Enable Fm+ mode EXTI sources selection register 0 (SYSCFG_EXTISS0) 1.8.2. Address offset: 0x008 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI3_SS[3:0] EXTI2_SS[3:0] EXTI1_SS[3:0] EXTI0_SS[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 82: Exti Sources Selection Register 1 (Syscfg_Extiss1)
GD32H737/757/759 User Manual 0101: PF1 pin 0110: PG1 pin 0111: PH1 pin 1010: PK1 pin EXTI0_SS[3:0] EXTI 0 sources selection 0000: PA0 pin 0001: PB0 pin 0010: PC0 pin 0011: PD0 pin 0100: PE0 pin 0101: PF0 pin 0110: PG0 pin...
Page 83: Exti Sources Selection Register 2 (Syscfg_Extiss2)
GD32H737/757/759 User Manual 0010: PC6 pin 0011: PD6 pin 0100: PE6 pin 0101: PF6 pin 0110: PG6 pin 0111: PH6 pin EXTI5_SS[3:0] EXTI 5 sources selection 0000: PA5 pin 0001: PB5 pin 0010: PC5 pin 0011: PD5 pin 0100: PE5 pin...
Page 84: Exti Sources Selection Register 3 (Syscfg_Extiss3)
GD32H737/757/759 User Manual 0001: PB11 pin 0010: PC11 pin 0011: PD11 pin 0100: PE11 pin 0101: PF11 pin 0110: PG11 pin 0111: PH11 pin 1001: PJ11 pin 11:8 EXTI10_SS[3:0] EXTI 10 sources selection 0000: PA10 pin 0001: PB10 pin 0010: PC10 pin...
Page 85 GD32H737/757/759 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI15_SS[3:0] EXTI14_SS[3:0] EXTI13_SS[3:0] EXTI12_SS[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI15_SS[3:0] EXTI 15 sources selection 0000: PA15 pin...
Page 86: Lockup Control Register (Syscfg_Lkctl)
GD32H737/757/759 User Manual 0010: PC12 pin 0011: PD12 pin 0100: PE12 pin 0101: PF12 pin 0110: PG12 pin 0111: PH12 pin Lockup control register (SYSCFG_LKCTL) 1.8.6. Address offset: 0x018 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 87: I/O Compensation Control Register (Syscfg_Cpsctl)
GD32H737/757/759 User Manual This bit is set by software and cleared by a system reset. 0: Region 1 SRAM0 ECC double error signal is disconnected from the break input of TIMER0/7/14/15/16 1: Region 1 SRAM0 ECC double error signal is connected from the break input of...
Page 88: I/O Compensation Cell Code Configuration Register (Syscfg_Cpscccfg)
GD32H737/757/759 User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. IOLV I/O in low voltage state 0: Product supply voltage is working higher than 2.5V 1: Product supply voltage is working below 2.5V 22:17 Reserved Must be kept at reset value.
Page 89: Timer Input Selection Register 0 (Syscfg_Timercisel0)
GD32H737/757/759 User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. PCPSCC[3:0] PMOS compensation cell code These bits define I/O compensation cell code for PMOS transistors. When CSEL bit of SYSCFG_CPSCTL is set, the I/O compensation cell will apply this code.
Page 90: Timer Input Selection Register 1 (Syscfg_Timercisel1)
GD32H737/757/759 User Manual These bits select the TIMER input source. 0000: TIMER7_CH3 input Others: Reserved 11:8 TIMER7_CI2_SEL[3: Selects TIMER7_CI2 input selection These bits select the TIMER input source. 0000: TIMER7_CH2 input Others: Reserved TIMER7_CI1_SEL[3: Selects TIMER7_CI1 input selection These bits select the TIMER input source.
Page 91: Timer Input Selection Register 2 (Syscfg_Timercisel2)
GD32H737/757/759 User Manual Others: Reserved 23:20 TIMER1_CI1_SEL[3: TIMER1_CI1 input selection These bits select the TIMER input source. 0000: TIMER1_CH1 input Others: Reserved 19:16 TIMER1_CI0_SEL[3: TIMER1_CI0 input selection These bits select the TIMER input source. 0000: TIMER1_CH0 input Others: Reserved 15:12...
Page 92: Timer Input Selection Register 3 (Syscfg_Timercisel3)
GD32H737/757/759 User Manual Bits Fields Descriptions 31:28 TIMER3_CI3_SEL[3: TIMER3_CI3 input selection These bits select the TIMER input source. 0000: TIMER3_CH3 input Others: Reserved 27:24 TIMER3_CI2_SEL[3: TIMER3_CI2 input selection These bits select the TIMER input source. 0000: TIMER3_CH2 input Others: Reserved...
Page 93 GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). TIMER22_CI3_SEL[3:0] TIMER22_CI2_SEL[3:0] TIMER22_CI1_SEL[3:0] TIMER22_CI0_SEL[3:0] TIMER23_CI3_SEL[3:0] TIMER23_CI2_SEL[3:0] TIMER23_CI1_SEL[3:0] TIMER23_CI0_SEL[3:0] Bits Fields Descriptions 31:28 TIMER22_CI3_SEL[3 TIMER22_CI3 input selection These bits select the TIMER input source. 0000: TIMER22_CH3 input 0001: CMP0 output...
Page 94: Timer Input Selection Register 4 (Syscfg_Timercisel4)
GD32H737/757/759 User Manual TIMER23_CI0_SEL[3 TIMER23_CI0 input selection These bits select the TIMER input source. 0000: TIMER23_CH0 input Others: Reserved Timer input selection register 4 (SYSCFG_TIMERCISEL4) 1.8.13. Address offset: 0x044 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 95: Timer Input Selection Register 5 (Syscfg_Timercisel5)
GD32H737/757/759 User Manual 11:8 TIMER31_CI2_SEL[3 TIMER31_CI2 input selection These bits select the TIMER input source. 0000: TIMER31_CH2 input Others: Reserved TIMER31_CI1_SEL[3 TIMER31_CI1 input selection These bits select the TIMER input source. 0000: TIMER31_CH1 input Others: Reserved TIMER31_CI0_SEL[3 TIMER31_CI0 input selection These bits select the TIMER input source.
Page 96 GD32H737/757/759 User Manual 0011: TIMER23_CH0 input 0100: LXTAL 0101: LPIRC4M 0110: CKOUT1 Others: Reserved 23:20 TIMER41_CI1_SEL[3 Selects TIMER41_CI1 input These bits select the TIMER input source. 0000: TIMER41_CH1 input 0001: TIMER3_CH1 input 0010: TIMER4_CH1 input 0011: TIMER22_CH1 input Others: Reserved...
Page 97: Timer Input Selection Register 6 (Syscfg_Timercisel6)
GD32H737/757/759 User Manual 0000: TIMER14_CH1 input 0001: TIMER1_CH1 input 0010: TIMER2_CH1 input 0011: TIMER3_CH1 input Others: Reserved TIMER14_CI0_SEL[3 Selects TIMER14_CI0 input These bits select the TIMER input source. 0000: TIMER14_CH0 input 0001: TIMER1_CH0 input 0010: TIMER2_CH0 input 0011: TIMER3_CH0 input...
Page 98: Cpu Icache Error Status Register(Syscfg_Cpuicac)
GD32H737/757/759 User Manual 0010: TIMER30_CH0 input 0011: TIMER31_CH0 input 0100: LXTAL 0101: LPIRC4M 0110: CKOUT1 Others: Reserved 15:12 TIMER43_CI1_SEL[3 Selects TIMER43_CI1 input These bits select the TIMER input source. 0000: TIMER43_CH1 input 0001: TIMER22_CH1 input 0010: TIMER23_CH1 input 0011: TIMER30_CH1 input...
Page 99: Cpu Dcache Error Status Register (Syscfg_Cpudcac)
GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). CPU_ICDET[3:0] CPU_ICERR[21:10] Reserved CPU_ICERR[9:0] Bits Fields Descriptions 31:28 CPU_ICDET[3:0] The ICACHE error detection information These bits are provided by the CPU to indicate the ICACHE error detection information.
Page 100: Sram Configuration Register 0 (Syscfg_Sramcfg0)
GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). Reserved Reserved IXIE IDIE OVFIE UFIE DZIE IOPIE Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. IXIE Inexact interrupt enable bit 0: Inexact interrupt disable...
Page 101: Sram Configuration Register 1 (Syscfg_Sramcfg1)
GD32H737/757/759 User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. SECURE_SRAM_SI Size of secure SRAM ZE[1:0] These bits are set and cleared by software. 00: 0 Kbytes 01: 32 Kbytes 10: 64 Kbytes 11: 128 Kbytes SRAM configuration register 1 (SYSCFG_SRAMCFG1) 1.8.20.
Page 102 GD32H737/757/759 User Manual Reserved TSCFG5[4:0] TSCFG4[4:0] TSCFG3[4:0] Reserved TSCFG2[4:0] TSCFG1[4:0] TSCFG0[4:0] Bits Fields Descriptions Reserved Must be kept at reset value. 30:26 TSCFG5[4:0] Event mode configuration A rising edge of the trigger input enables the counter. 00000: Event mode disable...
Page 103 GD32H737/757/759 User Manual 00111: The filtered output of channel 1 input (CI1FE1) 01000: The filtered output of external trigger input (ETIFP) 01001: The filtered output of channel 2 input (CI2FE2) 01010: The filtered output of channel 3 input (CI3FE3) 01011: The filtered output of multi mode channel 0 input (MCI0FEM0)
Page 104: Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=0, 7)
GD32H737/757/759 User Manual depends on each other TSCFG1[4:0] Quadrature decoder mode 1 configuration 00000: Quadrature decoder mode 1 disable Others: The counter counts on CI1FE1 edge, while the direction depends on CI0FE0 level TSCFG0[4:0] Quadrature decoder mode 0 configuration 00000: Quadrature decoder mode 0 disable Others: The counter counts on CI0FE0 edge, while the direction depends on CI1FE1 level.
Page 105 GD32H737/757/759 User Manual TSCFG7[4:0] Restart + event mode configuration The counter is reinitialized and started, the shadow registers are updated on the rising edge of the selected trigger input when these bits are not 0. 00000: Restart + event mode disable...
Page 106: Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=0, 7)
GD32H737/757/759 User Manual 10000: Reserved 10001: Internal trigger input 12 (ITI12) 10010: Internal trigger input 13 (ITI13) 10011: Internal trigger input 14 (ITI14) Others: Reserved TIMERx configuration register 2 (SYSCFG_TIMERxCFG2, x=0, 7) 1.8.23. Address offset: 0x108 for TIMER0 Address offset: 0x144 for TIMER7 Reset value: 0x0000 0000 TSCFG0[4:0], TSCFG1[4:0]..TSCFG9[4:0] are mutually exclusive and cannot be configured...
Page 107: Timerx Configuration Register 0 (Syscfg_Timerxcfg0, X=1, 2, 3, 4, 22, 23, 30, 31)
GD32H737/757/759 User Manual 10001: Internal trigger input 12 (ITI12) 10010: Internal trigger input 13 (ITI13) 10011: Internal trigger input 14 (ITI14) Others: Reserved Note: When TSCFG15[4:0] is used, TSCFGy[4:0](y=0..9) should be zero, otherwise, the ITS trigger cooperate with TSCFGy[4:0], and input source depend on TSCFGy[4:0].
Page 108 GD32H737/757/759 User Manual 00101: CI0 edge flag (CI0F_ED) 00110: The filtered output of channel 0 input (CI0FE0) 00111: The filtered output of channel 1 input (CI1FE1) 01000: The filtered output of external trigger input (ETIFP) 01001: Internal trigger input 4 (ITI4)
Page 109: Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=1, 2, 3, 4, 22, 23, 30, 31)
GD32H737/757/759 User Manual 00000: Restart mode disable 00001: Internal trigger input 0 (ITI0) 00010: Internal trigger input 1 (ITI1) 00011: Internal trigger input 2 (ITI2) 00100: Internal trigger input 3 (ITI3) 00101: CI0 edge flag (CI0F_ED) 00110: The filtered output of channel 0 input (CI0FE0)
Page 110 GD32H737/757/759 User Manual Address offset: 0x134 for TIMER4 Address offset: 0x158 for TIMER22 Address offset: 0x164 for TIMER23 Address offset: 0x170 for TIMER30 Address offset: 0x17C for TIMER31 Reset value: 0x0000 0000 TSCFG0[4:0], TSCFG1[4:0]..TSCFG9[4:0] are mutually exclusive and cannot be configured at the same time.
Page 111 GD32H737/757/759 User Manual 00111: The filtered output of channel 1 input (CI1FE1) 01000: The filtered output of external trigger input (ETIFP) 01001: Internal trigger input 4 (ITI4) 01010: Internal trigger input 5 (ITI5) 01011: Reserved 01100: Internal trigger input 7 (ITI7)
Page 112: Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=1, 2, 3, 4, 22, 23, 30, 31)
GD32H737/757/759 User Manual TIMERx configuration register 2 (SYSCFG_TIMERxCFG2, x=1, 2, 3, 4, 22, 1.8.26. 23, 30, 31) Address offset: 0x114 for TIMER1 Address offset: 0x120 for TIMER2 Address offset: 0x12C for TIMER3 Address offset: 0x138 for TIMER4 Address offset: 0x15C for TIMER22...
Page 113: Timerx Configuration Register 0 (Syscfg_Timerxcfg0, X=14, 40, 41, 42, 43, 44)
GD32H737/757/759 User Manual 10000: Internal trigger input 11 (ITI11) 10001: Internal trigger input 12 (ITI12) 10010: Internal trigger input 13 (ITI13) 10011: Internal trigger input 14 (ITI14) Others: Reserved Note: When TSCFG15[4:0] is used, TSCFGy[4:0](y=0..9) should be zero, otherwise, the ITS trigger cooperate with TSCFGy[4:0], and input source depend on TSCFGy[4:0].
Page 114 GD32H737/757/759 User Manual 00110: The filtered output of channel 0 input (CI0FE0) 00111: The filtered output of channel 1 input (CI1FE1) 01000: Reserved 01001: Reserved 01010: Reserved 01011: The filtered output of multi mode channel 0 input (MCI0FEM0) 10011: Internal trigger input 14 (ITI14)
Page 115: Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=14, 40, 41, 42, 43, 44)
GD32H737/757/759 User Manual 15:0 Reserved Must be kept at reset value. TIMERx configuration register 1 (SYSCFG_TIMERxCFG1, x=14, 40, 41, 1.8.28. 42, 43, 44) Address offset: 0x14C for TIMER14 Address offset: 0x188 for TIMER40 Address offset: 0x194 for TIMER41 Address offset: 0x1A0 for TIMER42...
Page 116: Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=14, 40, 41, 42, 43, 44)
GD32H737/757/759 User Manual Others: Reserved TSCFG6[4:0] External clock mode 0 configuration The counter counts on the rising edges of the selected trigger when these bits are not 0. 00000: External clock mode 0 disable 00001: Internal trigger input 0 (ITI0)
Page 117: User Configuration Register (Syscfg_Usercfg)
GD32H737/757/759 User Manual 31:21 Reserved Must be kept at reset value. 20:16 TSCFG15[4:0] Internal trigger input source configuration 00000: Reserved 00001: Internal trigger input 0 (ITI0) 00010: Internal trigger input 1 (ITI1) 00011: Internal trigger input 2 (ITI2) 00100: Internal trigger input 3 (ITI3)
Page 118: Axi Interconnect Registers
GD32H737/757/759 User Manual Others: Reserved Reserved Must be kept at reset value. BOR_TH[1:0] BOR threshold status bits 00: BOR threshold value 3 01: BOR threshold value 2 10: BOR threshold value 1 11: No BOR function 1.9. AXI interconnect registers...
Page 119: Axi Peripheral Id1 Register (Axi_Periph_Id1)
GD32H737/757/759 User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. PARTNUM[7:0] Part number[7:0] AXI peripheral ID1 register (AXI_PERIPH_ID1) 1.9.3. Address offset: 0x1FE4 Reset value: 0x0000 00B4 This register has to be accessed by word (32-bit). Reserved...
Page 120: Axi Peripheral Id3 Register (Axi_Periph_Id3)
GD32H737/757/759 User Manual JEP106CF JEP106 code flag JEP106ID[6:4] Part number[6:4] AXI peripheral ID3 register (AXI_PERIPH_ID3) 1.9.5. Address offset: 0x1FEC Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CUSTREV[3:0] CUSTMOD[11:8] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 121: Axi Componet Id2 Register (Axi_Comp_Id2)
GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). Reserved Reserved CLASS[3:0] PREAMB[11:8] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CLASS[3:0] Component class PARTNUM[11:8] Preamble bits AXI componet ID2 register (AXI_COMP_ID2) 1.9.8. Address offset: 0x1FF8 Reset value: 0x0000 0005 This register has to be accessed by word (32-bit).
Page 122: Axi Master Port X Bus Matrix Issuing Functionality Control Register (Axi_Mpxbm_Iss_Ctl)
GD32H737/757/759 User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. PREAMB[27:20] Preamble bits AXI Master Port x bus matrix issuing functionality control register 1.9.10. (AXI_MPxBM_ISS_CTL) Address offset: 0x2008 + 0x1000 * x, where x = 0 to 7 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 123: Axi Master Port X Long Burst Functionality Control Register (Axi_Mpx_Lb_Ctl)
GD32H737/757/759 User Manual Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. BPDIS Beats packing function disable configure 0: Normal operation 1: Disable beats packing function Master Port long burst functionality control register 1.9.12. (AXI_MPx_LB_CTL) Address offset: 0x202C + 0x1000 * x, where x = 0 and 1 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 124: Axi Slave Port X Functionality Control Register (Axi_Spx_Ctl)
GD32H737/757/759 User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. WR_ISSOV Override AMIB write issuing function 0: Normal issuing function 1: The AMIB write issuing capability is forced set to 1 RD_ISSOV Override AMIB read issuing function...
Page 125: Axi Slave Port X Read Qos Control Register (Axi_Spx_Rdqos_Ctl)
GD32H737/757/759 User Manual RD_AHB_I WR_AHB_ Reserved SSOV ISSOV Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. RD_AHB_ISSOV Converts AHB-Lite read transaction to single beat AXI transaction function 0: Override disabled 1: Override enabled WR_AHB_ISSOV Converts AHB-Lite write transaction to single beat AXI transaction function...
Page 126: Axi Slave Port X Issuing Functionality Control Register (Axi_Spx_Iss_Ctl)
GD32H737/757/759 User Manual Reserved WRQOS[3:0] Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. WRQOS[3:0] Write channel QoS configure 0000: Lowest priority … 1111: Highest priority Slave Port issuing functionality control register 1.9.18. (AXI_SPx_ISS_CTL) Address offset: 0x42108 + 0x1000 * x, where x = 0 to 5 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 127: Memory Density Information
GD32H737/757/759 User Manual Memory density information 1.10.1. Base address: 0x1FF0 F7E0 The value is factory programmed and can never be altered by user. FLASH_DENSITY[15:0] SRAM_DENSITY[15:0] Bits Fields Descriptions 31:16 FLASH_DENSITY Flash memory density [15:0] The value indicates the Flash memory density of the device in Kbytes.
Page 128 GD32H737/757/759 User Manual UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FF0 F7F0 The value is factory programmed and can never be altered by user. UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID...
Page 129: Ram Ecc Monitor Unit (Rameccmu)
GD32H737/757/759 User Manual RAM ECC monitor unit (RAMECCMU) The GD32H7xx device features two RAM ECC monitor units (RAMECCMU) in Region 0 and Region1 separately. It provides a method to verify ECC status for applications and execute error handling when errors occur.
Page 130: Table 2-1. Ramecc Monitor X Unit For Region 0 (X=0
GD32H737/757/759 User Manual Table 2-1. RAMECC monitor x unit for Region 0 (x=0..4) RAMECC monitor RAMECC monitor status number AXI SRAM ECC ITCM-RAM ECC DTCM-RAM ECC(D0TCM) DTCM-RAM ECC(D1TCM) RAM shared(ITCM/DTCM/AXI SRAM) ECC Table 2-2. RAMECC monitor x unit for Region 1 (x=0..2)
Page 131: Register Definition
GD32H737/757/759 User Manual 2.3. Register definition RAMECCMU Region 0 base address: 0x5200 9000 RAMECCMU Region 1 base address: 0x4802 3000 RAMECCMU global interruput register (RAMECCMU_INT) 2.3.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 132: Rameccmu Monitor X Status Register (Rameccmu_Mxstat)
GD32H737/757/759 User Manual for Region 1) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ECCERRL ECCDER ECCDER ECCSERR Reserved Reserved ATEN RBWIE Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. ECCERRLATEN...
Page 133: Rameccmu Monitor X Failing Address Register (Rameccmu_Mxfaddr)
GD32H737/757/759 User Manual rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. ECCDERRBWDF ECC double error on byte write detected flag This bit is set by hardware and cleared by writing 0. 0: Double error is detected during read when ECCDERRDF is set...
Page 134: Rameccmu Monitor X Failing Data Low Register (Rameccmu_Mxfdl)
GD32H737/757/759 User Manual RAMECCMU monitor x failing data low register (RAMECCMU_MxFDL) 2.3.5. Address offset: 0x2C + 0x20 * x, (x= ECC monitoring number, x=0..4 for Region 0, while x=0..2 for Region 1) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 135 GD32H737/757/759 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). ECCFECODE[31:16] ECCFECODE[15:0] Bits Fields Descriptions 31:0 ECCFECODE[31:0] ECC failing error code This register contains the index where the bit error occurs and the ECC code.
Page 136: Flash Memory Controller (Fmc)
GD32H737/757/759 User Manual Flash memory controller (FMC) 3.1. Overview The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. It also provides sector erase, mass erase, program operations for flash memory. 3.2. Characteristics  Up to 3840KB of on-chip flash memory for instruction and data.
Page 137: Read Operations
GD32H737/757/759 User Manual  Flash memory single read operations supporting 1,2,4,8-byte.  Flash memory incrementing burst read operations supporting size 1,2,4,8-byte; burst length up to 128 bytes.  Flash memory wrapped burst read operations supporting size 8-byte with 1,2,4,8-beat. ...
Page 138: Unlock The Fmc_Ctl And Fmc_Obctl Register
GD32H737/757/759 User Manual initialization vector AES_IV[127:0] = AESIV[95:0] || 12'b0 || ReadAddress[23:4]. User can modify the high 96 bits of the initial vector (AESIV[95:0]) by modifying the FMC_AESIVx_MDF register. The AESIV[95:0] is formed with [AESIV2, AESIV1,AESIV0]. When the initial vector needs to be modified, user must write the FMC_ASIV0_MDF, FMC_ASIV1_MDF, and FMC_ASIV2_MDF registers in sequence.
Page 139: Sector Erase
GD32H737/757/759 User Manual Sector erase 3.3.4. The FMC provides a sector erase function which is used to initialize the contents of a main flash block sector to a high state. Each sector can be erased independently without affecting the contents of other sectors. The following steps show the access sequence of the registers for a sector erase operation.
Page 140: Mass Erase
GD32H737/757/759 User Manual Start Unlock the Is the LK bit is 0 FMC_CTL Is the BUSY bit is 0 Set the SER bit, Write ADDR bits Send the command to FMC by set START bit Is the BUSY bit is 0...
Page 141: Figure 3-3. Process Of Typical Mass Erase Operation
GD32H737/757/759 User Manual Wait until all the operations have been finished by checking the value of the BUSY bit in FMC_STAT register. Read and verify the flash memory if required. If mass erase and sector erase is request at the same time, the mass erase operation will replace the sector erase operation.
Page 142: Figure 3-4. Process Of Protection-Removed Mass Erase Operation
GD32H737/757/759 User Manual Protection-removed mass erase The FMC provides a protection-removed mass erase function which is used to erase all sectors include sectors contain secure user or protected data. This erase can affect by setting the MER bit to 1 in the FMC_CTL register. The following steps show the protection-removed mass erase register access sequence.
Page 143 GD32H737/757/759 User Manual Start Unlock the Is the OBLK bit is 0 FMC_OBCTL Set DCRP_EREN bit, and modify DCRP area start/end address to make Is DCRP area exist DCRP_AREA_END < DCRP_AREA_START Set SCR_EREN bit, and modify secure user Is secure user...
Page 144: Main Flash Programming
GD32H737/757/759 User Manual Main flash Programming 3.3.6. The FMC provides a 64-bit/32-bit programming function by AXI interface which is used to modify the main flash block contents. The following steps show the register access sequence of the word programming operation.
Page 145: Option Bytes
GD32H737/757/759 User Manual Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PG bit Perform write Is the BUSY bit is 0 Finish Note: When programming, erasing, especially the mass erasing, abnormal power off or reset should be avoided as far as possible, otherwise unpredictable consequences may occur.
Page 146: Table 3-2. Option Byte
GD32H737/757/759 User Manual The option bytes block is reloaded to "_EFT" registers after each system reset, and the option Table 3-2. Option byte.The bytes take effect. The option bytes description is shown in the option bytes are configured according to the requirements of the application.
Page 147 GD32H737/757/759 User Manual Launch a system reset to start option bytes loading. Read from FMC_XXX_EFT register and verify the option bytes if required. Note: “XXX” includes OBSTAT0, DCRPADDR, SCRADDR, WP, BTADDR or OBSTAT1. When the operation is executed successfully, the ENDF in FMC_STAT register is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set.
Page 148: Sector Erase/Program Protection
GD32H737/757/759 User Manual level low to no protection demotion or a protection-removed mass erase. Otherwise will be preserved. The DCRP_EREN bit can be set without any restriction. The DCRP_EREN bit can be reset only when the SPC level low to no protection demotion or a protection-removed mass erase is requested simultaneously.
Page 149: Security Protection
GD32H737/757/759 User Manual FMC on protected sectors. If the sector erase or program command is sent to the FMC on a protected sector, the WPERR bit in the FMC_STAT register will then be set by the FMC. Note that the WPERR also set when sector erase while MER set or sector address not valid. The sector protection function can be individually enabled by configuring the WP[21:0] bit field to 0 in the option bytes.
Page 150 GD32H737/757/759 User Manual No protection When setting SPC[7:0] bits in FMC_OBSTAT0_EFT to 0xAA, no protection performed. The main flash and option bytes block are accessible by all operations. And access to other secured regions is also allowed. Protection level low When SPC_H in eFuse is 0, as long as setting SPC_L to 1 or SPC[7:0] option bits to any value except 0xAA or 0xCC, protection level low performed.
Page 151: Dedicated Code Read Protection Area
GD32H737/757/759 User Manual The JTAG port is always disabled when level high is active. Therefore, it is impossible to debug and analyze the defective parts with level high security protection. If security protection level high is set while the debugger is still connected, apply a power on reset.
Page 152: Table 3-5. Dcrp Area Configuration
GD32H737/757/759 User Manual configured by setting the same value to the start and end addresses of the DCRP area. When executing code in this area, the debug events will be ignored. Only CPU can access DCRP area, using only instruction fetch transactions. In all other cases, access to the DCRP area is illegal.
Page 153: Secure User Area
GD32H737/757/759 User Manual area in efuse should be both set to 0, and the DCRPLK bit in efuse should be set to 1, otherwise there may be vulnerability in the DCRP area. (2) If the user has security considerations, please configure the DCRP area by efuse, otherwise there may be security risks.
Page 154: Secure Mode
GD32H737/757/759 User Manual protection-removed mass erase. Only CPU can modify the secure user area definition bits and SCR_EREN bit. If secure user area is valid ( not empty ), during the SPC level low to no protection demotion, if the...
Page 155: Figure 3-6. Secure Access Mode
GD32H737/757/759 User Manual attacks. For example, licensed firmware update software requires highly protection because it processes confidential data ( such as encryption keys ) that cannot get by other processes. Secure areas with limited access is provided. In this area, secure services can be built that can be executed before any user application.
Page 156: Basic Security Service
GD32H737/757/759 User Manual modify rules of the relevant option bytes. Note: If user has security considerations, please configure the secure mode by efuse, otherwise there may be security risks. Basic security service 3.3.13. BSS provides the secure area setting function and secure area exiting function.
Page 157: Error Description
GD32H737/757/759 User Manual Precondition The called functions Input parameter{in} address of application vector to jump after exit secure user area. vectors Input parameter{in} jtag_state status of the JTAG after exit secure user area. BSS_EXIT_SCR_JTAG enable the JTAG after exiting _ENABLE...
Page 158 GD32H737/757/759 User Manual Program sequence error (PGSERR) The following operation will set the PGSERR in the FMC_STAT register, and the current program operation is aborted:  When a program operation is requested but the program enable bit (PG) has not been...
Page 159: Fmc Interrupts
GD32H737/757/759 User Manual  Access address out of range.  Any wrong sequence to unlock the FMC_CTL or FMC_OBCTL register. FMC interrupts 3.3.15. The FMC interrupt events and flags are listed in Table 3-9 FMC interrupt requests. Table 3-9 FMC interrupt requests...
Page 160: Register Definition
GD32H737/757/759 User Manual 3.4. Register definition FMC base address: 0x5200 2000 Unlock key register (FMC_KEY) 3.4.1. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). KEY[31:16] KEY[15:0] Bits Fields Descriptions 31:0 KEY[31:0] FMC_CTL unlock register These bits are only be written by software.
Page 161 GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). Reserved RSERRIE RPERRIE Reserved PGSERRIE WPERRIE ENDIE Reserved START Reserved PGCHEN Bits Fields Descriptions 31:25 Reserved Must be kept at reset value. RSERRIE Read secure error interrupt enable.
Page 162: Status Register (Fmc_Stat)
GD32H737/757/759 User Manual 0: Disable check whether the programming area is all 0xFF before programming. 1: Enable check whether the programming area is all 0xFF before programming. If this bit is set, and the programming area is not all 0xFF, PGSERR flag is set. And the program operation is invalid.
Page 163: Address Register (Fmc_Addr)
GD32H737/757/759 User Manual This bit is set by hardware. The software can clear it by writing 1. 0: Disable option byte modify error 1: Enable option byte modify error 29:25 Reserved Must be kept at reset value. RSERR Read secure error flag bit.
Page 164: Option Byte Control Register (Fmc_Obctl)
GD32H737/757/759 User Manual ADDR[31:16] ADDR[15:0] Bits Fields Descriptions 31:0 ADDR[31:0] Flash erase command address bits These bits are configured by software. ADDR bits are the address of flash to be erased. Option byte control register (FMC_OBCTL) 3.4.6. Address offset: 0x18 Reset value: 0x0000 0001 This register has to be accessed by word (32-bit).
Page 165: Option Byte Status Register 0 (Fmc_Obstat0_Eft)
GD32H737/757/759 User Manual Option byte status register 0 (FMC_OBSTAT0_EFT) 3.4.7. Address offset: 0x1C Reset value: 0xXXXX XXXX. Factory value is 0x01C6 AAD0 This register is the effective values of corresponding option bits. Load flash values after reset. This register has to be accessed by word (32-bit).
Page 166: Option Byte Status Register 0 (Fmc_Obstat0_Mdf)
GD32H737/757/759 User Manual 0: FWDGT is suspend in system deepsleep mode 1: FWDGT is running in system deepsleep mode. Reserved Must be kept at reset value. 15:8 SPC[7:0] Security protection level option byte status bits 0xAA: No protection 0xCC: Protection level high Any value except 0xAA or 0xCC: Protection level low.
Page 167 GD32H737/757/759 User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. IOSPDOPEN Allowed enable configuration bit for I/O speed optimization at low-voltage. 0: Chip operating voltage greater than 2.5V, so I/O speed optimization is not allowed 1: Chip operating voltage is less than 2.5V, so I/O speed optimization is allowed...
Page 168: Dcrp Address Register (Fmc_Dcrpaddr_Eft)
GD32H737/757/759 User Manual 1: No reset when entering deep-sleep mode Reserved Must be kept at reset value. nWDG_HW Watchdog configuration bit 0: Hardware free watchdog 1: Software free watchdog BOR_TH[1:0] BOR threshold configuration bits 00: No BOR function 01: BOR threshold value 1...
Page 169: Dcrp Address Register (Fmc_Dcrpaddr_Mdf)
GD32H737/757/759 User Manual 15:11 Reserved Must be kept at reset value. 10:0 DCRP_AREA_STAR DCRP area start address status bits T[10:0] These bits contain the first 4K-byte block of the DCRP area. Start absolute address = DCRP_AREA_START[10:0] * 4096 + 0x0800_0000.
Page 170: Secure Address Register (Fmc_Scraddr_Eft)
GD32H737/757/759 User Manual whole main flash block. If DCRP_AREA_END[10:0] < DCRP_AREA_START[10:0], protection is invalid. Secure address register (FMC_SCRADDR_EFT) 3.4.11. Address offset: 0x30 Reset value: 0xXXXX 0XXX. Factory value is 0x0000 00FF This register is the effective values of corresponding option bits. Load flash values after reset This register has to be accessed by word (32-bit).
Page 171: Erase/Program Protection Register (Fmc_Wp_Eft)
GD32H737/757/759 User Manual Reset value: 0xXXXX 0XXX This register is used for modifying values to corresponding option bits. Values after reset is the effective values of the corresponding option bits. This register has to be accessed by word (32-bit). SCR_ER...
Page 172: Erase/Program Protection Register (Fmc_Wp_Mdf)
GD32H737/757/759 User Manual Reserved WP[21:16] WP[15:0] Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. 21:0 WP[21:0] Sector erase/program protection option status bit In WP[21], each bit reflects the corresponding 64 sectors to erase/program protection status. 0: corresponding 64 sectors are erase/program protected.
Page 173: Boot Address Register (Fmc_Btaddr_Eft)
GD32H737/757/759 User Manual 0: set corresponding 64 sectors to erase/program protected. 1: set corresponding 64 sectors to not erase/program protected. In WP[20:16], each bit can set the corresponding 128 sectors to erase/program protection status. 0: set corresponding 128 sectors to erase/program protected.
Page 174: Option Byte Status Register 1 (Fmc_Obstat1_Eft)
GD32H737/757/759 User Manual BOOT_ADDR0[15:0] Bits Fields Descriptions 31:16 BOOT_ADDR1[15:0] Boot address 1 configuration bits. Configure the MSB of boot address if the BOOT pin is high. 15:0 BOOT_ADDR0[15:0] Boot address 0 configuration bits. Configure the MSB of the boot address if the BOOT pin is low.
Page 175: Option Byte Status Register 1 (Fmc_Obstat1_Mdf)
GD32H737/757/759 User Manual 1000: 128-Kbyte ITCM 1001: 256-Kbyte ITCM 1010: 512-Kbyte ITCM 1011~1111: Reserved Option byte status register 1 (FMC_OBSTAT1_MDF) 3.4.18. Address offset: 0x54 Reset value: 0xXXXX 0XXX. This register is used for modifying values to corresponding option bits. Values after reset is the effective values of the corresponding option bits.
Page 176: Rtdec Area Register (Fmc_Nodec)
GD32H737/757/759 User Manual NO-RTDEC area register (FMC_NODEC) 3.4.19. Address offset: 0x60 Reset value: 0x0000 00FF This register has to be accessed by word (32-bit) only when LK is set to 0. Reserved NODEC_AREA_END[10:0] Reserved NODEC_AREA_START[10:0] Bits Fields Descriptions 31:27 Reserved Must be kept at reset value.
Page 177: Aes Iv Register (Fmc_Aesivx_Mdf) (X = 0
GD32H737/757/759 User Manual AESIV[31:16] AESIV[15:0] Bits Fields Descriptions 31:0 AESIV[31:0] AES initialization vector status value The initialization vector AES_IV[127:0] = AESIV[95:0] || 12'b0 || ReadAddress[23:4]. The 96 bits AESIV[95:0] is formed with [AESIV2, AESIV1, AESIV0]. AES IV register (FMC_AESIVx_MDF) (x = 0…2) 3.4.21.
Page 178 GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). PID[31:16] PID[15:0] Bits Fields Descriptions 31:0 PID[31:0] Product reserved ID code register x These bits are read only by software. These bits are unchanged constant after power on. These bits are one time program...
Page 179: Electronic Fuse (Efuse)
GD32H737/757/759 User Manual Electronic fuse (EFUSE) 4.1. Overview The efuse controller has efuse macro that store system parameters. As a non-volatile unit of storage, the bit of efuse macro cannot be restored to 0 once it is programmed to 1.
Page 180: Efuse Macro Description
GD32H737/757/759 User Manual Efuse adopts the double-bit redundant backup mechanism. The first 512 bits data and the last 512 bits data are backed up with each other to effectively ensure the correctness of the data.When programming the Nth bit of the efuse, the efuse controller will program both the Nth and (N+512)th bit.
Page 181 GD32H737/757/759 User Manual Read operation system reset or a efuse to load the parameter from efuse macro into the register and this newly modified Debug password parameter takes effect only after the system is reset.  AES key parameter: The parameter stored in efuse macro can be modified multiple times, but once the bit...
Page 182: Table 4-1. System Parameters
GD32H737/757/759 User Manual Note: User must continuously write the complete 16 bytes AES key into the EFUSE_AES_KEYx register to ensure that the CRC function can check the contents of all AES key.  User data parameter The register can be read without restriction. After system reset, the register will be restored to the value of parameter which is read out from efuse.
Page 183: Read Operation
GD32H737/757/759 User Manual Param Width/ Start Program- Read-protected Description eter bytes address protected correctness of the written Firmware AES key regi AES key by AES key CRC ster x (EFUSE_AES_KE 0…3) function. Yx) (x = After system reset, register will be restored to the value of parameter which is User defined data.
Page 184: Program Operation
GD32H737/757/759 User Manual Note: Efuse is very sensitive to current surges which will affect the result of read operation. It is strictly prohibited to perform read operation during the sequence of power-up or power- down, otherwise it will cause unpredictable consequences.
Page 185: Efuse Interrupts
GD32H737/757/759 User Manual When the AES key stored in efuse macro is read out after system reset, the hardware CRC module will automatically calculate the corresponding AES key CRC checking code based on the AES key value stored in efuse macro and store the calculation result to the AES_KEY_CRC bit field in the EFUSE_CTL register.
Page 186: Figure 4-2 Efuse Interrupt Mapping Diagram
GD32H737/757/759 User Manual Figure 4-2 EFUSE interrupt mapping diagram PVIF PVIE PGIF PGIE EFUSE_INT RDIF RDIE IAERRIF IAERRIE...
Page 187: Register Definition
GD32H737/757/759 User Manual 4.4. Register definition EFUSE base address: 0x4002 2800 Control register (EFUSE_CTL) 4.4.1. Address offset: 0x00 Reset value: 0x7E00 0000 This register has to be accessed by word (32-bit). AES_KEY_CRC Reserved PVIE RDIE PGIE IAERRIE MPVEN Reserved EFRW...
Page 188: Address Register (Efuse_Addr)
GD32H737/757/759 User Manual IAERRIE Illegal access error interrupt enable 0: Disable the illegal access error interrupt 1: Enable the illegal access error interrupt This bit cannot be modified when the EFSTR bit in EFUSE_CTL register is 1 MPVEN Monitor program voltage function enable...
Page 189: Status Register (Efuse_Stat)
GD32H737/757/759 User Manual Status register (EFUSE_STAT) 4.4.3. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved LDO_RDY PVIF RDIF PGIF IAERRIF Bits Fields Descriptions 31:5 Reserved Must be kept at reset value.
Page 190: User Control Register (Efuse_User_Ctl)
GD32H737/757/759 User Manual Reserved Reserved PVIC RDIC PGIC IAERRIC rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. PVIC Clear bit for program voltage setting error interrupt flag 0: No effect 1: Clear error flag...
Page 191 GD32H737/757/759 User Manual 31:24 SCR_AREA_END[7: Secure user area end address bits These bits contain the last 32K-byte block of the secure user area. The secure user area can be defined by efuse with a granularity of 32 Kbytes. End absolute address = ( SCR_AREA_END[7:0] + 1) * 32768 - 1 + 0x0800_0000.
Page 192: Mcu Reserved Register (Efuse_Mcu_Rsv)
GD32H737/757/759 User Manual 00: Normal JTAG ( only valid when JTAGNSW bit is 1, otherwise SW debugger is selected ) 01: Secure JTAG ( only valid when JTAGNSW bit is 1, otherwise SW debugger is selected ) 10~11: No debug ( debug function is closed regardless of the JTAGNSW bit ) Reserved Must be kept at reset value.
Page 193 GD32H737/757/759 User Manual user only when MCURSVLK bit is 0. But the modified value of all bits in this register will not be stored in efuse macro, unless a efuse program operation are executed successfully. This register has to be accessed by word (32-bit).
Page 194: Debug Password Register X (Efuse_Dpx) (X = 0,1)
GD32H737/757/759 User Manual 1: Lock the low 16 bits of EFUSE_MCU_RSV register, the bits can not be modified If the MCURSVLK bit is 1, other lock bits in EFUSE_MCU_RSV register cannot be modified, so user should be careful when set MCURSVLK bit.
Page 195: Firmware Aes Key Register X (Efuse_Aes_Keyx) (X = 0
GD32H737/757/759 User Manual 31:0 DPx[31:0] Efuse debug password value. Firmware AES key register x (EFUSE_AES_KEYx) (x = 0…3) 4.4.8. Address offset: 0x24 + 0x4 * x Reset value: 0x0000 0000 This register cannot be read. This register can be written only when AESEN is 0. But the modified value of register will not be stored in efuse macro, unless a efuse program operation are executed successfully.
Page 196: Power Management Unit (Pmu)
GD32H737/757/759 User Manual Power management unit (PMU) 5.1. Overview The power consumption is regarded as one of the most important issues for the devices of GD32H7xx series. The Power management unit (PMU) provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 197: Function Overview
GD32H737/757/759 User Manual 5.3. Function overview provides details on the internal configuration of the PMU Figure 5-1. Power supply overview and the relevant power domains. Figure 5-1. Power supply overview DDSMPS LXSMPS SMPS FBSMPS SSSMPS Backup Domain Power Switch 3.3V...
Page 198 GD32H737/757/759 User Manual internal power switch, and the V pin which drives Backup domain, supplies power for RTC unit, LXTAL oscillator, BPOR and BREG, and three BKP PADs, including PC13 to PC15. In order to ensure the content of the Backup domain registers and the RTC supply, when V...
Page 199: Vdd / V Dda
GD32H737/757/759 User Manual Backup domain voltage thresholds There is an internal power switch, which can select the voltage source of Backup domain V or V The supply voltage for Backup domain (V ) can be monitored with a top voltage and...
Page 200: Figure 5-3. Waveform Of The Por / Pdr
GD32H737/757/759 User Manual signal which resets the whole chip except the Backup domain when the supply voltage is lower than the specified threshold. shows the Figure 5-3. Waveform of the POR / PDR relationship between the supply voltage and the power reset signal. V...
Page 201: Figure 5-5. Waveform Of The Lvd Threshold
GD32H737/757/759 User Manual Figure 5-4. Waveform of the BOR 100mV hyst BOR Reset (Active Low) domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL0). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in PMU_CS, indicates if V higher or lower than the LVD threshold.
Page 202: Figure 5-6. Waveform Of The Vavd Threshold
GD32H737/757/759 User Manual Generally, digital circuits are powered by V , while most of analog circuits are powered by . To improve the ADC and DAC conversion accuracy, the independent power supply V is implemented to achieve better performance of analog circuits. V...
Page 203: 0.9V Power Domain
GD32H737/757/759 User Manual threshold. The temperature voltage thresholds can be enabled / disabled via VBTMEN bit in PMU_CTL1. When enabled, the temperature thresholds increase power consumption. As an example the levels could be used to trigger a routine to perform temperature control tasks.
Page 204: Figure 5-8. Ldo Supplies For 0.9V Power Domain
GD32H737/757/759 User Manual 0b1, LDO is on, and power supplies for 0.9V power domain, the power supplies voltage is controlled by LDOVS[2:0] bits field; BYPASS bit is 0b0, 0.9V power domain is not powered by V (external Power supplies directly).
Page 205: Figure 5-10. Smps Supplies For Ldo, Ldo Supplies For 0.9V Power Domain
GD32H737/757/759 User Manual Figure 5-9. SMPS supplies for 0.9V power domain DDLDO DDSMPS SMPS LXSMPS (off) SSLDO (on) FBSMPS SSSMPS 0.9V DVSEN CORE DVSCFG LDOEN BYPASS SMPS supply  SMPS power supplies LDO, LDO power supplies V mode: 0.9V The configuration method to enter this mode is that the DVSEN bit is 0b1, DVSCFG bit is 0b0, and the values of DVSVC[1:0] bits are 0b01 / 0b10 / 0b11.
Page 206: Figure 5-11. Smps Supplies For Ldo And External, Ldo Supplies For 0.9V Power Domain
GD32H737/757/759 User Manual consumption mode of the system; the BYPASS bit is 0b0, and the 0.9V power domain is not powered through V (external direct power supplies). Figure 5-11. SMPS supplies for CORE shows this power supplies mode. LDO and external, LDO supplies for 0.9V power domain Figure 5-11.
Page 207: Figure 5-13. Bypass
GD32H737/757/759 User Manual Figure 5-13. Bypass Note: In addition to the above valid combinations, other DVSEN, DVSCFG, DVSVC[1:0], LDOEN, BYPASS bits or bit field configuration combinations are invalid. The power supplies state of the 0.9V power domain will remain the state after reset (no configure the power supplies mode).
Page 208: Power Saving Modes
GD32H737/757/759 User Manual Power saving modes 5.3.4. After a system reset or a power reset, the GD32H7xx MCU operates at full function and all power domains are active. Users can achieve lower power consumption through slowing down the system clocks (HCLK, PCLK1, and PCLK2) or gating the clocks of the unused peripherals or configuring the LDO output voltage by LDOVS[2:0] bits in PMU_CTL3 register.
Page 209: Table 5-1. Power Saving Mode Summary
GD32H737/757/759 User Manual Standby mode The Standby mode is based on the SLEEPDEEP mode of the Cortex ® -M7, too. In Standby mode, the whole 0.9V domain is power off, the LDO is shut down, and all of IRC4M, IRC64M, HXTAL and PLLs are disabled.
Page 210: Register Definition
GD32H737/757/759 User Manual 5.4. Register definition PMU base address: 0x5800 5800 Control register 0 (PMU_CTL0) 5.4.1. Address offset: 0x00 Reset value: 0x0000 8000 (reset by wakeup from Standby mode) This register can be accessed by word (32-bit). VOVDEN Reserved VAVDVC[1:0]...
Page 211: Control And Status Register (Pmu_Cs)
GD32H737/757/759 User Manual 13:9 Reserved Must be kept at reset value. BKPWEN Backup domain write enable bit This bit is set and cleared by software. 0: Disable write access to the registers in backup domain 1: Enable write access to the registers in backup domain After reset, any write access to the registers in Backup domain is ignored.
Page 212 GD32H737/757/759 User Manual Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) This register can be accessed by word (32-bit). Reserved VOVDF Reserved VAVDF Reserved WUPEN5 Reserved WUPEN3 Reserved WUPEN1 WUPEN0 Reserved LVDF STBF Bits Fields Descriptions 31:21 Reserved Must be kept at reset value.
Page 213: Control Register 1 (Pmu_Ctl1)
GD32H737/757/759 User Manual 0: Disable WKUP pin1 function 1: Enable WKUP pin1 function If WUPEN1 is set before entering the power saving mode, a rising edge on the WKUP pin1 wakes up the system from the power saving mode. As the WKUP pin1 is active high, the WKUP pin1 is internally configured to input pull down mode.
Page 214 GD32H737/757/759 User Manual BKPVS Reserved VBTMEN Reserved Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. TEMPHF Temperature level monitoring versus high threshold 0: Temperature below high threshold level. 1: Temperature equal or above high threshold level. TEMPLF Temperature level monitoring versus low threshold 0: Temperature above low threshold level.
Page 215: Control Register 2 (Pmu_Ctl2)
GD32H737/757/759 User Manual modes. If BREN is set, the application must wait till the backup voltage stabilizer ready flag (BKPVSRF) is set. Which indicate that the data written into the SRAM will be maintained in Standby and V modes. 0: Backup voltage stabilizer disabled.
Page 216: Control Register 3 (Pmu_Ctl3)
GD32H737/757/759 User Manual 15:10 Reserved Must be kept at reset value. VCRSEL battery charging resistor selection 0: 5kOhms resistor is selected for charing V battery. 1: 1.5kOhms resistor is selected for charing V battery. VCEN battery charging enable 0: Disable V battery charging.
Page 217: Parameter Register (Pmu_Par)
GD32H737/757/759 User Manual Reserved LDOVS[2:0] Reserved Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. VOVRF voltage ready bit 0.9V This bit is set by hardware to indicate that the V supply is ready. 0.9V 0: V supply not ready 0.9V...
Page 218 GD32H737/757/759 User Manual 31:21 Reserved Must be kept at reset value. When enter Deep-sleep, switch to LPIRC4M / IRC64M (confirmed by 20:16 TSW_IRCCNT[4:0] DSPWUSSEL) clock. Wait the LPIRC4M / IRC64M (confirmed by DSPWUSSEL) counter and then set stop_state signal. The default is 10 clocks.
Page 219: Reset And Clock Unit (Rcu)
GD32H737/757/759 User Manual Reset and clock unit (RCU) 6.1. Reset control unit (RCTL) Overview 6.1.1. GD32H7xx reset control unit includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain.
Page 220: Clock Control Unit (Cctl)
GD32H737/757/759 User Manual source (external or internal reset). Figure 6-1. The system reset circuit NRST Filter POWER_RSTn WWDGT_RSTn min 20 us pulse System Reset FWDGT_RSTn generator SW_RSTn OB_STDBY_RSTn OB_DPSLP_RSTn Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the Backup domain control register or backup domain power on reset (VDD or VBAT power on, if both supplies have previously been powered off).
Page 221: Figure 6-2. Clock Tree
GD32H737/757/759 User Manual Figure 6-2. Clock tree RTCDIV[5:0] FCLK CK_HXTAL /2 to /63 (free running clock) CK_CST CK_RTC ÷ 2 32.768 KHz (to Cortex-M7 SysTick) LXTAL OSC (to RTC) RTCSRC[1:0] CK_FWDGT CK_DAC 32 KHz 300 MHz max IRC32K ACLK (to FWDGT)
Page 222 GD32H737/757/759 User Manual LPDTS block diagram. (2). The CK_PER is peripheral clock which is clocked by CK_IRC64MDIV, CK_LPIRC4M or CK_HXTAL. (3). The CK_TPIU is Trace Port Interface Unit (TPIU) clock which is clocked by CK_IRC64MDIV, CK_HXTAL, CK_LPIRC4M or CK_PLL0R. (4). The CK_RSPDIF_SYMB is RSPDIF channel symbol clock, refer to Figure 33-1.
Page 223 GD32H737/757/759 User Manual The SPI5(I2S5) is clocked by the clock of CK_APB2, CK_PLL1Q, CK_PLL2Q, CK_IRC64MDIV, CK_LPIRC4M, CK_HXTAL or I2S_CKIN which defined by SPI5SEL bits in RCU_CFG5 register. The SPI5 / I2S5 supports clock switch dynamically. The OSPI is clocked by the clock of CK_AHB.
Page 224: Characteristics
GD32H737/757/759 User Manual The FWDGT is clocked by IRC32K clock, which is forced on when FWDGT started. Characteristics 6.2.2.  4 to 50 MHz High Speed crystal oscillator (HXTAL).  Internal 64 MHz RC oscillator (IRC64M).  Internal 48 MHz RC oscillator (IRC48M).
Page 225: Figure 6-4. Hxtal Clock Source In Bypass Mode
GD32H737/757/759 User Manual Select external clock bypass mode by setting the HXTALBPS and HXTALEN bits in the control register RCU_CTL. The CK_HXTAL is equal to the external clock which drives the OSCIN pin.During bypass mode, the signal is connected to OSCIN, and OSCOUT remains in the suspended state, as shown in Figure 6-4.
Page 226 GD32H737/757/759 User Manual The frequency accuracy of the IRC48M can be calibrated by the manufacturer, but its operating frequency is still not enough accurate because the USBHS need the frequency must between 48MHz±1%. A hardware automatically dynamic trim performed in CTC unit adjust the IRC48M to the needed frequency.
Page 227 GD32H737/757/759 User Manual CK_LPIR4M clock to be the system or kernel clock when the system initially wakes-up. Phase locked loop (PLL) There are five internal Phase Locked Loop, the PLL0, PLL1, PLL2, PLLUSBHS0 and PLLUSBHS1. The PLL0, PLL1 and PLL2 support integer and fraction factors and the fraction factors can be modified at run time.
Page 228 GD32H737/757/759 User Manual Peripheral clock switch dynamically If the peripheral has two more source clock selection, the peripheral can switches from the running clock to another present clock dynamically. Otherwise, peripheral clock can not be switched. Only TRNG / USART / I2C / SPI / RSPDIF / SAI / SDIO / EXMC / CAN / HPDF peripherals support clock switch dynamically.
Page 229: Table 6-1. Clock Output 0 Source Select
GD32H737/757/759 User Manual Clock output capability The clock output capability is ranging from 32 kHz to 600 MHz. There are several clock signals can be selected via the CK_OUT0 clock source selection bits, CKOUT0SEL, in the Clock configuration register 2 (RCU_CFG2). The corresponding GPIO pin should be configured in the properly alternate function I/O (AFIO) mode to output the selected clock signal.
Page 230: Register Definition
GD32H737/757/759 User Manual 6.3. Register definition RCU base address: 0x5802 4400 Control register (RCU_CTL) 6.3.1. Address offset: 0x00 Reset value: 0xC000 8040 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). IRC64MS IRC64ME HXTALB HXTALST HXTALE...
Page 231 GD32H737/757/759 User Manual 1: PLL1 is stable PLL1EN PLL1 enable Set and reset by software. Reset by hardware when entering Deep-sleep or Standby mode. 0: PLL1 is switched off 1: PLL1 is switched on PLL0STB PLL0 clock stabilization flag Set by hardware to indicate if the PLL0 output clock is stable and ready for use.
Page 232: Pll0 Register (Rcu_Pll0)
GD32H737/757/759 User Manual 1: High speed 4 ~ 50 MHz crystal oscillator enabled 15:7 IRC64MCALIB[8:0] Internal 64MHz RC Oscillator calibration value These bits are load automatically at power on. IRC64MADJ[6:0] Internal 64MHz RC Oscillator clock trim adjust value These bits are set by software. The trimming value is these bits IRC64MADJ[6:0] added to the IRC64MCALIB[8:0] bits.
Page 233 GD32H737/757/759 User Manual Reserved Must be kept at reset value. 22:16 PLL0P[6:0] The PLL0P output frequency division factor from PLL0 VCO clock Set and reset by software when the PLL0 is disable. These bits used to generator PLL0P output clock (CK_PLL0P) from PLL0 VCO clock (CK_PLL0VCO). The CK_PLL0P is used to system clock (no more than 600MHz).
Page 234: Clock Configuration Register 0 (Rcu_Cfg0)
GD32H737/757/759 User Manual 111111: CK_PLL0SRC / 63 Clock configuration register 0 (RCU_CFG0) 6.3.3. Address offset: 0x08 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). I2C0SEL[1:0] APB3PSC[2:0] APB4PSC[2:0] Reserved RTCDIV[5:0] APB2PSC[2:0] APB1PSC[2:0]...
Page 235 GD32H737/757/759 User Manual 000010: CK_HXTAL / 2 000011: CK_HXTAL / 3 … 111111: CK_HXTAL / 63 15:13 APB2PSC[2:0] APB2 prescaler selection Set and reset by software to control the APB2 clock division ratio. 0xx: CK_AHB selected 100: (CK_AHB / 2) selected...
Page 236: Clock Interrupt Register (Rcu_Int)
GD32H737/757/759 User Manual HXTAL is selected directly or indirectly as the clock source of CK_SYS. 00: Select CK_IRC64MDIV as the CK_SYS source 01: Select CK_HXTAL as the CK_SYS source 10: Select CK_LPIRC4M as the CK_SYS source 11: Select CK_PLL0P as the CK_SYS source Clock interrupt register (RCU_INT) 6.3.4.
Page 237 GD32H737/757/759 User Manual Set by hardware when the LPIRC4M clock is stuck. Reset when setting the LPIRC4MSTBIC bit by software. 0: Clock operating normally 1: LPIRC4M clock stuck CKMIC HXTAL clock stuck interrupt clear Write 1 by software to reset the CKMIF flag.
Page 238 GD32H737/757/759 User Manual 0: Disable the PLL2 stabilization interrupt 1: Enable the PLL2 stabilization interrupt PLL1STBIE PLL1 stabilization interrupt enable Set and reset by software to enable/disable the PLL1 stabilization interrupt. 0: Disable the PLL1 stabilization interrupt 1: Enable the PLL1 stabilization interrupt...
Page 239: Ahb1 Reset Register (Rcu_Ahb1Rst)
GD32H737/757/759 User Manual 0: No PLL1 stabilization interrupt generated 1: PLL1 stabilization interrupt generated PLL0STBIF PLL0 stabilization interrupt flag Set by hardware when the PLL0 is stable and the PLL0STBIE bit is set. Reset when setting the PLL0STBIC bit by software.
Page 240 GD32H737/757/759 User Manual USBHS0R ENET1R Reserved Reserved Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. USBHS1RST USBHS1 reset This bit is set and reset by software. 0: No reset 1: Reset the USBHS1 28:26 Reserved Must be kept at reset value.
Page 241: Ahb2 Reset Register (Rcu_Ahb2Rst)
GD32H737/757/759 User Manual 0: No reset 1: Reset the Ethernet1 AHB2 reset register (RCU_AHB2RST) 6.3.6. Address offset: 0x14 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved TRNGRS SDIO1RS Reserved TMURST...
Page 242: Ahb3 Reset Register (Rcu_Ahb3Rst)
GD32H737/757/759 User Manual FACRST FAC reset This bit is set and reset by software. 0: No reset 1: Reset the FAC DCIRST DCI reset This bit is set and reset by software. 0: No reset 1: Reset the DCI AHB3 reset register (RCU_AHB3RST) 6.3.7.
Page 243: Ahb4 Reset Register (Rcu_Ahb4Rst)
GD32H737/757/759 User Manual 1: Reset the OSPI0 OSPIMRST OSPIM reset This bit is set and reset by software. 0: No reset 1: Reset the OSPIM MDMARST MDMA reset This bit is set and reset by software. 0: No reset 1: Reset the MDMA...
Page 244 GD32H737/757/759 User Manual 1: Reset the HWSEM CRCRST CRC reset This bit is set and reset by software. 0: No reset 1: Reset the CRC 13:10 Reserved Must be kept at reset value. PKRST GPIO port K reset This bit is set and reset by software.
Page 245: Apb1 Reset Register (Rcu_Apb1Rst)
GD32H737/757/759 User Manual PBRST GPIO port B reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port B PARST GPIO port A reset This bit is set and reset by software. 0: No reset...
Page 246 GD32H737/757/759 User Manual CTCRST CTC reset This bit is set and reset by software. 0: No reset 1: Reset the CTC 26:25 Reserved Must be kept at reset value. I2C3RST I2C3 reset This bit is set and reset by software.
Page 247 GD32H737/757/759 User Manual 0: No reset 1: Reset the MDIO SPI2RST SPI2 reset This bit is set and reset by software. 0: No reset 1: Reset the SPI2 SPI1RST SPI1 reset This bit is set and reset by software. 0: No reset...
Page 248: Apb2 Reset Register (Rcu_Apb2Rst)
GD32H737/757/759 User Manual 1: Reset the TIMER22 TIMER6RST TIMER6 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER6 TIMER5RST TIMER5 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER5...
Page 249 GD32H737/757/759 User Manual Bits Fields Descriptions TRIGSELRST TRIGSEL reset This bit is set and reset by software. 0: No reset 1: Reset the TRIGSEL EDOUTRST EDOUT reset This bit is set and reset by software. 0: No reset 1: Reset the EDOUT...
Page 250 GD32H737/757/759 User Manual 0: No reset 1: Reset the SPI5 SPI4RST SPI4 reset This bit is set and reset by software. 0: No reset 1: Reset the SPI4 HPDFRST HPDF reset This bit is set and reset by software. 0: No reset...
Page 251: Apb3 Reset Register (Rcu_Apb3Rst)
GD32H737/757/759 User Manual 0: No reset 1: Reset the all ADC1 ADC0RST ADC0 reset This bit is set and reset by software. 0: No reset 1: Reset the all ADC0 Reserved Must be kept at reset value. USART5RST USART5 reset This bit is set and reset by software.
Page 252: Apb4 Reset Register (Rcu_Apb4Rst)
GD32H737/757/759 User Manual 31:2 Reserved Must be kept at reset value. WWDGTRST WWDGT reset This bit is set and reset by software. 0: No reset 1: Reset the WWDGT TLIRST TLI reset This bit is set and reset by software.
Page 253: Ahb1 Enable Register (Rcu_Ahb1En)
GD32H737/757/759 User Manual SYSCFGRST SYSCFG reset This bit is set and reset by software. 0: No reset 1: Reset the SYSCFG AHB1 enable register (RCU_AHB1EN) 6.3.13. Address offset: 0x30 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit).
Page 254 GD32H737/757/759 User Manual 1: Enabled Ethernet0 TX clock ENET0EN Ethernet0 clock enable This bit is set and reset by software. 0: Disabled Ethernet0 clock 1: Enabled Ethernet0 clock Reserved Must be kept at reset value. DMAMUXEN DMAMUX clock enable This bit is set and reset by software.
Page 255: Ahb2 Enable Register (Rcu_Ahb2En)
GD32H737/757/759 User Manual 0: Disabled Ethernet1 TX clock 1: Enabled Ethernet1 TX clock ENET1EN Ethernet1 clock enable This bit is set and reset by software. 0: Disabled Ethernet1 clock 1: Enabled Ethernet1 clock AHB2 enable register (RCU_AHB2EN) 6.3.14. Address offset: 0x34 Reset value: 0x0000 0100 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit).
Page 256: Ahb3 Enable Register (Rcu_Ahb3En)
GD32H737/757/759 User Manual CAUEN CAU clock enable This bit is set and reset by software. 0: Disabled CAU clock 1: Enabled CAU clock SDIO1EN SDIO1 clock enable This bit is set and reset by software. 0: Disabled SDIO1 clock 1: Enabled SDIO1 clock...
Page 257 GD32H737/757/759 User Manual 1: Enabled RAMECCMU0 clock RTDEC1EN RTDEC1 clock enable This bit is set and reset by software. 0: Disabled RTDEC1 clock 1: Enabled RTDEC1 clock RTDEC0EN RTDEC0 clock enable This bit is set and reset by software. 0: Disabled RTDEC0 clock...
Page 258: Ahb4 Enable Register (Rcu_Ahb4En)
GD32H737/757/759 User Manual AHB4 enable register (RCU_AHB4EN) 6.3.16. Address offset: 0x3C Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved HWSEME BKPSRA CRCEN Reserved PKEN PJEN PHEN PGEN PFEN PEEN PDEN...
Page 259: Apb1 Enable Register (Rcu_Apb1En)
GD32H737/757/759 User Manual 1: Enabled GPIO port H clock PGEN GPIO port G clock enable This bit is set and reset by software. 0: Disabled GPIO port G clock 1: Enabled GPIO port G clock PFEN GPIO port F clock enable This bit is set and reset by software.
Page 260 GD32H737/757/759 User Manual RSPDIFE TIMER51 TIMER50 TIMER31 TIMER30 TIMER23 TIMER22 TIMER6E TIMER5E TIMER4E TIMER3E TIMER2E TIMER1E SPI2EN SPI1EN Reserved Bits Fields Descriptions UART7EN UART7 clock enable This bit is set and reset by software. 0: Disabled UART7 clock 1: Enabled UART7 clock...
Page 261 GD32H737/757/759 User Manual I2C0EN I2C0 clock enable This bit is set and reset by software. 0: Disabled I2C0 clock 1: Enabled I2C0 clock UART4EN UART4 clock enable This bit is set and reset by software. 0: Disabled UART4 clock 1: Enabled UART4 clock...
Page 262 GD32H737/757/759 User Manual 0: Disabled TIMER51 clock 1: Enabled TIMER51 clock TIMER50EN TIMER50 clock enable This bit is set and reset by software. 0: Disabled TIMER50 clock 1: Enabled TIMER50 clock TIMER31EN TIMER31 clock enable This bit is set and reset by software.
Page 263: Apb2 Enable Register (Rcu_Apb2En)
GD32H737/757/759 User Manual This bit is set and reset by software. 0: Disabled TIMER2 clock 1: Enabled TIMER2 clock TIMER1EN TIMER1 clock enable This bit is set and reset by software. 0: Disabled TIMER1 clock 1: Enabled TIMER1 clock APB2 enable register (RCU_APB2EN) 6.3.18.
Page 264 GD32H737/757/759 User Manual This bit is set and reset by software. 0: Disabled TIMER42 clock 1: Enabled TIMER42 clock TIMER41EN TIMER41 clock enable This bit is set and reset by software. 0: Disabled TIMER41 clock 1: Enabled TIMER41 clock TIMER40EN TIMER40 clock enable This bit is set and reset by software.
Page 265 GD32H737/757/759 User Manual TIMER15EN TIMER15 clock enable This bit is set and reset by software. 0: Disabled TIMER15 clock 1: Enabled TIMER15 clock TIMER14EN TIMER14 clock enable This bit is set and reset by software. 0: Disabled TIMER14 clock 1: Enabled TIMER14 clock...
Page 266: Apb3 Enable Register (Rcu_Apb3En)
GD32H737/757/759 User Manual 1: Enabled USART0 clock Reserved Must be kept at reset value. TIMER7EN TIMER7 clock enable This bit is set and reset by software. 0: Disabled TIMER7 clock 1: Enabled TIMER7 clock TIMER0EN TIMER0 clock enable This bit is set and reset by software.
Page 267: Ahb1 Sleep Mode Enable Register (Rcu_Ahb1Spen)
GD32H737/757/759 User Manual Reserved LPDTSE SYSCFG Reserved PMUEN VREFEN CMPEN Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. PMUEN PMU clock enable This bit is set and reset by software. 0: Disabled PMU clock 1: Enabled PMU clock...
Page 268 GD32H737/757/759 User Manual USBHS0 USBHS0S ENET1PT ENET1R ENET1TX ENET1S ULPISPE Reserved PSPEN XSPEN SPEN Bits Fields Descriptions Reserved Must be kept at reset value. USBHS1ULPISPEN USBHS1 ULPI clock enable when sleep mode This bit is set and reset by software.
Page 269 GD32H737/757/759 User Manual 1: Enabled DMA1 clock when sleep mode DMA0SPEN DMA0 clock enable when sleep mode This bit is set and reset by software. 0: Disabled DMA0 clock when sleep mode 1: Enabled DMA0 clock when sleep mode 20:18 Reserved Must be kept at reset value.
Page 270: Ahb2 Sleep Mode Enable Register (Rcu_Ahb2Spen)
GD32H737/757/759 User Manual 1: Enabled Ethernet1 clock when sleep mode AHB2 sleep mode enable register (RCU_AHB2SPEN) 6.3.22. Address offset: 0x54 Reset value: 0x0000 01DF This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved RAMECC TMUSPE...
Page 271: Ahb3 Sleep Mode Enable Register (Rcu_Ahb3Spen)
GD32H737/757/759 User Manual This bit is set and reset by software. 0: Disabled SDIO1 clock when sleep mode 1: Enabled SDIO1 clock when sleep mode FACSPEN FAC clock enable when sleep mode This bit is set and reset by software.
Page 272 GD32H737/757/759 User Manual 1: Enabled RAMECCMU0 clock when sleep mode RTDEC1SPEN RTDEC1 clock enable when sleep mode This bit is set and reset by software. 0: Disabled RTDEC1 clock when sleep mode 1: Enabled RTDEC1 clock when sleep mode RTDEC0SPEN RTDEC0 clock enable when sleep mode This bit is set and reset by software.
Page 273: Ahb4 Sleep Mode Enable Register (Rcu_Ahb4Spen)
GD32H737/757/759 User Manual AHB4 sleep mode enable register (RCU_AHB4SPEN) 6.3.24. Address offset: 0x5C Reset value: 0x0000 63FF This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved BKPSRAM Reserved CRCSPEN Reserved PKSPEN PJSPEN PHSPEN PGSPEN PFSPEN PESPEN PDSPEN PCSPEN PBSPEN PASPEN...
Page 274: Apb1 Sleep Mode Enable Register (Rcu_Apb1Spen)
GD32H737/757/759 User Manual 1: Enabled GPIO port G clock when sleep mode PFSPEN GPIO port F clock enable when sleep mode This bit is set and reset by software. 0: Disabled GPIO port F clock when sleep mode 1: Enabled GPIO port F clock when sleep mode...
Page 275 GD32H737/757/759 User Manual Bits Fields Descriptions UART7SPEN UART7 clock enable when sleep mode This bit is set and reset by software. 0: Disabled UART7 clock when sleep mode 1: Enabled UART7 clock when sleep mode UART6SPEN UART6 clock enable when sleep mode This bit is set and reset by software.
Page 276 GD32H737/757/759 User Manual This bit is set and reset by software. 0: Disabled UART4 clock when sleep mode 1: Enabled UART4 clock when sleep mode UART3SPEN UART3 clock enable when sleep mode This bit is set and reset by software.
Page 277 GD32H737/757/759 User Manual 1: Enabled TIMER50 clock when sleep mode TIMER31SPEN TIMER31 clock enable when sleep mode This bit is set and reset by software. 0: Disabled TIMER31 clock when sleep mode 1: Enabled TIMER31 clock when sleep mode TIMER30SPEN TIMER30 clock enable when sleep mode This bit is set and reset by software.
Page 278: Apb2 Sleep Mode Enable Register (Rcu_Apb2Spen)
GD32H737/757/759 User Manual 0: Disabled TIMER1 clock when sleep mode 1: Enabled TIMER1 clock when sleep mode APB2 sleep mode enable register (RCU_APB2SPEN) 6.3.26. Address offset: 0x64 Reset value: 0xFFFF 3733 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit).
Page 279 GD32H737/757/759 User Manual 0: Disabled TIMER41 clock when sleep mode 1: Enabled TIMER41 clock when sleep mode TIMER40SPEN TIMER40 clock enable when sleep mode This bit is set and reset by software. 0: Disabled TIMER40 clock when sleep mode 1: Enabled TIMER40 clock when sleep mode...
Page 280 GD32H737/757/759 User Manual This bit is set and reset by software. 0: Disabled TIMER14 clock when sleep mode 1: Enabled TIMER14 clock when sleep mode 15:14 Reserved Must be kept at reset value. SPI3SPEN SPI3 clock enable when sleep mode This bit is set and reset by software.
Page 281: Apb3 Sleep Mode Enable Register (Rcu_Apb3Spen)
GD32H737/757/759 User Manual 1: Enabled TIMER7 clock when sleep mode TIMER0SPEN TIMER0 clock enable when sleep mode This bit is set and reset by software. 0: Disabled TIMER0 clock when sleep mode 1: Enabled TIMER0 clock when sleep mode APB3 sleep mode enable register (RCU_APB3SPEN) 6.3.27.
Page 282: Backup Domain Control Register (Rcu_Bdctl)
GD32H737/757/759 User Manual PMUSPE LPDTSS VREFSPE CMPSPE SYSCFG Reserved SPEN Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. PMUSPEN PMU clock enable when sleep mode This bit is set and reset by software. 0: Disabled PMU clock when sleep mode...
Page 283 GD32H737/757/759 User Manual LXTALBP LXTALST RTCEN Reserved RTCSRC[1:0] Reserved LCKMD LCKMEN LXTALDRI[1:0] LXTALEN Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. BKPRST Backup domain reset This bit is set and reset by software. 0: No reset 1: Resets backup domain...
Page 284: Reset Source/Clock Register (Rcu_Rstsck)
GD32H737/757/759 User Manual LXTALDRI[1:0] LXTAL drive capability Set and reset by software. Backup domain reset resets this value. 00: Lower driving capability edium low driving capability 10: Medium high driving capability 11: Higher driving capability Note: The LXTALDRI is not in bypass mode.
Page 285 GD32H737/757/759 User Manual WWDGTRSTF Window watchdog timer reset flag Set by hardware when a window watchdog timer reset generated. Reset by writing 1 to the RSTFC bit. 0: No window watchdog reset generated 1: Window watchdog reset generated FWDGTRSTF Free watchdog timer reset flag Set by hardware when free watchdog timer reset generated.
Page 286: Pll Clock Additional Control Register (Rcu_Plladdctl)
GD32H737/757/759 User Manual IRC32KEN IRC32K enable Set and reset by software. 0: Disable IRC32K 1: Enable IRC32K PLL clock additional control register (RCU_PLLADDCTL) 6.3.31. Address offset: 0x80 Reset value: 0xFF81 0101 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit).
Page 287 GD32H737/757/759 User Manual 0: Disable the CK_PLL1R output 1: Enable the CK_PLL1R output PLL1QEN PLL1Q divider output enable This bit is set and reset by software. The PLL1QEN bit can be written only if the PLL1EN is 0. 0: Disable the CK_PLL1Q output...
Page 288: Pll1 Register (Rcu_Pll1)
GD32H737/757/759 User Manual 0000010: CK_PLL1Q = CK_PLL1VCO / 3. 0000011: CK_PLL1Q = CK_PLL1VCO / 4 0000100: CK_PLL1Q = CK_PLL1VCO / 5 … 1111111: CK_PLL1Q = CK_PLL1VCO / 128 Reserved Must be kept at reset value. PLL0Q[6:0] The PLL0Q output frequency division factor from PLL0 VCO clock Set and reset by software when the PLL0 is disable.
Page 289 GD32H737/757/759 User Manual CK_PLL1VCO is described in PLL1N bits in RCU_PLL1 register. 0000000: CK_PLL1R = CK_PLL1VCO 0000001: CK_PLL1R = CK_PLL1VCO / 2 0000010: CK_PLL1R = CK_PLL1VCO / 3. 0000011: CK_PLL1R = CK_PLL1VCO / 4 0000100: CK_PLL1R = CK_PLL1VCO / 5 …...
Page 290: Pll2 Register (Rcu_Pll2)
GD32H737/757/759 User Manual The VCO source clock is between 1M to 16MHz. 000000: Reserved. 000001: CK_PLL1SRC 000010: CK_PLL1SRC / 2 000011: CK_PLL1SRC / 3 … 111111: CK_PLL1SRC / 63 PLL2 register (RCU_PLL2) 6.3.33. Address offset: 0x88 Reset value: 0x0101 2020...
Page 291 GD32H737/757/759 User Manual Set and reset by software when the PLL2 is disable. These bits used to generator PLL2 P output clock (CK_PLL2P) from PLL2 VCO clock (CK_PLL2VCO). The CK_PLL2P is used to USBHS (48MHz), TRNG (48MHz), or SDIO (≤48MHz). The CK_PLL2VCO is described in PLL2N bits in RCU_PLL2 register.
Page 292: Clock Configuration Register 1 (Rcu_Cfg1)
GD32H737/757/759 User Manual Clock configuration register 1 (RCU_CFG1) 6.3.34. Address offset: 0x8C Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). HPDFSE TIMERSE Reserved USART5SEL[1:0] USART2SEL[1:0] USART1SEL[1:0] PLL2RDIV[1:0] PERSEL[1:0] CAN2SEL[1:0] CAN1SEL[1:0] CAN0SEL[1:0]...
Page 293 GD32H737/757/759 User Manual 10: CK_LXTAL selected as USART2 source clock 11: CK_IRC64MDIV selected as USART2 source clock 19:18 USART1SEL[1:0] USART1 clock source selection Set and reset by software to control the USART1 clock source 00: CK_APB1 selected as USART1 source clock...
Page 294: Clock Configuration Register 2 (Rcu_Cfg2)
GD32H737/757/759 User Manual RSPDIFSEL[1:0] RSPDIF clock source selection Set and reset by software to control the RSPDIF clock source 00: CK_PLL0Q selected as RSPDIF source clock 01: CK_PLL1R selected as RSPDIF source clock 10: CK_PLL2R selected as RSPDIF source clock...
Page 295 GD32H737/757/759 User Manual 000: CK_PLL0Q selected as SAI2 BLOCK 0 source clock 001: CK_PLL1P selected as SAI2 BLOCK 0 source clock 010: CK_PLL2P selected as SAI2 BLOCK 0 source clock 011: I2S_CKIN selected as SAI2 BLOCK 0 source clock 100: CK_PER selected as SAI2 BLOCK 0 source clock...
Page 296: Clock Configuration Register 3 (Rcu_Cfg3)
GD32H737/757/759 User Manual 11:8 CKOUT1DIV[3:0] The CK_OUT1 divider which the CK_OUT1 frequency can be reduced see bits14:12 of RCU_CFG2 for CK_OUT1 0000: inhibit predividers 0001: CK_OUT1 is divided by 1 0010: CK_OUT1 is divided by 2 0011: CK_OUT1 is divided by 3 0100: CK_OUT1 is divided by 4 …...
Page 297 GD32H737/757/759 User Manual Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). DSPWUS Reserved ADC2SEL[1:0] ADC01SEL[1:0] Reserved Reserved Reserved SDIO1SEL Reserved I2C3SEL[1:0] I2C2SEL[1:0] I2C1SEL[1:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value.
Page 298: Pll All Configuration Register (Rcu_Pllall)
GD32H737/757/759 User Manual or switched to HXTAL, this bit cannot be changed. 23:13 Reserved Must be kept at reset value. SDIO1SEL SDIO1 clock source selection Set and reset by software to control the SDIO1 clock source. 0: CK_PLL0Q selected as SDIO1 source clock...
Page 299 GD32H737/757/759 User Manual 31:18 Reserved Must be kept at reset value. 17:16 PLLSEL[1:0] PLLs clock source selection Set and reset by software to control the PLLs clock source. 00: CK_IRC64MDIV selected as source clock of PLL0, PLL1, PLL2 01: CK_LPIRC4M selected as source clock of PLL0, PLL1, PLL2...
Page 300: Pll0 Fraction Configuration Register (Rcu_Pll0Fra)
GD32H737/757/759 User Manual 11: input clock frequency: 8 - 16MHz PLL0 fraction configuration register (RCU_PLL0FRA) 6.3.38. Address offset: 0x9C Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved PLL0FRA Reserved PLL0FRAN[12:0]...
Page 301: Pll2 Fraction Configuration Register (Rcu_Pll2Fra)
GD32H737/757/759 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. PLL1FRAEN PLL1 fractional latch enable. These bits are set and reset by software. These bits can lock the PLL1FRAN value into a Sigma-Delta modulator .When PLL1FRAEN bit switchs from "0" to "1", the PLL1FRAN value will transfer to modulator.
Page 302: Additional Clock Control Register 0 (Rcu_Addctl0)
GD32H737/757/759 User Manual tune the PLL2 VCO. These bits must configure the PLL2 VCO out frequency to the following range: When PLL2VCOSEL = 0, the range is 192MHz to 836MHz; When PLL2VCOSEL = 1, the range is 150MHz to 420MHz.
Page 303: Additional Clock Control Register 1(Rcu_Addctl1)
GD32H737/757/759 User Manual IRC48M clock or PLL48M clock. The CK48M clock used for TRNG/USBHS. The PLL48M clock refer to PLL48MSEL bit in RCU_ADDCTL register. 0: Don’t select IRC48M clock (use CK_PLL0Q clock or CK_PLL2P clock select by PLL48MSEL) 1: Select IRC48M clock Additional clock control register 1(RCU_ADDCTL1) 6.3.42.
Page 304: Additional Clock Interrupt Register (Rcu_Addint)
GD32H737/757/759 User Manual LPIRC4MDSPEN LPIRC4M clock enable in deepsleep mode Set and reset by software. LPIRC4M can be forced on even in deepsleep mode to quickly be used as a kernel clock for some peripherals. This bit has no effect on the value of LPIRC4MEN.
Page 305 GD32H737/757/759 User Manual PLLUSB IRC48MS PLLUSBH PLLUSBH IRC48MS PLLUSBH Reserved Reserved HS1STBI Reserved TBIE S1STBIE S0STBIE TBIF S0STBIF Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. IRC48MSTBIC Internal 48 MHz RC oscillator Stabilization interrupt clear Write 1 by software to reset the IRC48MSTBIF flag.
Page 306: Clock Configuration Register 4 (Rcu_Cfg4)
GD32H737/757/759 User Manual 1: IRC48M stabilization interrupt generated PLLUSBHS1STBIF Internal PLL of USBHS1 stabilization interrupt flag Set by hardware when the USBHS1 PLL clock is stable and the PLLUSBHS1STBIE bit is set. Reset by software when setting the PLLUSBHS1STBIC bit.
Page 307: Usb Clock Control Register (Rcu_Usbclkctl)
GD32H737/757/759 User Manual 1: CK_PLL1R selected as SDIO0 source clock USB clock control register (RCU_USBCLKCTL) 6.3.45. Address offset: 0xD4 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved USBHS1PSC[2:0] USBHS0PSC[2:0] PLLUSBH...
Page 308 GD32H737/757/759 User Manual 111 :CK_USBHS0 = CK_PLL1Q / 8 Reserved Must be kept at reset value. 14:13 USBHS148MSEL[1:0] USBHS1 48M clock source selection Set and reset by software. 00: CK_PLL0R selected as USBHS1 48M source clock 01: CK_PLLUSBHS1/USBHS1DV output clock selected as USBHS1 48M source...
Page 309: Pllusb Configuration Register (Rcu_Pllusbcfg)
GD32H737/757/759 User Manual 0: 48M selected as USBHS0 source clock 1: 60M selected as USBHS0 source clock Reserved Must be kept at reset value. PLLUSB configuration register (RCU_PLLUSBCFG) 6.3.46. Address offset: 0xD8 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit).
Page 310: Apb2 Additional Reset Register (Rcu_Addapb2Rst)
GD32H737/757/759 User Manual 0000: Reserved 0001: PLLUSBHS1PREDV input source clock divided by 1 0010: PLLUSBHS1PREDV input source clock divided by / 2 … 1111: PLLUSBHS1PREDV input source clock divided by / 15 Reserved Must be kept at reset value. 14:8...
Page 311: Apb2 Additional Enable Register (Rcu_Addapb2En)
GD32H737/757/759 User Manual Reserved CAN2RS CAN1RS CAN0RS Reserved Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. CAN2RST CAN2 reset This bit is set and reset by software. 0: No reset 1: Reset CAN2 unit CAN1RST CAN1 reset This bit is set and reset by software.
Page 312: Apb2 Additional Sleep Enable Register (Rcu_Addapb2Spen)
GD32H737/757/759 User Manual CAN1EN CAN1 clock enable This bit is set and reset by software. 0: Disable CAN1 clock 1: Enable CAN1 clock CAN0EN CAN0 clock enable This bit is set and reset by software. 0: Disable CAN0 clock 1: Enable CAN0 clock APB2 additional sleep enable register (RCU_ADDAPB2SPEN) 6.3.49.
Page 313 GD32H737/757/759 User Manual This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved SPI5SEL[2:0] Reserved SPI4SEL[2:0] Reserved SPI3SEL[2:0] Reserved SPI2SEL[2:0] Reserved SPI1SEL[2:0] Reserved SPI0SEL[2:0] Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. 22:20...
Page 314 GD32H737/757/759 User Manual Reserved Must be kept at reset value. 10:8 SPI2SEL[2:0] SPI2 / I2S2 clock source selection Set and reset by software to control the SPI2 / I2S2 clock source 000: CK_PLL0Q selected as SPI2 / I2S2 source clock...
Page 315: Clock Trim Controller (Ctc)
GD32H737/757/759 User Manual Clock trim controller (CTC) Overview 7.1. The Clock Trim Controller (CTC) is used to trim internal 48MHz RC oscillator (IRC48M) automatically by hardware. The CTC unit trim the frequency of the IRC48M based on an external accurate reference signal source. It can automatically adjust the trim value to provide a precise IRC48M clock.
Page 316: Ref Sync Pulse Generator
GD32H737/757/759 User Manual Figure 7-1. CTC overview PCLK1 APB1 BUS Register SWREFPUL Reserved GPIO (CTC_SYNC) Prescale (/1,/2,/4, ,/128) LXTAL Reserved REFPSC[2:0] REFSEL[1:0] REF sync pulse CK_IRC48M RLVALUE 48MHz Counter REFDIR REFCAP TRIMVALUE TRIMVALUE Comparator adjustment CKLIM REF sync pulse generator 7.3.1.
Page 317: Frequency Evaluation And Automatically Trim Process
GD32H737/757/759 User Manual and then up- counting to 128 x CKLIM (defined in CTC_CTL1 register), and then stop until next REF sync pulse detected. If any REF sync pulse detected, the current CTC trim counter value is captured to REFCAP in status register (CTC_STAT), and the counter direction is captured to REFDIR in status register (CTC_STAT).
Page 318: Software Program Guide
GD32H737/757/759 User Manual CTC_CTL0 register is 1. If the AUTOTRIM bit in CTC_CTL0 register set, the TRIMVALUE in CTC_CTL0 register is not changed.  CKLIM ≤ Counter < 3 x CKLIM when REF sync pulse is detected. The CKOKIF in CTC_STAT register set, and an interrupt generated if CKOKIE bit in CTC_CTL0 register is 1.
Page 319 GD32H737/757/759 User Manual RLVALUE = ( F ÷ F ) - 1 (7-2) clock The typical step size is 0.12%. Where the F is the frequency of correct clock (IRC48M), clock the F is the frequency of reference sync pulse.
Page 320: Register Definition
GD32H737/757/759 User Manual Register definition 7.4. CTC base address: 0x4000 8400 Control register 0 (CTC_CTL0) 7.4.1. Address offset: 0x00 Reset value: 0x0000 2000 This register has to be accessed by word (32-bit) Reserved SWREF AUTO CKWARN Reserved TRIMVALUE[5:0] CNTEN Reserved EREFIE...
Page 321: Control Register 1 (Ctc_Ctl1)
GD32H737/757/759 User Manual 0: CTC trim counter disabled 1: CTC trim counter enabled. Reserved Must be kept at reset value. EREFIE EREFIF interrupt enable 0: EREFIF interrupt disable 1: EREFIF interrupt enable ERRIE Error (ERRIF) interrupt enable 0: ERRIF interrupt disable...
Page 322: Status Register (Ctc_Stat)
GD32H737/757/759 User Manual 01: LXTAL clock selected Other values are reserved. Reserved Must be kept at reset value. 26:24 REFPSC[2:0] Reference signal source prescaler These bits are set and cleared by software 000: Reference signal not divided 001: Reference signal divided by 2...
Page 323 GD32H737/757/759 User Manual When a reference sync pulse occurred during the counter is working, the CTC trim counter direction is captured to REFDIR bit. 0: Up-counting 1: Down-counting 14:11 Reserved Must be kept at reset value. TRIMERR Trim value error bit This bit is set by hardware when the TRIMVALUE in CTC_CTL0 register overflow or underflow.
Page 324: Interrupt Clear Register (Ctc_Intc)
GD32H737/757/759 User Manual 1: An error occur CKWARNIF Clock trim warning interrupt flag This bit is set by hardware when a clock trim warning occurred. If the CTC trim counter greater or equal to 3 x CKLIM and smaller to 128 x CKLIM when a reference sync pulse detected, this bit will be set.
Page 325 GD32H737/757/759 User Manual REFMISS and CKERR bits in CTC_STAT register. Write 0 is no effect. CKWARNIC CKWARNIF interrupt clear bit This bit is written by software and read as 0. Write 1 to clear CKWARNIF bit in CTC_STAT register. Write 0 is no effect.
Page 326: Interrupt / Event Controller (Exti)
GD32H737/757/759 User Manual Interrupt / event controller (EXTI) Overview 8.1. ® Cortex -M7 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and power management controls. It’s tightly coupled to the processer core. More details about ®...
Page 327: Table 8-1. Nvic Exception Types In Cortex ® -M7
GD32H737/757/759 User Manual ® Table 8-1. NVIC exception types in Cortex Vector Exception type Priority (a) Vector address Description number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management...
Page 328 GD32H737/757/759 User Manual Interrupt Vector Peripheral interrupt description Vector address number number DMA0 channel0 global interrupt 0x0000_006C IRQ 11 IRQ 12 DMA0 channel1 global interrupt 0x0000_0070 IRQ 13 DMA0 channel2 global interrupt 0x0000_0074 IRQ 14 DMA0 channel3 global interrupt 0x0000_0078...
Page 329 GD32H737/757/759 User Manual Interrupt Vector Peripheral interrupt description Vector address number number UART4 global interrupt 0x0000_0114 IRQ 53 TIMER5 global interrupt and DAC underrun error IRQ 54 0x0000_0118 interrupt IRQ 55 TIMER6 global interrupt 0x0000_011C IRQ 56 DMA1 channel 0 global interrupt...
Page 330 GD32H737/757/759 User Manual Interrupt Vector Peripheral interrupt description Vector address number number I2C3 event interrupt 0x0000_01BC IRQ 95 I2C3 error interrupt 0x0000_01C0 IRQ 96 IRQ 97 RSPDIF global interrupt 0x0000_01C4 0x0000_01C8- IRQ 98-101 114-117 Reserved 0x0000_01D4 IRQ 102 DMAMUX overrun interrupt...
Page 331 GD32H737/757/759 User Manual Interrupt Vector Peripheral interrupt description Vector address number number TMU global interrupt 0x0000_02A8 IRQ 154 0x0000_02AC- Reserved IRQ 155-160 171-176 0x0000_02C0 IRQ 161 TIMER22 global interrupt 0x0000_02C4 IRQ 162 TIMER23 global interrupt 0x0000_02C8 IRQ 163 TIMER30 global interrupt...
Page 332 GD32H737/757/759 User Manual Interrupt Vector Peripheral interrupt description Vector address number number CAN2 interrupt for message buffer IRQ 194 0x0000_0348 CAN2 interrupt for Bus off / Bus off done IRQ 195 0x0000_034C CAN2 interrupt for Error IRQ 196 0x0000_0350 CAN2 interrupt for Error in fast transmission...
Page 333: External Interrupt And Event (Exti) Block Diagram
GD32H737/757/759 User Manual External interrupt and event (EXTI) block diagram 8.4. Figure 8-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~37 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control External interrupt and event function overview 8.5.
Page 334: Table 8-3. Exti Source
GD32H737/757/759 User Manual Hardware trigger Hardware trigger may be used to detect the voltage change of external or internal signals. The software should follow these steps to use this function: Configure EXTI sources in SYSCFG module based on application requirement.
Page 335 GD32H737/757/759 User Manual EXTI line Source number RTC alarm RTC tamper and timestamp event, LXTAL clock stuck RTC wakeup CMP0 output CMP1 output Ethernet1 wakeup Ethernet0 wakeup CAN0 wakeup CAN1 wakeup CAN2 wakeup USART0 wakeup USART1 wakeup USART2 wakeup USART5 wakeup...
Page 336: Register Definition
GD32H737/757/759 User Manual 8.6. Register definition EXTI base address: 0x5800 0000 Interrupt enable register 0 (EXTI_INTEN0) 8.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). INTEN31 INTEN30 INTEN29 INTEN28 INTEN27 INTEN26 INTEN25 INTEN24 INTEN23 INTEN22 INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16...
Page 337: Falling Edge Trigger Enable Register 0 (Exti_Ften0)
GD32H737/757/759 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). RTEN31 RTEN30 RTEN29 RTEN28 RTEN27 RTEN26 RTEN25 RTEN24 RTEN23 RTEN22 RTEN21 RTEN20 RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8...
Page 338: Pending Register 0 (Exti_Pd0)
GD32H737/757/759 User Manual Bits Fields Descriptions Interrupt / event software trigger bit x (x = 0…31) 31:0 SWIEVx 0: Deactivate the EXTIx software interrupt / event request 1: Activate the EXTIx software interrupt / event request Pending register 0 (EXTI_PD0) 8.6.6.
Page 339: Event Enable Register 1 (Exti_Even1)
GD32H737/757/759 User Manual Event enable register 1 (EXTI_EVEN1) 8.6.8. Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved EVEN37 EVEN36 EVEN35 EVEN34 EVEN33 EVEN32 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value.
Page 340: Software Interrupt Event Register 1 (Exti_Swiev1)
GD32H737/757/759 User Manual Reserved Reserved FTEN37 FTEN36 FTEN35 FTEN34 FTEN33 FTEN32 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. Falling edge trigger enable bit x (x = 32…37) FTENx 0: Falling edge of linex is invalid 1: Falling edge of linex is valid as an interrupt / event request Software interrupt event register 1 (EXTI_SWIEV1) 8.6.11.
Page 341 GD32H737/757/759 User Manual rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. Interrupt pending status bit x (x = 32…37) 0: EXTI linex is not triggered 1: EXTI linex is triggered. This bit is cleared to 0 by writing 1 to it.
Page 342: Trigger Selection Controller (Trigsel)
GD32H737/757/759 User Manual Trigger selection controller (TRIGSEL) Overview 9.1. The trigger selection controller (TRIGSEL) allows software to select the trigger input signal for various peripherals. TRIGSEL provides a flexible mechanism for a peripheral to select different trigger inputs. With TRIGSEL, there are up to 4 trigger selection outputs could be selected for each peripheral.
Page 343: Internal Connect
GD32H737/757/759 User Manual Figure 9-1. TRIGSEL main composition example Trigger Select Trigger input 0 Trigger output 3 Trigger input 1 Trigger output 2 Peripheral_x Trigger output 1 Trigger output 0 Trigger input 255 INSELx Trigger Register Internal connect 9.4. The TRIGSEL allows software to select the trigger input for peripherals. The Table 9-1.
Page 344 GD32H737/757/759 User Manual fields bits value trigger input selection 0x0c TRIGSEL_IN10 0x0d TRIGSEL_IN11 0x0e TRIGSEL_IN12 0x0f TRIGSEL_IN13 0x10 LXTAL_TRG 0x11 TIMER0_TRGO0 0x12 TIMER0_TRGO1 0x13 TIMER0_CH0 0x14 TIMER0_CH1 0x15 TIMER0_CH2 0x16 TIMER0_CH3 0x17 TIMER0_MCH0 0x18 TIMER0_MCH1 0x19 TIMER0_MCH2 0x1a TIMER0_MCH3 0x1b~0x20...
Page 345 GD32H737/757/759 User Manual fields bits value trigger input selection 0x3a TIMER4_CH2 0x3b TIMER4_CH3 0x3c TIMER4_ETI 0x3d TIMER5_TRGO0 0x3e TIMER6_TRGO0 0x3f TIMER7_TRGO0 0x40 TIMER7_TRGO1 0x41 TIMER7_CH0 0x42 TIMER7_CH1 0x43 TIMER7_CH2 0x44 TIMER7_CH3 0x45 TIMER7_MCH0 0x46 TIMER7_MCH1 0x47 TIMER7_MCH2 0x48 TIMER7_MCH3 0x49~0x4e...
Page 346 GD32H737/757/759 User Manual fields bits value trigger input selection 0x6b TIMER23_CH0 0x6c TIMER23_CH1 0x6d TIMER23_CH2 0x6e TIMER23_CH3 0x6f TIMER23_ETI 0x70 TIMER30_TRGO0 0x71 TIMER30_CH0 0x72 TIMER30_CH1 0x73 TIMER30_CH2 0x74 TIMER30_CH3 0x75 TIMER30_ETI 0x76 TIMER31_TRGO0 0x77 TIMER31_CH0 0x78 TIMER31_CH1 0x79 TIMER31_CH2 0x7a...
Page 347: Table 9-2. Trigsel Input And Output Mapping
GD32H737/757/759 User Manual fields bits value trigger input selection 0x98 TIMER44_TRGO0 0x99 TIMER44_CH0 0x9a TIMER44_CH1 0x9b TIMER44_MCH0 0x9c~0x9d Reserved 0x9e TIMER44_BRKIN 0x9f TIMER50_TRGO0 0xa0 TIMER51_TRGO0 0xa1 RTC_Alarm 0xa2 RTC_TPTS 0xa3 ADC0_WD0_OUT 0xa4 ADC0_WD1_OUT 0xa5 ADC0_WD2_OUT 0xa6 ADC1_WD0_OUT 0xa7 ADC1_WD1_OUT 0xa8...
Page 348 GD32H737/757/759 User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output TRIGSEL_IN2 TRIGSEL_IN3 Output0 TRIGSEL_OUT2 TRIGSEL_EXTOUT1 TRIGSEL_IN4 Output1 TRIGSEL_OUT3 TRIGSEL_IN5 TRIGSEL_IN6 TRIGSEL_IN7 Output0 TRIGSEL_OUT4 TRIGSEL_EXTOUT2 TRIGSEL_IN8 Output1 TRIGSEL_OUT5 TRIGSEL_IN9 TRIGSEL_IN10 TRIGSEL_IN11 Output0 TRIGSEL_OUT6 TRIGSEL_EXTOUT3 TRIGSEL_IN12 Output1 TRIGSEL_OUT7 TRIGSEL_IN13 LXTAL_TRG...
Page 349 GD32H737/757/759 User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output TIMER3_CH0 TIMER3_CH1 TRIGSEL_TIMER14B Output0 TIMER14_BRKIN0 TIMER3_CH2 RKIN TIMER3_CH3 TIMER3_ETI TIMER4_TRGO0 TRIGSEL_TIMER15B Output0 TIMER15_BRKIN0 TIMER4_CH0 RKIN TIMER4_CH1 TIMER4_CH2 TIMER4_CH3 TRIGSEL_TIMER16B Output0 TIMER16_BRKIN0 TIMER4_ETI RKIN TIMER5_TRGO0 TIMER6_TRGO0 TIMER7_TRGO0 TRIGSEL_TIMER40B Output0...
Page 350 GD32H737/757/759 User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output TIMER22_CH1 TIMER22_CH2 CAN2_EX_TIME_TIC TRIGSEL_CAN2 Output0 TIMER22_CH3 TIMER22_ETI TIMER23_TRGO0 TIMER23_CH0 TRIGSEL_LPDTS Output0 LPDTS_TRG TIMER23_CH1 TIMER23_CH2 TIMER23_CH3 TIMER23_ETI TRIGSEL_EDOUT Output0 EDOUT_TRG TIMER30_TRGO0 TIMER30_CH0 TIMER30_CH1 TIMER30_CH2 TRIGSEL_HPDF Output0 HPDF_ITR TIMER30_CH3 TIMER30_ETI...
Page 351 GD32H737/757/759 User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output TIMER43_MCH0 TIMER43_BRKIN TRIGSEL_TIMER22E Output0 TIMER22_ETI TIMER44_TRGO0 TIMER44_CH0 TIMER44_CH1 TIMER44_MCH0 TRIGSEL_TIMER23E Output0 TIMER23_ETI TIMER44_BRKIN TIMER50_TRGO0 TIMER51_TRGO0 RTC_Alarm TRIGSEL_TIMER30E Output0 TIMER30_ETI RTC_TPTS ADC0_WD0_OUT ADC0_WD1_OUT ADC0_WD2_OUT TRIGSEL_TIMER31E Output0 TIMER31_ETI ADC1_WD0_OUT ADC1_WD1_OUT...
Page 352 GD32H737/757/759 User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output TRIGSEL_TIMER14I Output0 TIMER14_ITI14 TI14 TRIGSEL_TIMER22I Output0 TIMER22_ITI14 TI14 TRIGSEL_TIMER23I Output0 TIMER23_ITI14 TI14 TRIGSEL_TIMER30I Output0 TIMER30_ITI14 TI14 TRIGSEL_TIMER31I Output0 TIMER31_ITI14 TI14 TRIGSEL_TIMER40I Output0 TIMER40_ITI14 TI14 TRIGSEL_TIMER41I Output0 TIMER41_ITI14 TI14...
Page 353 GD32H737/757/759 User Manual Note: All output can select all input as trigger source except TIMERx_BRKINx and TIMERx_ITIx. TIMERx_BRKINx can only select TIMERx_BRKINx as trigger. TIMERx_ITIx cannot select CMP_OUT and LXTAL_TRG, other timers CHx/MCHx signals and their own signals as trigger. When illegal data is selected for these outputs, the output will be selected as 0.
Page 354: Register Definition
GD32H737/757/759 User Manual Register definition 9.5. TRIGSEL base address: 0x4001 8400 Trigger selection for EXTOUT0 register (TRIGSEL_EXTOUT0) 9.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved INSEL1[7:0] INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock.
Page 355: Trigger Selection For Extout2 Register (Trigsel_Extout2)
GD32H737/757/759 User Manual INSEL1[7:0] INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_EXTOUT1 register. 0: TRIGSEL_EXTOUT1 register write is enabled.
Page 356: Trigger Selection For Extout3 Register (Trigsel_Extout3)
GD32H737/757/759 User Manual These bits are used to select trigger input signal connected to output1. The output is used as the source of external output5 signal. For the detailed configuration, please refer to Table 9-1. Trigger input bit fields selection.
Page 357: Trigger Selection For Adc1 Register (Trigsel_Adc1)
GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). Reserved INSEL1[7:0] INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_ADC0 register.
Page 358: Trigger Selection For Adc2 Register (Trigsel_Adc2)
GD32H737/757/759 User Manual 30:16 Reserved Must be kept at reset value. 15:8 Reserved Must be kept at reset value. INSEL0[7:0] Trigger input source selection for output0 These bits are used to select trigger input signal connected to output0. The output is used as the source of ADC1_ROUTRG(ADC1 routine sequence) trigger input.
Page 359: Trigger Selection For Dac_Out1 Register (Trigsel_Dacout1)
GD32H737/757/759 User Manual Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_DACOUT0 register. 0: TRIGSEL_DACOUT0 register write is enabled.
Page 360: Trigger Selection For Timer0_Brkin Register (Trigsel_Timer0Brkin)
GD32H737/757/759 User Manual These bits are used to select trigger input signal connected to output0. The output is used as the source of DAC_OUT1_EXTRIG (DAC_OUT1 external trigger) input. For the detailed configuration, please refer to Table 9-1. Trigger input bit fields selection.
Page 361: Trigger Selection For Timer14_Brkin Register (Trigsel_Timer14Brkin)
GD32H737/757/759 User Manual Reset value: 0x0051 504F This register has to be accessed by word (32-bit). Reserved INSEL2[7:0] INSEL1[7:0] INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER7BRKIN register.
Page 362: Trigger Selection For Timer15_Brkin Register (Trigsel_Timer15Brkin)
GD32H737/757/759 User Manual Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER14BRKIN register. 0: TRIGSEL_TIMER14BRKIN register write is enabled.
Page 363: Trigger Selection For Timer16_Brkin Register (Trigsel_Timer16Brkin)
GD32H737/757/759 User Manual Trigger selection for TIMER16_BRKIN register (TRIGSEL_TIMER16B 9.5.14. RKIN) Address offset: 0x34 Reset value: 0x0000 0063 This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER16BRKIN register.
Page 364: Trigger Selection For Timer41_Brkin Register (Trigsel_Timer41Brkin)
GD32H737/757/759 User Manual TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER40BRKIN register. 0: TRIGSEL_TIMER40BRKIN register write is enabled. 1: TRIGSEL_TIMER40BRKIN register write is disabled.
Page 365: Trigger Selection For Timer42_Brkin Register (Trigsel_Timer42Brkin)
GD32H737/757/759 User Manual Trigger selection for TIMER42_BRKIN register (TRIGSEL_TIMER42B 9.5.17. RKIN) Address offset: 0x40 Reset value: 0x0000 0090 This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER42BRKIN register.
Page 366: Trigger Selection For Timer44_Brkin Register (Trigsel_Timer44Brkin)
GD32H737/757/759 User Manual TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER43BRKIN register. 0: TRIGSEL_TIMER43BRKIN register write is enabled. 1: TRIGSEL_TIMER43BRKIN register write is disabled.
Page 367: Trigger Selection For Can1 Register (Trigsel_Can1)
GD32H737/757/759 User Manual Reset value: 0x0000 003d This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_CAN0 register.
Page 368: Trigger Selection For Can2 Register (Trigsel_Can2)
GD32H737/757/759 User Manual INSEL0[7:0] Trigger input source selection for output0 These bits are used to select trigger input signal connected to output0. The output is used as the source of CAN1_EX_TIME_TICK trigger input. For the detailed configuration, please refer to Table 9-1.
Page 369: Trigger Selection For Timer0_Eti Register (Trigsel_Timer0Eti)
GD32H737/757/759 User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_LPDTS register. 0: TRIGSEL_LPDTS register write is enabled. 1: TRIGSEL_LPDTS register write is disabled.
Page 370: Trigger Selection For Timer2_Eti Register (Trigsel_Timer2Eti)
GD32H737/757/759 User Manual Reset value: 0x0000 002a This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER1ETI register.
Page 371: Trigger Selection For Timer3_Eti Register (Trigsel_Timer3Eti)
GD32H737/757/759 User Manual INSEL0[7:0] Trigger input source selection for output0 These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER2_ETI trigger input. For the detailed configuration, please refer to Table 9-1.
Page 372: Trigger Selection For Timer7_Eti Register (Trigsel_Timer7Eti)
GD32H737/757/759 User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER4ETI register. 0: TRIGSEL_TIMER4ETI register write is enabled. 1: TRIGSEL_TIMER4ETI register write is disabled.
Page 373: Trigger Selection For Timer23_Eti Register (Trigsel_Timer23Eti)
GD32H737/757/759 User Manual Reset value: 0x0000 0069 This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER22ETI register.
Page 374: Trigger Selection For Timer30_Eti Register (Trigsel_Timer30Eti)
GD32H737/757/759 User Manual INSEL0[7:0] Trigger input source selection for output0 These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER23_ETI trigger input. For the detailed configuration, please refer to Table 9-1.
Page 375: Trigger Selection For Edout Register (Trigsel_Edout)
GD32H737/757/759 User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER31ETI register. 0: TRIGSEL_TIMER31ETI register write is enabled. 1: TRIGSEL_TIMER31ETI register write is disabled.
Page 376: Trigger Selection For Timer0_Iti14 Register (Trigsel_Timer0Iti14)
GD32H737/757/759 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_HPDF register.
Page 377: Trigger Selection For Timer1_Iti14 Register (Trigsel_Timer1Iti14)
GD32H737/757/759 User Manual INSEL0[7:0] Trigger input source selection for output0 These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER0_ITI14 trigger input. For the detailed configuration, please refer to Table 9-1.
Page 378: Trigger Selection For Timer3_Iti14 Register (Trigsel_Timer3Iti14)
GD32H737/757/759 User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER2ITI14 register. 0: TRIGSEL_TIMER2ITI14 register write is enabled. 1: TRIGSEL_TIMER2ITI14 register write is disabled.
Page 379: Trigger Selection For Timer7_Iti14 Register (Trigsel_Timer7Iti14)
GD32H737/757/759 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER4ITI14 register.
Page 380: Trigger Selection For Timer14_Iti14 Register (Trigsel_Timer14Iti14)
GD32H737/757/759 User Manual INSEL0[7:0] Trigger input source selection for output0 These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER7_ITI14 trigger input. For the detailed configuration, please refer to Table 9-1.
Page 381: Trigger Selection For Timer23_Iti14 Register (Trigsel_Timer23Iti14)
GD32H737/757/759 User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER22ITI14 register. 0: TRIGSEL_TIMER22ITI14 register write is enabled. 1: TRIGSEL_TIMER22ITI14 register write is disabled.
Page 382: Trigger Selection For Timer31_Iti14 Register (Trigsel_Timer31Iti14)
GD32H737/757/759 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER30ITI14 register.
Page 383: Trigger Selection For Timer40_Iti14 Register (Trigsel_Timer40Iti14)
GD32H737/757/759 User Manual INSEL0[7:0] Trigger input source selection for output0 These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER31_ITI14 trigger input. For the detailed configuration, please refer to Table 9-1.
Page 384: Trigger Selection For Timer42_Iti14 Register (Trigsel_Timer42Iti14)
GD32H737/757/759 User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER41ITI14 register. 0: TRIGSEL_TIMER41ITI14 register write is enabled. 1: TRIGSEL_TIMER41ITI14 register write is disabled.
Page 385: Trigger Selection For Timer44_Iti14 Register (Trigsel_Timer44Iti14)
GD32H737/757/759 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER43ITI14 register.
Page 386 GD32H737/757/759 User Manual INSEL0[7:0] Trigger input source selection for output0 These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER44_ITI14 trigger input. For the detailed configuration, please refer to Table 9-1.
Page 387: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32H737/757/759 User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) 10.1. Overview There are up to 135 general purpose I/O pins (GPIO), named PA0~PA10, PA13~PA15, PB0~PB15, PC0~PC15, PD0~PD15, PE0~PE15, PF0~PF15, PG0~PG15, PH0~PH15, PJ8~PJ11, PK0~PK2 for the device to implement logic input/output functions. Each GPIO port has related control and configuration registers to satisfy the requirements of specific applications.
Page 388: Figure 10-1. Basic Structure Of A Standard I/O Port Bit
GD32H737/757/759 User Manual be configured by GPIO output speed registers (GPIOx_OSPD). Each port can be configured as floating (no pull-up and pull-down), pull-up or pull-down function by GPIO pull-up/pull-down registers (GPIOx_PUD). Table 10-1. GPIO configuration table PAD TYPE CTLy PUDy...
Page 389: Gpio Pin Configuration
GD32H737/757/759 User Manual Figure 10-1. Basic structure of a standard I/O port bit Write Bit Operate Registers Output Output driver Control Read/Write Register Output Control Alternate Function Output protection Analog ( Input / Output ) I/O pin Alternate Function Input...
Page 390: External Interrupt/Event Lines
GD32H737/757/759 User Manual External interrupt/event lines 10.3.2. All ports have external interrupt capability. To use external interrupt lines, the port must be configured as input mode. Alternate functions (AF) 10.3.3. When the port is configured as AFIO (set CTLy bits to “0b10”, which is in GPIOx_CTL registers), the port is used as peripheral alternate functions.
Page 391: Analog Configuration
GD32H737/757/759 User Manual  The schmitt trigger input is enabled.  The weak pull-up and pull-down resistors could be chosen.  The output buffer is enabled. Open Drain Mode: The pad output low level when a “0” in the output control register;...
Page 392: Alternate Function (Af) Configuration
GD32H737/757/759 User Manual Figure 10-4. Analog configuration protection Analog ( Input / Output ) I/O pin Alternate function (AF) configuration 10.3.8. To suit for different device packages, the GPIO supports some alternate functions mapped to some other pins by software.
Page 393: Gpio Single Cycle Toggle Function
GD32H737/757/759 User Manual register (GPIOx_LOCK). When the special LOCK sequence has occurred on LKK bit in GPIOx_LOCK register and the LKy bit is set in GPIOx_LOCK register, the corresponding port is locked and the corresponding port configuration cannot be modified until the next reset. It recommended to be used in the configuration of driving a power module.
Page 394: Input Filtering
GD32H737/757/759 User Manual To ADC Output driver The switch default state depends on PxySWON bit Reset value in SYSCFG_PMCFG Alternate Function Output Output Control protection I/O pin Alternate Function Input Schmitt trigger Input driver To ADC CTLx [1:0] in GPIOx_CTL...
Page 395: Figure 10-7. Filtering Using The Sampling Window
GD32H737/757/759 User Manual Filtering using the sampling window In this mode, the signal first communicates with the system clock (CK_AHB), and then the filtering process through the specified number of cycles will be carry out before allowing the input to be changed. Users need to specify two parameters for this type of filtering: sampling period and sampling times.
Page 396: Figure 10-8. Input Filtering Clock Cycle
GD32H737/757/759 User Manual the width of the sampling window or a longer time. The number of sampling windows is always one less than the number of samples. For three sampling windows, the width of sampling window is two sampling periods. Similarly, for six sampling windows, the width of sampling window is five sampling periods.
Page 397: Register Definition
GD32H737/757/759 User Manual 10.4. Register definition GPIOA base address: 0x5802 0000 GPIOB base address: 0x5802 0400 GPIOC base address: 0x5802 0800 GPIOD base address: 0x5802 0C00 GPIOE base address: 0x5802 1000 GPIOF base address: 0x5802 1400 GPIOG base address: 0x5802 1800...
Page 398 GD32H737/757/759 User Manual These bits are set and cleared by software. Refer to CTL0[1:0] description 23:22 CTL11[1:0] Pin 11 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 21:20 CTL10[1:0] Pin 10 configuration bits These bits are set and cleared by software.
Page 399: Port Output Mode Register (Gpiox_Omode, X=A
GD32H737/757/759 User Manual 01: GPIO output mode 10: Alternate function mode 11: Analog mode Note: PB2 is used for BOOT1, so the default mode is Input Floating mode. Port output mode register (GPIOx_OMODE, x=A…H, J, K) 10.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit).
Page 400: Port Output Speed Register (Gpiox_Ospd, X=A
GD32H737/757/759 User Manual Refer to OM0 description Pin 8 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 7 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 6 output mode bit These bits are set and cleared by software.
Page 401 GD32H737/757/759 User Manual OSPD7[1:0] OSPD6[1:0] OSPD5[1:0] OSPD4[1:0] OSPD3[1:0] OSPD2[1:0] OSPD1[1:0] OSPD0[1:0] Bits Fields Descriptions 31:30 OSPD15[1:0] Pin 15 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description 29:28 OSPD14[1:0] Pin 14 output max speed bits These bits are set and cleared by software.
Page 402: Port Pull-Up/Down Register (Gpiox_Pud, X=A
GD32H737/757/759 User Manual OSPD4[1:0] Pin 4 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description OSPD3[1:0] Pin 3 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description...
Page 403 GD32H737/757/759 User Manual Refer to PUD0[1:0] description 25:24 PUD12[1:0] Pin 12 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description 23:22 PUD11[1:0] Pin 11 pull-up or pull-down bits These bits are set and cleared by software.
Page 404: Port Input Status Register (Gpiox_Istat, X=A
GD32H737/757/759 User Manual PUD0[1:0] Pin 0 pull-up or pull-down bits These bits are set and cleared by software. 00: Floating mode, no pull-up and pull-down (reset value) 01: With pull-up mode 10: With pull-down mode 11: Reserved Port input status register (GPIOx_ISTAT, x=A…H, J, K) 10.4.5.
Page 405: Port Bit Operate Register (Gpiox_Bop, X=A
GD32H737/757/759 User Manual These bits are set and cleared by software. 0: Pin output low 1: Pin output high Port bit operate register (GPIOx_BOP, x=A...H, J, K) 10.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit).
Page 406: Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A
GD32H737/757/759 User Manual It can only be set by using the lock key writing sequence. And is always readable. 0: GPIOx_LOCK register and the port configuration are not locked 1: GPIOx_LOCK register is locked until an MCU reset LOCK key writing sequence: Write 1→Write 0→Write 1→...
Page 407: Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A
GD32H737/757/759 User Manual 11:8 SEL2[3:0] Pin 2 alternate function selected These bits are set and cleared by software. Refer to SEL0[3:0] description SEL1[3:0] Pin 1 alternate function selected These bits are set and cleared by software. Refer to SEL0[3:0] description...
Page 408: Bit Clear Register (Gpiox_Bc, X=A
GD32H737/757/759 User Manual Refer to SEL8[3:0] description 19:16 SEL12[3:0] Pin 12 alternate function selected These bits are set and cleared by software. Refer to SEL8[3:0] description 15:12 SEL11[3:0] Pin 1 alternate function selected These bits are set and cleared by software.
Page 409: Port Bit Toggle Register (Gpiox_Tg, X=A
GD32H737/757/759 User Manual 31:16 Reserved Must be kept at reset value. 15:0 Port clear bit y(y=0..15) These bits are set and cleared by software. 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit Port bit toggle register (GPIOx_TG, x=A…H, J, K) 10.4.12.
Page 410: Input Filtering Type Register (Gpiox_Iftp, X=A
GD32H737/757/759 User Manual 00: FLPRDx = CK_AHB 01: FLPRDx = CK_AHB / 2 02: FLPRDx = CK_AHB / 4 ..FF: FLPRDx = CK_AHB / 510 FLPRD0 Filter sampling period for GPIO1 to GPIO7: 00: FLPRDx = CK_AHB 01: FLPRDx = CK_AHB / 2 02: FLPRDx = CK_AHB / 4 ..
Page 411 GD32H737/757/759 User Manual 21:20 IFTP10[1:0] Pin 10 input filtering type bits These bits are set and cleared by software. Refer to IFTP0[1:0] description 19:18 IFTP9[1:0] Pin 9 input filtering type bits These bits are set and cleared by software. Refer to IFTP0[1:0] description...
Page 412: Cyclic Redundancy Checks Management Unit (Crc)
GD32H737/757/759 User Manual Cyclic redundancy checks management unit (CRC) Overview 11.1. A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 7/8/16/32 bit CRC code within user...
Page 413: Function Overview
GD32H737/757/759 User Manual Function overview 11.3.  CRC calculation unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If the CRC_DATA register has not been cleared by setting the CRC_CTL register, the new input raw data will be calculated based on the result of previous value of CRC_DATA.
Page 414: Register Definition
GD32H737/757/759 User Manual Register definition 11.4. CRC base address: 0x4002 3000 Data register (CRC_DATA) 11.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Software writes and reads.
Page 415: Control Register (Crc_Ctl)
GD32H737/757/759 User Manual by any other peripheral. The CRC_CTL register will generate no effect to the byte. Control register (CRC_CTL) 11.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved REV_O...
Page 416: Polynomial Register (Crc_Poly)
GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). IDATA[31:16] IDATA[15:0] Bits Fields Descriptions 31:0 IDATA[31:0] Configurable initial CRC data value When RST bit in CRC_CTL asserted, CRC_DATA will be programmed to this value. Polynomial register (CRC_POLY) 11.4.5.
Page 417: True Random Number Generator (Trng)
GD32H737/757/759 User Manual True random number generator (TRNG) Overview 12.1. The true random number generator (TRNG) module can generate a 32-bit random value by using continuous analog noise and it has been pre-certified NIST SP800-90B. Characteristics 12.2.  LFSR (Linear Feedback Shift Register) mode and NIST (National Institute of Standards and Technology) mode to generate random number.
Page 418: Function Overview
GD32H737/757/759 User Manual Function overview 12.3. Figure 12-1. TRNG block diagram 32-bit *4 / 32-bit * 8 32-bit HCLK Clock Check Seed Check 128/256-bit Conditioning (optional) TRNG_CLK 256/440-bit post-process (optional) Analog Seed NIST HCLK domain mode TRNG_CLK domain There are two modes in TRNG module, NIST mode and LFSR mode.
Page 419: Post Processing
GD32H737/757/759 User Manual increase the entropy of the random number, and TRNG generates 32-bit data each time in this mode. Post processing 12.3.2. When this function is enabled, half of the bits are taken from the sampled noise source, half of the bits are taken from inverted sampled noise source.
Page 420: Health Tests
GD32H737/757/759 User Manual Health tests 12.3.5. This component ensures the stable operation of TRNG and can quickly monitor the occurrence of errors. The health tests features of TRNG module following NIST SP800-90B. For more details about thresholds, refer to TRNG_HTCFG register.
Page 421: Nist Mode State
GD32H737/757/759 User Manual NIST mode state 12.3.6. The states of NIST mode are shown below: The initial state of the TRNG is idle state. It goes to warm-up state after enabling the TRNG by setting RNGEN bit in the TRNG_CTL register. This state is a period for analog initialition.
Page 422: Error Flags
GD32H737/757/759 User Manual set. As required by the FIPS PUB 140-2, the first random data in data register should be saved but not be used. Every subsequent new random data should be compared to the previously random data. The data can only be used if it is not equal to the previously one.
Page 423: Register Definition
GD32H737/757/759 User Manual Register definition 12.4. TRNG base address: 0x4802 1800 Control register (TRNG_CTL) 12.4.1. Address offset: 0x00 Reset value: 0x0300 0410 This register has to be accessed by word (32-bit). CONDRS CTL_LK Reserved NR[1:0] Reserved CLKDIV[3:0] INMOD OUTMOD ALGO[1:0]...
Page 424 GD32H737/757/759 User Manual 0: 256 bits 1: 440 bits OUTMOD Select random data width output of conditioning module 0: 128-bit 1: 256-bit conditioning module hash algorithm selection 13:12 ALGO[1:0] 00: SHA1 01: MD5 10: SHA224 11: SHA256 Reserved Must be kept at reset value.
Page 425: Status Register (Trng_Stat)
GD32H737/757/759 User Manual Must be kept at reset value. Reserved Status register (TRNG_STAT) 12.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved SEIF CEIF Reserved ERR_STA SECS CECS DRDY rc_w0...
Page 426: Data Register (Trng_Data)
GD32H737/757/759 User Manual DRDY Random data ready status bit. This bit is cleared by reading the TRNG_DATA register and set when a new random number is generated. 0: The content of TRNG data register is not available. 1: The content of TRNG data register is available.
Page 427 GD32H737/757/759 User Manual RCT_TH[6:0] Repetition count test threshold. Default 40.
Page 428: Cryptographic Acceleration Unit (Cau)
GD32H737/757/759 User Manual Cryptographic Acceleration Unit (CAU) 13.1. Overview The cryptographic acceleration unit (CAU) is used to encipher and decipher data with DES, Triple-DES or AES (128, 192, or 256) algorithms. This module follows the following standards:  The Data Encryption Standard (DES) and the Triple Data Encryption Algorithm (TDEA) are announced by Federal Information Processing Standards Publication (FIPS) 46-3, October 25, 1999.
Page 429: Cau Data Type And Initialization Vectors
GD32H737/757/759 User Manual  Multiple data types are supported, including No swapping, Half-word swapping Byte swapping and Bit swapping.  Data can be transferred by DMA, CPU during interrupts, or without both of them. Support to use initial key from EFUSE.
Page 430: Initialization Vectors
GD32H737/757/759 User Manual Figure 13-2. DATAM Byte swapping and Bit swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Byte swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Bit swapping Initialization vectors 13.3.2. The initialization vectors are used in CBC, CTR, GCM, GMAC, CCM, CFB and OFB modes to XOR with data blocks.
Page 431: Des / Tdes Cryptographic Acceleration Processor
GD32H737/757/759 User Manual Figure 13-3. CAU diagram CAU_ CAU_ CAU_ CAU_ CAU_ CAU_ CAU_ CAU_ CAU_GCMCC CAU_GCMCT STAT0 DMAEN INTEN INTF STAT1 KEY0..3 IV0..1 MCTXS0..7 XS0..7 AHB BUS CAU_DI CAU_DO Input FIFO Output FIFO Configuration 8*32 8*32 Data swapping Data swapping Cryptographic acceleration core（DES / TDES / AES）...
Page 432: Figure 13-4. Des / Tdes Ecb Encryption
GD32H737/757/759 User Manual DES / TDES ECB encryption The 64-bit input plaintext is first obtained after data swapping according to the data type. When the TDES algorithm is configured, the input data block is read in the DEA and encrypted using KEY1.
Page 433: Figure 13-5. Des / Tdes Ecb Decryption
GD32H737/757/759 User Manual Figure 13-5. DES / TDES ECB decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt SWAP CAU_DO Plaintext DES / TDES CBC encryption The input data of the DEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors.
Page 434: Figure 13-6. Des / Tdes Cbc Encryption
GD32H737/757/759 User Manual Figure 13-6. DES / TDES CBC encryption CAU_DI Plaintext DATAM SWAP CAU_IV0(H/L) KEY1 DEA, encrypt KEY2 DEA, decrypt KEY3 DEA, encrypt SWAP CAU_DO Ciphertext DES / TDES CBC decryption In DES / TDES CBC decryption, when the TDES algorithm is configured, the first ciphertext block is used directly after data swapping according to the data type, it is read in the DEA and decrypted using KEY3.
Page 435: Aes Cryptographic Acceleration Processor
GD32H737/757/759 User Manual Figure 13-7. DES / TDES CBC decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt CAU_IV0(H/L) SWAP CAU_DO Plaintext AES cryptographic acceleration processor 13.4.2. The AES cryptographic acceleration processor consists of three components, including the AES algorithm (AEA), multiple keys and the initialization vectors or Nonce.
Page 436: Figure 13-8. Aes Ecb Encryption
GD32H737/757/759 User Manual Figure 13-8. AES ECB encryption CAU_DI Plaintext DATAM SWAP CAU_KEY0...3 AEA, encrypt SWAP CAU_DO Ciphertext AES-ECB mode decryption First of all, the key derivation must be completed to prepare the decryption keys, the input key of the key schedule is the same to that used in encryption. The last round key obtained from the above operation is then used as the first round key in the decryption.
Page 437: Figure 13-9. Aes Ecb Decryption
GD32H737/757/759 User Manual Figure 13-9. AES ECB decryption CAU_DI Ciphertext DATAM SWAP CAU_KEY0..3 AEA, decrypt SWAP CAU_DO Plaintext AES-CBC mode encryption The input data of the AEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors. The XOR result of the swapped plaintext data block and the 128-bit initialization vector CAU_IV0..1 is read in the...
Page 438: Figure 13-11. Aes Cbc Decryption
GD32H737/757/759 User Manual Figure 13-10. AES CBC encryption CAU_DI Plaintext DATAM SWAP CAU_IV0..1(H/L) CAU_KEY0..3 AEA, encrypt SWAP CAU_DO Ciphertext AES-CBC mode decryption Similar to that in AES-ECB mode decryption, the key derivation also must be completed first to prepare the decryption keys, the input of the key schedule should be the same to that used in encryption.
Page 439: Figure 13-12. Counter Block Structure
GD32H737/757/759 User Manual Figure 13-11. AES CBC decryption CAU_DI Ciphertext DATAM SWAP CAU_KEY0..3 AEA, decrypt CAU_IV0..1(H/L) SWAP CAU_DO Plaintext AES-CTR mode In counter mode, a counter is used in addition with a nonce value to be encrypted and decrypted in AEA, and the result will be used for the XOR operation with the plaintext or the ciphertext.
Page 440 GD32H737/757/759 User Manual Figure 13-13. AES CTR encryption/decryption Plaintext/ CAU_DI Ciphertext DATAM SWAP CAU_IV0..1(H/L) AEA, encrypt/ CAU_KEY0..3 decrypt SWAP Ciphertext CAU_DO Plaintext AES-GCM mode The AES Galois / counter mode (GCM) can be used to encrypt or authenticate message, and then ciphertext and tag can be obtained.
Page 441 GD32H737/757/759 User Manual can also be used. Repeat (h) until all AAD data are supplied, wait until BUSY bit is cleared. 3. GCM encryption / decryption phase This phase must be performed after GCM AAD phase. In this phase, the message is authenticated and encrypted / decrypted.
Page 442 GD32H737/757/759 User Manual 1. CCM prepare phase In this phase, B0 packet (the first packet) is programmed into the CAU_DI register. CAU_DO never contain data in this phase. (a) Clear the CAUEN bit to make sure CAU is disabled. (b) Configure the ALGM[3:0] bits to ‘1001’.
Page 443: Operating Modes
GD32H737/757/759 User Manual is needed. The input is the A0 value. (q) Wait until the ONE flag is set to 1, and then read CAU_DO 4 times. The output corresponds to the authentication tag. (r) Disable the CAU AES-CFB mode...
Page 444 GD32H737/757/759 User Manual 14. Enable the CAU by set the CAUEN bit as 1 in the CAU_CTL register. 15. If the INF bit in the CAU_STAT0 register is 1, then write data blocks into the CAU_DI register. The data can be transferred by DMA / CPU during interrupts / no DMA or interrupts.
Page 445: Cau Dma Interface
GD32H737/757/759 User Manual Data append For GCM payload encryption or CCM payload decryption, CAU supports non 128 bit integer multiple data block processing. When the last data block is less than 128bit, use ‘0’ to fill the remaining bits, and then configure the number of bytes to be filled in the NBPILB bitfield of the CAU_CTL register.
Page 446: Cau Suspended Mode
GD32H737/757/759 User Manual 13.8. CAU suspended mode It is possible to suspend a data block if another new data block with a higher priority needs to be processed in CAU. The following steps can be performed to complete the encryption / decryption acceleration of the suspended data blocks.
Page 447: Register Definition
GD32H737/757/759 User Manual 13.9. Register definition CAU base address: 0x4802 1000 Control register (CAU_CTL) 13.9.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved NBPILB[3:0] ALGM[3] Reserved GCM_CCMPH[1:0] CAUEN FFLUSH Reserved KEYM[1:0]...
Page 448 GD32H737/757/759 User Manual 13:10 Reserved Must be kept at reset value. KEYM[1:0] AES key size mode configuration, must be configured when BUSY=0 00: 128-bit key length 01: 192-bit key length 10: 256-bit key length 11: never use DATAM[1:0] Data swapping type mode configuration, must be configured when BUSY=0...
Page 449: Status Register 0 (Cau_Stat0)
GD32H737/757/759 User Manual KEY_SEL Key select 0: Use key from CAU_KEY0..3(H/L) 1:Use key from efuse Status register 0 (CAU_STAT0) 13.9.2. Address offset: 0x04 Reset value: 0x0000 0003 This register has to be accessed by word (32-bit). Reserved Reserved BUSY Bits...
Page 450: Data Output Register (Cau_Do)
GD32H737/757/759 User Manual Reset value: 0x0000 0000 The data input register is used to transfer plaintext or ciphertext blocks into the input FIFO for processing. The MSB is firstly written into the FIFO and the LSB is the last one. If the CAUEN is 0 and the input FIFO is not empty, when it is read, then the first data in the FIFO is popped out and returned.
Page 451: Dma Enable Register (Cau_Dmaen)
GD32H737/757/759 User Manual DMA enable register (CAU_DMAEN) 13.9.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved DMAOEN DMAIEN Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. DMAOEN...
Page 452: Status Register 1 (Cau_Stat1)
GD32H737/757/759 User Manual 1: IN FIFO interrupt is enable Status register 1 (CAU_STAT1) 13.9.7. Address offset: 0x18 Reset value: 0x0000 0001 This register has to be accessed by word (32-bit). Reserved Reserved OSTA ISTA Bits Fields Descriptions 31:2 Reserved Must be kept at reset value.
Page 453: Key Registers (Cau_Key0
GD32H737/757/759 User Manual IINTF IN FIFO enabled interrupt flag 0: IN FIFO Interrupt not pending 1: IN FIFO Interrupt pending when CAUEN is 1 Key registers (CAU_KEY0..3(H / L)) 13.9.9. Address offset: 0x20 to 0x3C Reset value: 0x0000 0000 These registers have to be accessed by word (32-bit), and all of them must be written when BUSY is 0.
Page 454 GD32H737/757/759 User Manual KEY0L[31:16] KEY0L[15:0] CAU_KEY1H Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). KEY1H[31:16] KEY1H[15:0] CAU_KEY1L Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 455: Initial Vector Registers (Cau_Iv0
GD32H737/757/759 User Manual CAU_KEY2L Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). KEY2L[31:16] KEY2L[15:0] CAU_KEY3H Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). KEY3H[31:16]...
Page 456 GD32H737/757/759 User Manual This registers have to be accessed by word (32-bit), and all of them must be written when BUSY is 0. In DES / TDES mode, IV0H is the leftmost bits, and IV0L is the rightmost bits of the initialization vectors.
Page 457: Gcm Or Ccm Mode Context Switch Register X (Cau_Gcmccmctxsx) (X=0
GD32H737/757/759 User Manual CAU_IV1L Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). IV1L[31:16] IV1L[15:0] Bits Fields Descriptions IV0...1(H / L) The initialization vector for DES, TDES, AES 31:0 GCM or CCM mode context switch register x (CAU_GCMCCMCTXSx) 13.9.11.
Page 458 GD32H737/757/759 User Manual CTXx[15:0] Bits Fields Descriptions 31:0 CTXx[31:0] The internal status of the CAU core. Read and save the register data when a high- priority task is coming to be processed, and restore the saved data back to the registers to resume the suspended processing.
Page 459: Hash Acceleration Unit (Hau)
GD32H737/757/759 User Manual Hash Acceleration Unit (HAU) 14.1. Overview The hash acceleration unit is used for information security. The secure hash algorithm (SHA- 1, SHA-224, SHA-256), the message-digest algorithm (MD5) and the keyed-hash message authentication code (HMAC) algorithm are supported for various applications. The digest will...
Page 460: Figure 14-2. Datam Byte Swapping And Bit Swapping
GD32H737/757/759 User Manual types. Figure 14-1. DATAM No swapping and Half-word swapping word0 word0 WORD 0 (MSB) word1 word1 WORD 1 word2 word2 WORD 2 word3 word3 WORD 3 (LSB) No swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Half-word swapping Figure 14-2.
Page 461: Hau Core
GD32H737/757/759 User Manual 14.4. HAU core The hash acceleration unit is used to compute condensed information of input messages with secure hash algorithms. The digest result has a length of 160 / 224 / 256 / 128 bits for a...
Page 462: Digest Computing
GD32H737/757/759 User Manual set 1 to start the calculation of the digest of the last block. Data Padding Example: The input message is “HAU”, which ASCII hexadecimal code is: 484155 Then the VBL bits in the HAU_CFG register is set as decimal 24 because of the valid bit length.
Page 463: Hash Mode
GD32H737/757/759 User Manual  The intermediate block computing can be started when HAU_DI is filled with another new word of the next block.  The last block computing can be started when CALEN bit in the HAU_CFG register is 1.
Page 464: Transfer Data By Cpu
GD32H737/757/759 User Manual the high-prior task is finished, resume the suspended operation. When suspending the current task, it is necessary to save the context of the current task from registers to memory, and then the task can be resumed by restoring the context from memory to the HAU registers.
Page 465: Hau Interrupt
GD32H737/757/759 User Manual HAU_CTXS37 (HAU_CTXS0 ~ HAU_CTXS53 when HMAC operation is to be resumed) registers. Set DMAE bit of HAU_CTL register to 1, continue the operation from where it suspended before. Note: If the value of NWIF[3:0] bits of HAU_CTL register is 0, it means the context switch...
Page 466: Register Definition
GD32H737/757/759 User Manual 14.7. Register definition HAU base address: 0x4802 1400 Control register (HAU_CTL) 14.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ALGM[1] Reserved Reserved DINE NWIF[3:0] ALGM[0] DATAM[1:0] DMAE...
Page 467: Data Input Register (Hau_Di)
GD32H737/757/759 User Manual ALGM[0] Algorithm selection bit 0 This bit and bit 18 of CTL are written by software to select the SHA-1, SHA-224, SHA256 or the MD5 algorithm: 00: Select SHA-1 algorithm 01: Select MD5 algorithm 10: Select SHA224 algorithm...
Page 468: Configuration Register (Hau_Cfg)
GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). DI[31:16] DI[15:0] Bits Fields Descriptions 31:0 DI[31:0] Message data input When write to these registers, the current content pushed to IN FIFO and new value updates. When read, returns the current content.
Page 469: Data Output Register (Hau_Do0
GD32H737/757/759 User Manual 0x1F: Only bits [31:1] of the last data written to HAU_DI after data swapping are valid Note: These bits must be configured before setting the CALEN bit. Data output register (HAU_DO0..7) 14.7.4. Address offset: 0x0C Reset value: 0x0000 0000 The data output registers are read only registers.
Page 470 GD32H737/757/759 User Manual HAU_DO2 Address offset: 0x14 and 0x318 Reset value: 0x0000 0000 These registers have to be accessed by word (32-bit). DO2[31:16] DO2[15:0] HAU_DO3 Address offset: 0x18 and 0x31C Reset value: 0x0000 0000 These registers have to be accessed by word (32-bit).
Page 471: Interrupt Enable Register (Hau_Inten)
GD32H737/757/759 User Manual DO5[15:0] HAU_DO6 Address offset: 0x328 Reset value: 0x0000 0000 These registers have to be accessed by word (32-bit). DO6[31:16] DO6[15:0] HAU_DO7 Address offset: 0x32C Reset value: 0x0000 0000 These registers have to be accessed by word (32-bit).
Page 472: Status And Flag Register (Hau_Stat)
GD32H737/757/759 User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CCIE Calculation completion interrupt enable 0: Calculation completion interrupt is disabled 1: Calculation completion interrupt is enabled DIIE Data input interrupt enable 0: Data input interrupt is disabled...
Page 473 GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). CTXx[31:16] CTXx[15:0] Bits Fields Descriptions 31:0 CTXx[31:0] The complete internal status of the HAU core. Read and save the register data when a high-priority task is coming to be processed, and restore the saved data back to...
Page 474: Trigonometric Math Unit (Tmu)
GD32H737/757/759 User Manual Trigonometric Math Unit (TMU) Overview 15.1. The Trigonometric Math Unit (TMU) is a fully configurable block that execute common trigonometric and arithmetic operations. The TMU can reduce the burden of CPU, and it is usually used in motor control, signal processing and many other applications.
Page 475: Function Overview
GD32H737/757/759 User Manual The Post-process module converts and scales the data (x ) and writes the processed results into TMU_ODATA register. The contents of the TMU_ODATA register are in q1.31 or q1.15 format. Function overview 15.4. Data format and configuration 15.4.1.
Page 476: Mode Configuration
GD32H737/757/759 User Manual Table 15-2. Output data configuration OWIDTH bit ONUM bit Fixed format read operation to TMU_ODATA q1.31 Only one read operation q1.31 Two successive read operation q1.15 Only one read operation q1.15 Not available Mode configuration 15.4.2. The MODE[3:0] bit-field in TMU_CS register is used to configure the mode of the CORDIC- algorithm core.
Page 477 GD32H737/757/759 User Manual Table 15-4. Mode 0 description Parameter Range Description The angle θ in radians range from –π to π. The θ must be divide by π in software to convert it to the θ ∈[-1,1) First input data π...
Page 478: Table 15-5. Mode 1 Description
GD32H737/757/759 User Manual Mode 1: m*sin ( θ ) Mode 1 calculates the sine of an angle. This mode take two input datas and generate two ouput datas. Detailed information refer to Table 15-5. Mode 1 description Table 15-5. Mode 1 description...
Page 479: Table 15-6. Mode 2 Description
GD32H737/757/759 User Manual The scaling 128 is used for the input and output data in this example. Of course, other scaling, such as 101, can also be used. Mode 2: phase= atan2 (y,x) Mode 2 calculates the atan2(y,x) of a vector (x,y) . This mode take two input datas and generate two ouput datas.
Page 480: Table 15-7. Mode 3 Description
GD32H737/757/759 User Manual Mode 3: modulus=√x Mode 3 calculates the modulus √x of a vector (x,y). This mode take two input datas and generate two ouput datas. Detailed information refer to Table 15-7. Mode 3 description Table 15-7. Mode 3 description...
Page 481: Table 15-8. Mode 4 Description
GD32H737/757/759 User Manual Mode 4: tan Mode 4 calculates the tan (x). This mode take one input data and generate one ouput data. Detailed information refer to Table 15-8. Mode 4 description Table 15-8. Mode 4 description Parameter Range Description If x∈[-1,1), the software does not need to process it, and the...
Page 482: Table 15-10. Mode 6 Description
GD32H737/757/759 User Manual Parameter Range Description The output data is multiplied 2 to get the real Second output sinh (x) ∈ [ -0.683,0.683 ] hyperbolic sine of a hyperbolic angle ��. data The bit-field FACTOR[2:0] is configured as 3’b001 FACTOR[2:0] Note: The scaling factor FACTOR[2:0] must be 1.
Page 483: Table 15-11. Mode 7 Description
GD32H737/757/759 User Manual 2. The scaling factor f=3 b001 is written into FACTOR[2:0] bit-field in TMU_CS register. 3. The input data 0x4000 is written into TMU_IDATA. Then the TMU calculation starts. 4. When the ENDF flag is set to 1, reading the TMU_ODATA register can get the first output sinh (1.0)
Page 484: Table 15-12. Mode 8 Description
GD32H737/757/759 User Manual 8 description Table 15-12. Mode 8 description Parameter Range Description x∈[0.107,9.35], a scaling factor 2 −�� is applied in ∈[0.0535,0.875] Input data <(1- ). Then write softwate to ensure that to TMU_IDATA in q1.15 or q1.31 format.
Page 485: Tmu Operation Pending
GD32H737/757/759 User Manual Parameter Range Description <(1- ). Then write softwate to ensure that to TMU_IDATA in q1.15 or q1.31 format. √ x ∈[0.04,1] The output data is multiplied 2 to get the real √ x. Output data f∈ [ 0,2 ]...
Page 486: Zero-Overhead Mode
GD32H737/757/759 User Manual Note: After a reset, the second input data is +1 (0x7FFFFFFF). While an TMU operation is pending, the further contents written into TMU_IDATA or TMU_CS register will cover the original contents. The new TMU contents will be suspended, and the suspension of the original contents will be invalid.
Page 487 GD32H737/757/759 User Manual ENDF Reserved IWIDTH OWIDTH INUM ONUM WDEN RDEN Reserved FACTOR[2:0] ITRTNUM[3:0] MODE[3:0] Bits Fields Descriptions ENDF End of TMU operation flag 0: No TMU operation or TMU operation is ongoing 1: TMU operation ends and the output data has been written into TMU_ODATA register.
Page 488 GD32H737/757/759 User Manual Note: When the format of input data is q1.15 (IWIDTH=1) and the TMU mode need only one input data (INUM=0), the upper half-word of TMU_IDATA register is unused. ONUM The number of times that the TMU_ODATA needs to be read 0: One 32-bit read operation.
Page 489: Input Data Register (Tmu_Idata)
GD32H737/757/759 User Manual q1.15 format. ITRTNUM[3:0] Number of iterations This bit-field defines the number of iterations: ITRTNUM[3:0]*4. 0000: Reserved 0001: 4 iteration steps 0010: 8 iteration steps … 0110: 24 iteration steps 0111~1111: Reserved Note: the higher the number of iterations, the higher the accuracy.
Page 490: Output Data Register (Tmu_Odata)
GD32H737/757/759 User Manual data configuration Note: 1. When no TMU operation is is ongoing and the required number of arguments has been written, a new operation will be started automatically. 2. When the TMU operation is ongoing, the written data is suspended until the end of the TMU operation and the output data is read.
Page 491: Direct Memory Access Controller (Dma)
GD32H737/757/759 User Manual Direct memory access controller (DMA) 16.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the MCU, thereby increasing system performance by off-loading the MCU from copying large amounts of data and avoiding frequent interrupts to serve peripherals needing more data or having available data.
Page 492: Function Overview
GD32H737/757/759 User Manual – Multi-data mode: Pack/Unpack data when memory transfer width are different from peripheral transfer width. – Single-data mode: Read data from source when FIFO is empty and wirte data to destination when one data has been pushed into FIFO.
Page 493: Figure 16-2. Data Stream For Three Transfer Modes
GD32H737/757/759 User Manual and memory-to-memory, which is determined by the TM bits in the DMA_CHxCTL register, as listed in Table 16-1. Transfer mode. Table 16-1. Transfer mode Transfer mode TM[1:0] Source Destination DMA_CHxM0ADDR/ Peripheral to memory DMA_CHxPADDR DMA_CHxM1ADDR DMA_CHxM0ADDR/ Memory to peripheral...
Page 494: Peripheral Handshake
GD32H737/757/759 User Manual Peripheral handshake 16.3.2. To ensure a well-organized and efficient data transfer, a handshake mechanism is introduced between the DMA and peripherals, including a request signal and a acknowledge signal:  Request signal asserted by peripheral to DMA controller, indicating that the peripheral is ready to transmit or receive data.
Page 495 GD32H737/757/759 User Manual multi-data mode, if PWIDTH is not equal to MWIDTH, the DMA can automatically packs/unpacks data to achieve an integrated and correct data transfer operation. In single- data mode, MWIDTH is automatically locked as PWIDTH by hardware immediately after enable the DMA channel.
Page 496: Table 16-2. Cnt Configuration
GD32H737/757/759 User Manual into single transfer automatically. Table 16-2. CNT configuration PWIDTH MWIDTH 8-bit 16-bit Multiple of 2 8-bit 32-bit Multiple of 4 16-bit 32-bit Multiple of 2 Others Any value 1. If the circular mode is enabled by setting the CMEN bit in the DMA_CHxCTL register. The...
Page 497: Table 16-3. Fifo Counter Critical Value Configuration Rules
GD32H737/757/759 User Manual configuration, including single-data mode and multi-data mode. When the transfer mode is memory-to-memory, only multi-data mode is supported to implement the DMA data processing. Multi-data mode The multi-data mode is selected by configuring the MDMEN bit in the DMA_CHxFCTL register to ‘1’.
Page 498: Figure 16-4. Data Packing/Unpacking When Pwidth = '00
GD32H737/757/759 User Manual entirely fill the FIFO. Then DMA lanches memory burst transfers to pop three words from the FIFO depending on the FIFO counter critical value and a word is still remained in the FIFO. There is no enough space for a peripheral burst transfer and the FIFO counter critical value is not reached, which makes DMA transfer frozen.
Page 499: Address Generation
GD32H737/757/759 User Manual Suppose the CNT bits are 8, the PWIDTH bits are equal to ‘01’, and both PNAGA and MNAGA are set. The DMA transfer operations for different MWIDTH are shown in the Figure 16-5. Data packing/unpacking when PWIDTH = ‘01’.
Page 500: Circular Mode
GD32H737/757/759 User Manual base address registers (DMA_CHxPADDR, DMA_CHxM0ADDR, and DMA_CHxM1ADDR). In the increasing mode, the next address is euqal to the current address plus 1 or 2 or 4, depending on the transfer data width. In Multi-data mode with PBURST in the DMA_CHxCTL register is ‘00’, if PAIF in the DMA_CHxCTL register is enabled, the next peripheral address...
Page 501: Transfer Operation
GD32H737/757/759 User Manual Figure 16-7. DMA operation of switch-buffer mode MBS = 0 Enable the channel peripheral-to-memory FIFO memory buffer 0 Peripheral push data pop data Memory 0 transfer: transfer finish transfer finish MBS = 0 MBS = 1 FIFO...
Page 502: Transfer Finish
GD32H737/757/759 User Manual FIFO data and write to the peripheral. Transfer finish 16.3.8. The DMA transfer is finished automatically and the FTFIFx bit in the DMA_INTF0 or DMA_INTF1 register is set when one of the following situations occurs:  Transfer completion.
Page 503: Channel Configuration
GD32H737/757/759 User Manual  Memory-to-memory: The same as the peripheral-to-memory mode with the source memory transfer is implemented through the peripheral port. Error detection Three types error can disable the DMA transfer:  FIFO error: When a wrong FIFO configuration is detected, the DMA channel is disabled immediately without starting any transfers.
Page 504: Interrupts
GD32H737/757/759 User Manual be used, configure the DMA_CHxM0ADDR or DMA_CHxM1ADDR corresponding with the MBS bit in the DMA_CHxCTL register. Configure the DMA_CHxCNT register to set the total transfer data number. 10. Configure the CHEN bit with ‘1’ in the DMA_CHxCTL register to enable the channel.
Page 505: Flag
GD32H737/757/759 User Manual Flag bit Enable bit Clear bit Interrupt event DMA_INTF0 or DMA_CHxCTL or DMA_INTC0 or DMA_INTF1 DMA_CHxFCTL DMA_INTC1 exception FIFO error and FEEIF FEEIE FEEIFC exception These five events can be divided into three types:  Flag: Full transfer finish flag and half transfer finish flag.
Page 506: Error
GD32H737/757/759 User Manual Single-data mode exception This exception can be detected only when the single-data mode is enabled and the transfer mode is peripheral-to-memory. When a peripheral request is valid and the FIFO is not empty, there are two or more data items stored in the FIFO after responding the peripheral request, which could be a problem for the subsequent processing of the data and the single-data mode exception bit SDEIFx will be set.
Page 507 GD32H737/757/759 User Manual Register access error The register access error is detected only when the switch-buffer is enabled. If the software attempts to update a memory address register currently accessed by the DMA controller, a register access error is detected. For example, when the memory 0 buffer is the current source or destination, a write access on the DMA_CHxM0ADDR register could produce a register access error.
Page 508: Dma Request Mapping
GD32H737/757/759 User Manual and exception interrupt is set, an interrupt is generated. Figure 16-8. System connection of DMA0 and DMA1 ITCM ITCM DTCM DTCM Bus matrix Bus matrix AXI SRAM AXI SRAM RAM shared RAM shared SRAM0 SRAM0 SRAM1 SRAM1...
Page 509: Register Definition
GD32H737/757/759 User Manual 16.5. Register definition DMA0 base address: 0x4002 0000 DMA1 base address: 0x4002 0400 Interrupt flag register 0 (DMA_INTF0) 16.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved FTFIF3...
Page 510: Interrupt Flag Register 1 (Dma_Intf1)
GD32H737/757/759 User Manual 23/17/7/1 Reserved Must be kept at reset value. FIFO error and exception of channel x (x=0…3) 22/16/6/0 FEEIFx Hardware set and software cleared by writing 1 to the corresponding bit in DMA_INTC0 register. 0: FIFO error or exception has not occurred on channel x...
Page 511: Interrupt Flag Clear Register 0 (Dma_Intc0)
GD32H737/757/759 User Manual 1: Single data mode exception has occurred on channel x 23/17/7/1 Reserved Must be kept at reset value. FIFO error and exception of channel x (x=4…7) 22/16/6/0 FEEIFx Hardware set and software cleared by writing 1 to the corresponding bit in DMA_INTC1 register.
Page 512: Interrupt Flag Clear Register 1 (Dma_Intc1)
GD32H737/757/759 User Manual Interrupt flag clear register 1 (DMA_INTC1) 16.5.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved FTFIFC7 HTFIFC7 TAEIFC7 SDEIFC7 Reserved FEEIFC7 FTFIFC6 HTFIFC6 TAEIFC6 SDEIFC6 Reserved FEEIFC6 Reserved...
Page 513 GD32H737/757/759 User Manual PAIF MWIDTH[1:0] PWIDTH[1:0] MNAGA PNAGA CMEN TM[1:0] Reserved FTFIE HTFIE TAEIE SDEIE CHEN Bits Fields Descriptions 31:25 Reserved Must be kept at reset value. 24:23 MBURST[1:0] Transfer burst type of memory Software set and clear. 00: single burst...
Page 514 GD32H737/757/759 User Manual 00: Low 01: Medium 10: High 11: Ultra high These bits can not be written when CHEN is ‘1’. PAIF Peripheral address increment fixed Software set and clear. 0: The peripheral address increment is determined by PWIDTH 1: The peripheral address increment is fixed to 4 This bit can not be written when CHEN is ‘1’.
Page 515 GD32H737/757/759 User Manual Software set and clear. 0: Disable circular mode. 1: Enable circular mode This bit can not be written when CHEN is ‘1’. This bit is automatically locked as ‘1’ by hardware immediately after enable CHEN if SBMEN is configured to ‘1’.
Page 516: Channel X Counter Register (Dma_Chxcnt)
GD32H737/757/759 User Manual at which point this bit is read as 0. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer. Channel x counter register (DMA_CHxCNT) 16.5.6. x = 0...7, where x is a channel number Address offset: 0x14 + 0x18 ×...
Page 517: Channel X Memory 0 Base Address Register (Dma_Chxm0Addr)
GD32H737/757/759 User Manual These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. When PWIDTH is 01 (16-bit), the LSB of these bits is ignored. Access is automatically aligned to a half word address. When PWIDTH is 10 (32-bit), the two LSBs of these bits are ignored. Access is automatically aligned to a word address.
Page 518: Channel X Fifo Control Register (Dma_Chxfctl)
GD32H737/757/759 User Manual M1ADDR[15:0] Bits Fields Descriptions 31:0 M1ADDR[31:0] Memory 1 base address When MBS in the DMA_CHxCTL register is read as to ‘1’, these bits specific the memory base address accessed by DMA during the transmission. These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’ and MBS in the DMA_CHxCTL register is read as ‘1’.
Page 519 GD32H737/757/759 User Manual 001: One word 010: Two words 011: Three words 100: Empty 101: Full 110~111: Reserved These bits specific the number of data stored in FIFO during the transmission. When MDMEN is configured to ‘0’, these bits has no meaning.
Page 520: Master Direct Memory Access Controller (Mdma)
GD32H737/757/759 User Manual Master direct memory access controller (MDMA) 17.1. Overview The master direct memory access (MDMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the MCU, thereby increasing system performance by off-loading the MCU from copying large amounts of data and avoiding frequent interrupts to serve peripherals needing more data or having available data.
Page 521: Function Overview
GD32H737/757/759 User Manual  ® The AHB bus interface is used to access Cortex -M7 TCM memory. And only when the increment and data size are identical and lower than or equal to 32-bit, burst access is allowed. When the increment and data size is larger than 32 bits, burst access is prohibited.
Page 522: Figure 17-2. Connections Of The Four Modes
GD32H737/757/759 User Manual Transfer mode TRIGMOD[1:0] Multi-block transfer Link transfer  Buffer transfer can transmit up to 128 bytes at a time.  Block transfer can transmit a maximum of 64KB at a time. The number of bytes to be transferred can be configured by TBNUM[16:0] in the MDMA_CHxBTCFG register.
Page 523: Data Process
GD32H737/757/759 User Manual request sources source TRIGSEL[5:0] DMA1_CH2_TRIG DMA1_CH3_TRIG DMA1_CH4_TRIG DMA1_CH5_TRIG DMA1_CH6_TRIG DMA1_CH7_TRIG TLI_INT Reserved Reserved Reserved Reserved Reserved OSPI0_FT OSPI0_TC IPA_CLUT_TRIG IPA_TC_TRIG IPA_TWM_TRIG Reserved Reserved SDIO0_DATA_END SDIO0_BUF_END SDIO0_CMD_END OSPI1_FT OSPI1_TC Data process 17.3.1. Arbitration MDMA manages requests based on channel request priority through an arbiter. When more...
Page 524: Figure 17-3. Word, Halfword, Byte Order Exchange
GD32H737/757/759 User Manual Data type The word, halfword, and byte exchange operations on the target data can be configured by the WES/HWES/BES bits in the MDMA_CHxCTL0 register. The data exchange process is shown in Figure 17-3. Word, halfword, byte order exchange.
Page 525: Figure 17-5. Data Padding And Alignment (Source Less Than Destination)
GD32H737/757/759 User Manual Figure 17-4. Data padding and alignment (source greater than destination) word 4 write B0[7:0] @0x0 read B3B2B1B0[31:0] @0x0 word 3 write B4[7:0] @0x1 read B7B6B5B4[31:0] @0x4 write B8[7:0] @0x2 read B11B10B9B8[31:0] @0x8 write B12[7:0] @0x3 word 2...
Page 526: Address Generation
GD32H737/757/759 User Manual SWIDTH[1:0] = 00, DWIDTH[1:0] = 10, the unpacking process is shown in Figure 17-6. Data packing / unpacking. Figure 17-6. Data packing / unpacking read B0[7:0] @0x0 read B8[7:0] @0x8 word 4 read B1[7:0] @0x1 read B9[7:0] @0x9...
Page 527: Transfer Modes
GD32H737/757/759 User Manual address generation configuration. Table 17-3. Source and destination address generation configuration SIMOD[1:0] DIMOD[1:0] No increment No increment Increment of the source is Increment of the destination is SIOS DIOS decrement of the source is decrement of the destination is...
Page 528 GD32H737/757/759 User Manual When the buffer transfer is completed, the TCF bit in MDMA_CHxSTAT0 register will be set. The TCF bit can be cleared by writing 1 to the TCFC bit in MDMA_CHxSTATC register If TRIGMOD[1:0] is not 00 and the total number of data to be transferred is greater than 128 bytes, then the arbitrator manages the request event based on the MDMA channel request priority after each buffer transfer.
Page 529: Table 17-4. Update Mode Of Source And Destination Address
GD32H737/757/759 User Manual MDMA_CHxBTCFG register. When BRNUM[11:0] is not 0, the multi-block transfer mode is enabled. BRNUM[11:0] can be configured from 0 to 4095. When a block transfer is completed, the BRNUM value is reduced by 1. The source address and the destination address of the...
Page 530: Transfer Status
GD32H737/757/759 User Manual If the TRIGSEL[5:0] in the MDMA_CHxCTL1 register changes while loading the channel configuration register, the trigger source will be changed by hardware automatically. Note: In link transfer mode, the SWREQMOD bit and TRIGMOD[1:0] in the MDMA_CHxCFG register cannot be modified.
Page 531: Table 17-7. Mdma Interrupt Events
GD32H737/757/759 User Manual Error name Description MDTERR Mask data transmission error flag LDTERR Link data error flag Transmission error flag The transmission error flag (ERR) will be set when the following occurs:  A bus error occurred during MDMA read or write access.
Page 532: Figure 17-7. Mdma Interrupt Logic
GD32H737/757/759 User Manual Figure 17-7. MDMA interrupt logic CHTCFx CHTCIEx Interrupt BTCFx events BTCIEx GIFx BRTCFx Global interrupt events BRTCIEx ERRx ERRIEx TCFx TCIEx Note: "x" represents the the number of channels (corresponding to x=0...15).
Page 533: Register Definition
GD32H737/757/759 User Manual 17.4. Register definition MDMA base address: 0x52000000 Global interrupt flag register (MDMA_GINTF) 17.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by byte (8-bit), half-word (16-bit), word (32-bit). Reserved GIF15 GIF14 GIF13...
Page 534: Channel X Status Clear Register (Mdma_Chxstatc)
GD32H737/757/759 User Manual REQAF Channel x request active flag If the SWREQ bit in MDMA_CHxCTL0 is set, and CHEN is enabled, this bit will be set. When the request of channel x is completed, this bit is cleared by hardware.
Page 535: Channel X Status Register 1 (Mdma_Chxstat1)
GD32H737/757/759 User Manual Reserved TCFC BTCFC MBTCFC CHTCFC ERRC Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. TCFC Channel x buffer transfer complete flag clear 0: No effect. 1: Clear the TCF bit in the MDMA_CHxSTAT0 register by writing 1 to this bit.
Page 536: Channel X Control Register 0 (Mdma_Chxctl0)
GD32H737/757/759 User Manual When the block size is not an integer multiple of the source or destination data size, this bit will be set by hardware. And this bit is cleared by writing 1 to ERRC bit in MDMA_CHxSTATC register.
Page 537 GD32H737/757/759 User Manual Reserved HWES Reserved SMODEN PRIO[1:0] TCIE BTCIE MBTCIE CHTCIE ERRIE CHEN Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. SWREQ Software request When the channel is enabled, request for channel x can be activated by setting this bit.
Page 538: Channel X Configure Register (Mdma_Chxcfg)
GD32H737/757/759 User Manual 01: Medium 10: High 11: Ultra high Note: When the channel is enabled (CHEN=1), these bits cannot be modified. TCIE Buffer transfer complete interrupt enable This bit is set and cleared by software. 0: Buffer transfer complete interrupt disable.
Page 539 GD32H737/757/759 User Manual DBURST[ SBURST[2:0] DIOS[1:0] SIOS[1:0] DWIDTH[1:0] SWIDTH[1:0] DIMOD[1:0] SIMOD[1:0] Bits Fields Descriptions BWMOD Bufferable write mode This bit is set and cleared by software. 0: Bufferable write mode disable. 1: Bufferable write mode enable. Note: When the channel is enabled (CHEN=1), this bit cannot be modified.
Page 540 GD32H737/757/759 User Manual Reserved Reserved Note: When the packet is enabled (PKEN=1) or the source data size is equal to the destination data size, these bits is invalid. When the channel is enabled (CHEN=1), these bits cannot be modified. PKEN Pack enable This bit is set and cleared by software.
Page 541 GD32H737/757/759 User Manual 11: 64-bit Note: When the channel is enabled (CHEN=1), these bits cannot be modified. If DIOS < DWIDTH and DIMOD is not 00, the result will be unpredictable. SIOS[1:0] Offset size of source increment These bits are set and cleared by software.
Page 542: Channel X Block Transfer Configure Register (Mdma_Chxbtcfg)
GD32H737/757/759 User Manual Channel x block transfer configure register (MDMA_CHxBTCFG) 17.4.7. x = 0...15, where x is a channel number Address offset: 0x54 + 0x40 × x Reset value: 0x0000 0000 This register has to be accessed by byte (8-bit), half-word (16-bit), word (32-bit).
Page 543: Channel X Destination Address Register (Mdma_Chxdaddr)
GD32H737/757/759 User Manual SADDR[31:16] SADDR[15:0] Bits Fields Descriptions 31:0 SADDR[31:0] Source address Channel x destination address register (MDMA_CHxDADDR) 17.4.9. x = 0...15, where x is a channel number Address offset: 0x5C + 0x40 × x Reset value: 0x0000 0000 This register has to be accessed by byte (8-bit), half-word (16-bit), word (32-bit).
Page 544: Channel X Link Address Register (Mdma_Chxladdr)
GD32H737/757/759 User Manual value of these bits must be an integer multiple of DWIDTH. When BRNUM=0, these bits are invalid. Note: When the channel is enabled (CHEN=1), these bits cannot be modified. 15:0 SADDRUV[15:0] Source address update value These bits are used to configure the increment or decrement of the source address after the block transfer is completed.
Page 545: Channel X Mask Address Register (Mdma_Chxmaddr)
GD32H737/757/759 User Manual Reserved DBSEL SBSEL Reserved TRIGSEL[5:0] Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. DBSEL Destination bus select This bit is used to configure the destination bus for the selected channel x during write operations.
Page 546: Channel X Mask Data Register (Mdma_Chxmdata)
GD32H737/757/759 User Manual 31:0 MADDR[31:0] Mask address When the bit field is not 0, the DMA request is acknowledged by writing the MDATA value in the MDMA_CHxMDATA register to the address specified by MADDR. Channel x mask data register (MDMA_CHxMDATA) 17.4.14.
Page 547: Dma Request Multiplexer (Dmamux)
GD32H737/757/759 User Manual DMA request multiplexer (DMAMUX) 18.1. Overview DMAMUX is a transmission scheduler for DMA requests. The DMAMUX request multiplexer is used for routing a DMA request line between the peripherals / generated DMA request (from the DMAMUX request generator) and the DMA controller. Each DMAMUX request multiplexer channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs.
Page 548: Block Diagram
GD32H737/757/759 User Manual 18.3. Block diagram Figure 18-1. Block diagram of DMAMUX Request multiplexer Slave Port Channel 15 Channel 2 Channel 1 Peri_reqx To DMA controller: Channel 0 Reqx_out Sync Counter underrun: Reqx_in Evtx_out Configuration Register Input selector Synchronization inputs:...
Page 549: Function Overview
GD32H737/757/759 User Manual 18.5. Function overview As shown in Figure 18-1. Block diagram of DMAMUX, DMAMUX includes two sub-blocks:  DMAMUX request multiplexer. DMAMUX request multiplexer inputs (Reqx_in) source from: – Peripherals (Peri_reqx). – DMAMUX request generator outputs (Gen_reqx). DMAMUX request multiplexer outputs (Reqx_out) is connected to channels of DMA controller.
Page 550: Figure 18-2. Synchronization Mode
GD32H737/757/759 User Manual Note: The NBR[4:0] bits value shall only be written by software when both synchronization enable bit SYNCEN and event generation enable EVGEN bit of the corresponding request multiplexer channel x are disabled. When synchronization mode is enabled...
Page 551: Figure 18-3. Event Generation
GD32H737/757/759 User Manual be routed to the DMAMUX multiplexer channel output until a synchronization input event occurs again. Channel event generation Each DMA request line multiplexer channel has an event output called Evtx_out, which is the DMA request multiplexer counter underrun event. Signals Evt0_out ~ Evt3_out can be used for DMA request chaining.
Page 552: Dmamux Request Generator
GD32H737/757/759 User Manual DMAMUX request generator 18.5.2. The DMAMUX request generator produces DMA requests upon trigger input event. Its component unit is the request generator channels. DMA request trigger inputs are connected in parallel to all request generator channels. And there is a built-in DMAMUX request generator counter for each request generator channel.
Page 553: Interrupt
GD32H737/757/759 User Manual Set and configure the DMA channel x completely, except enabling the channel x. Set and configure the related DMAMUX channel y completely. Configure the CHEN bit with ‘1’ in the DMA_CHxCTL register to enable the DMA channel Interrupt 18.5.4.
Page 554: Table 18-2. Request Multiplexer Input Mapping
GD32H737/757/759 User Manual Request multiplexer input mapping A DMA request is sourced either from the peripherals or from the DMAMUX request generator, the sources can refer to Table 18-2. Request multiplexer input mapping, configured by the MUXID[7:0] bits in the DMAMUX_RM_CHxCFG register for the DMAMUX request multiplexer channel x.
Page 555 GD32H737/757/759 User Manual Request multiplexer channel input identification Source MUXID[7:0] TIMER2_UP Reserved TIMER2_TRG TIMER3_CH0 TIMER3_CH1 TIMER3_CH2 TIMER3_CH3 Reserved TIMER3_TRG TIMER3_UP I2C0_RX I2C0_TX I2C1_RX I2C1_TX SPI0_RX SPI0_TX SPI1_RX SPI1_TX USART0_RX USART0_TX USART1_RX USART1_TX USART2_RX USART2_TX TIMER7_CH0 TIMER7_CH1 TIMER7_CH2 TIMER7_CH3 TIMER7_MCH0 TIMER7_MCH1...
Page 556 GD32H737/757/759 User Manual Request multiplexer channel input identification Source MUXID[7:0] TIMER4_UP TIMER4_CMT TIMER4_TRG SPI2_RX SPI2_TX UART3_RX UART3_TX UART4_RX UART4_TX DAC_CH0 DAC_CH1 TIMER5_UP TIMER6_UP USART5_RX USART5_TX I2C2_RX I2C2_TX CAU_IN CAU_OUT HAU_IN UART6_RX UART6_TX UART7_RX UART7_TX SPI3_RX SPI3_TX SPI4_RX SPI4_TX SAI0_B0 SAI0_B1...
Page 557 GD32H737/757/759 User Manual Request multiplexer channel input identification Source MUXID[7:0] TIMER14_MCH0 TIMER14_UP TIMER14_TRG TIMER14_CMT TIMER15_CH0 TIMER15_MCH0 Reserved TIMER15_UP TIMER16_CH0 TIMER16_MCH0 Reserved TIMER16_UP ADC2 FAC_READ FAC_WRITE TMU_READ TMU_WRITE TIMER22_CH0 TIMER22_CH1 TIMER22_CH2 TIMER22_CH3 TIMER22_UP Reserved TIMER22_TRG TIMER23_CH0 TIMER23_CH1 TIMER23_CH2 TIMER23_CH3 TIMER23_UP Reserved...
Page 558 GD32H737/757/759 User Manual Request multiplexer channel input identification Source MUXID[7:0] TIMER31_CH1 TIMER31_CH2 TIMER31_CH3 Reserved TIMER31_UP TIMER31_TRG TIMER40_CH0 TIMER40_MCH0 TIMER40_CMT TIMER40_UP TIMER41_CH0 TIMER41_MCH0 TIMER41_CMT TIMER41_UP TIMER42_CH0 TIMER42_MCH0 TIMER42_CMT TIMER42_UP TIMER43_CH0 TIMER43_MCH0 TIMER43_CMT TIMER43_UP TIMER44_CH0 TIMER44_MCH0 TIMER44_CMT TIMER44_UP TIMER50_UP TIMER51_UP SAI1_B0 SAI1_B1...
Page 559: Table 18-3. Trigger Input Mapping
GD32H737/757/759 User Manual Request multiplexer channel input identification Source MUXID[7:0] TIMER40_CH1 TIMER40_TRG TIMER41_CH1 TIMER41_TRG TIMER42_CH1 TIMER42_TRG TIMER43_CH1 TIMER43_TRG TIMER44_CH1 TIMER44_TRG Trigger input mapping The DMA request trigger input for the DMAMUX request generator channel x is selected through the TID[5:0] bits in DMAMUX_RG_CHxCFG register, the sources can refer to Table 18-3.
Page 560: Table 18-4. Synchronization Input Mapping
GD32H737/757/759 User Manual Trigger input identification Source TID[5:0] EXTI_13 EXTI_14 EXTI_15 RTC_WAKEUP CMP0_OUTPUT CMP1_OUTPUT I2C0_WAKEUP I2C1_WAKEUP I2C2_WAKEUP I2C3_WAKEUP I2C0_INT_EVENT I2C1_INT_EVENT I2C2_INT_EVENT I2C3_INT_EVENT ADC2_INT Synchronization input mapping The synchronization input is selected by SYNCID[4:0] bits in the DMAMUX_RM_CHxCFG register, the sources can refer to Table 18-4.
Page 561 GD32H737/757/759 User Manual Synchronization input Source identification SYNCID[4:0] EXTI_10 EXTI_11 EXTI_12 EXTI_13 EXTI_14 EXTI_15 RTC_WAKEUP CMP0_OUTPUT I2C0_WAKEUP I2C1_WAKEUP I2C2_WAKEUP I2C3_WAKEUP...
Page 562: Register Definition
GD32H737/757/759 User Manual 18.6. Register definition DMAMUX base address: 0x4002 0800 Request multiplexer channel configuration register 18.6.1. (DMAMUX_RM_CHxCFG) x = 0...15, where x is a channel number Address offset: 0x00 + 0x04 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 563: Request Multiplexer Channel Interrupt Flag Register (Dmamux_Rm_Intf)
GD32H737/757/759 User Manual 1: Enable event generation SOIE Synchronization overrun interrupt enable 0: Disable interrupt 1: Enable interrupt MUXID[7:0] Multiplexer input identification Selects the input DMA request in multiplexer input sources. Request multiplexer channel interrupt flag register (DMAMUX_RM_INTF) 18.6.2. Address offset: 0x80 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 564: Request Generator Channel X Configuration Register (Dmamux_Rg_Chxcfg)
GD32H737/757/759 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SOIFCx Clear bit for synchronization overrun event flag of request multiplexer channel x. Writing 1 clears the corresponding overrun flag SOIFx in the DMAMUX_RM_INTF register.
Page 565: Request Generator Channel Interrupt Flag Register (Dmamux_Rg_Intf)
GD32H737/757/759 User Manual Reserved Must be kept at reset value. TID[5:0] Trigger input identification Selects the DMA request trigger input source. Request generator channel interrupt flag register (DMAMUX_RG_INTF) 18.6.5. Address offset: 0x140 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 566 GD32H737/757/759 User Manual Writing 1 clears the corresponding trigger overrun flag TOIFx in the DMAMUX_RG_INTF register.
Page 567: Debug (Dbg)
GD32H737/757/759 User Manual Debug (DBG) 19.1. Overview The GD32H7xx series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the Arm CoreSight™ module together with a ® daisy chained standard TAP controller. Debug and trace functions are integrated into the Cortex -M7.
Page 568: Jtag
GD32H737/757/759 User Manual JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JTAG function without NJTRST pin, then the PB3 can be used to other GPIO functions (NJTRST tied to 1 by hardware). If switch to SW debug mode, the PA15/PB3/PB4 are released to other GPIO functions.
Page 569 GD32H737/757/759 User Manual DP0[31:0], DP1[31:0]: Don’t care 2b’00 or 2b’01 NDBG[1:0] = 1b’0 JTAGNSW = DP0[31:0], DP1[31:0]: Don’t care NDBG[1:0] = 2b’00 1b’1 JTAGNSW = Normal JTAG DP0[31:0], DP1[31:0]: Don’t care NDBG[1:0] = 2b’01 1b’1 JTAGNSW = Secure JTAG DP0[31:0], DP1[31:0]: Efuse debug password value 3.
Page 570: Debug Reset
GD32H737/757/759 User Manual Debug reset 19.2.4. The JTAG-DP and SW-DP registers are in the power on reset domain. The system reset initializes the majority of the Cortex -M7, excluding NVIC and debug logic, (FPB, DWT, and ® ITM). The NJTRST reset can reset JTAG TAP controller only. So, it can perform debug feature under system reset.
Page 571: Register Definition
GD32H737/757/759 User Manual 19.4. Register definition DBG base address: 0xE00E1000 ID code register (DBG_ID) 19.4.1. Address offset: 0x00 Read only This register has to be accessed by word (32-bit). ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by software.
Page 572: Control Register1 (Dbg_Ctl1)
GD32H737/757/759 User Manual 01: Trace pin used in synchronous mode and the data length is 1 10: Trace pin used in synchronous mode and the data length is 2 11: Trace pin used in synchronous mode and the data length is 4.
Page 573: Control Register2 (Dbg_Ctl2)
GD32H737/757/759 User Manual Control register2 (DBG_CTL2) 19.4.4. Address offset: 0x3C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). I2C3_HOL I2C2_HOL I2C1_HOL I2C0_HOL Reserved Reserved TIMER51_ TIMER50_ TIMER31_ TIMER30_ TIMER23_ TIMER22_ TIMER6_ TIMER5_ TIMER4_ TIMER3_ TIMER2_...
Page 574 GD32H737/757/759 User Manual 1: Hold the TIMER50 counter for debug when core halted. TIMER31_HOLD TIMER31 hold bit This bit is set and reset by software. 0: no effect 1: Hold the TIMER31 counter for debug when core halted. TIMER30_HOLD TIMER30 hold bit This bit is set and reset by software.
Page 575: Control Register3 (Dbg_Ctl3)
GD32H737/757/759 User Manual 0: no effect 1: Hold the TIMER1 counter for debug when core halted. Control register3 (DBG_CTL3) 19.4.5. Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). TIMER44_ TIMER43_ TIMER42_ TIMER41_...
Page 576: Control Register4 (Dbg_Ctl4)
GD32H737/757/759 User Manual This bit is set and reset by software. 0: no effect 1: Hold the TIMER16 counter for debug when core halted. TIMER15_HOLD TIMER15 hold bit This bit is set and reset by software. 0: no effect 1: Hold the TIMER15 counter for debug when core halted.
Page 577 GD32H737/757/759 User Manual FWDGT_ RTC_HOL Reserved Reserved HOLD Reserved Bits Fields Descriptions 31:19 Reserved Must be kept at reset value. FWDGT_HOLD FWDGT hold bit This bit is set and reset by software. 0: no effect 1: Hold the FWDGT counter clock for debug when core halted.
Page 578: Analog-To-Digital Converter (Adc)
GD32H737/757/759 User Manual Analog-to-digital converter (ADC) 20.1. Overview A 12 / 14-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip. ADC0 has 20 external channels, 1 internal channel(DAC_OUT0 channel), ADC1 has 18 external channels, 3 internal channels(the battery voltage, V...
Page 579: Pins And Internal Signals
GD32H737/757/759 User Manual  Operation modes: Converts a single channel or scans a sequence of channels. – Single operation mode converts selected inputs once per trigger. – Continuous operation mode converts selected inputs continuously. – Discontinuous operation mode. – SYNC mode (the device with two ADCs).
Page 580: Function Overview
GD32H737/757/759 User Manual Description Name The negative reference voltage for the REF- ADC,V REF- ADCx_IN[19:0] Up to 20 external channels Note: V and V have to be connected to V and V , respectively. 20.4. Function overview Figure 20-1. ADC module block diagram...
Page 581: Dual Clock Domain Architecture
GD32H737/757/759 User Manual The internal analog calibration can be reset by setting the RSTCLB bit in ADC_CTL1 register. Calibration software procedure: Ensure that ADCON=1. Delay 14 CK_ADC to wait for ADC stability. Set RSTCLB (optional). Set CLB=1. Wait until CLB=0.
Page 582: Routine Sequence
GD32H737/757/759 User Manual Table 20-3. ADC differential channel pin matching ADC0 ADC1 ADC2 Differential channel n number PA1_C PA1_C PC3_C PA0_C PA0_C PC2_C PA1_C PA0_C PA1_C PA0_C PC3_C PC2_C PF11 PF12 PF13 PF14 PF10 PF12 PF11 PF14 PF13 PF10 null...
Page 583: Operation Modes
GD32H737/757/759 User Manual The ADC_RSQ0~ADC_RSQ8 registers specify the selected channels of the routine sequence. The RL[3:0] bits in the ADC_RSQ0 register specify the total conversion sequence length. Note: Although the ADC supports 22 multiplexed channels, the maximum length of the sequence is only 16.
Page 584: Figure 20-3. Continuous Operation Mode
GD32H737/757/759 User Manual Figure 20-3. Continuous operation mode Sample Routine trigger Convert Software procedure for continuous operation mode on a routine channel: Set the CTN bit in the ADC_CTL1 register. Configure RSQ0 with the analog channel number. Configure ADC_RSQx register.
Page 585: Figure 20-4. Scan Operation Mode, Continuous Disable
GD32H737/757/759 User Manual Figure 20-4. Scan operation mode, continuous disable Software procedure for scan operation mode on a routine sequence: Set the SM bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register Configure ADC_RSQx registers. Configure ETMRC[1:0] bits in the ADC_CTL1 register if in need.
Page 586: Conversion Result Threshold Monitor Function
GD32H737/757/759 User Manual Set the DISRC bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register. Configure DISNUM[2:0] bits in the ADC_CTL0 register. Configure ADC_RSQx registers. Configure ETMRC[1:0] bits in the ADC_CTL1 register if in need. Prepare the DMA module to transfer data from the ADC_RDATA (refer to the spec of the module).
Page 587: Sample Time Configuration
GD32H737/757/759 User Manual 14-bit Data storage mode Figure 20-7. Routine channel data D12 D11 D10 DAL=0 Routine channel data D13 D12 D11 D10 DAL=1 12-bit Figure 20-8. Data storage mode 6-bit resolution data storage mode is different from 14-bit/12-bit/10-bit/8-bit resolution data storage mode, shown as Figure 20-9.
Page 588: Dma Request
GD32H737/757/759 User Manual Table 20-4. Trigger source for routine channels for ADC0/ADC1/ADC2 ETMRC[1:0] Trigger Source Trigger Type 01, 10, 11 TRIGSEL Signal from TRIGSEL SWRCST Software trigger DMA request 20.4.11. The DMA request, which is enabled by the DMA bit of ADC_CTL1 register, is used to transfer data of routine sequence for conversion of more than one channel.
Page 589 GD32H737/757/759 User Manual TSVEN1 or TSVEN2 bit. The output voltage of the temperature sensor changes linearly with temperature. Because there is an offset, which is up to 45 °C and varies from chip to chip due to the chip production variation, the internal temperature sensor is more appropriate to detect temperature variations instead of absolute temperature.
Page 590: Battery Voltage Monitoring
GD32H737/757/759 User Manual 2) The sampling accuracy of high precison temperature sensor can be improved by means of hardware on chip over sampling or software averaging. Battery voltage monitoring 20.4.14. The V channel can be used to measure the backup battery voltage on the V pin.
Page 591: On-Chip Hardware Oversampling
GD32H737/757/759 User Manual 12.5 173.61 ns 222.22 ns 10.5 145.83 ns 194.5 ns 118.06 ns 166.67 ns Table 20-6. t timings depending on resolution for ADC2 CONV (min) CONV SMPL DRES[1:0] (ns) at (us) at CONV (ADC clock (ADC clock...
Page 592: Figure 20-11. 20-Bit To 16-Bit Result Truncation (For 12Bit Adc)
GD32H737/757/759 User Manual Figure 20-11. 20-bit to 16-bit result truncation (for 12bit ADC) Raw 20-bit data Shifting Truncation and rounding Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are simply truncated.
Page 593: Adc Sync Mode
GD32H737/757/759 User Manual Figure 20-14. Numerical example with 10-bits shift and rounding(for 14bit ADC) Raw 24-bit data Shifting(10 bit) Table 20-7. Some examples show the maximum output results for N and M combimations (grayed values indicates truncation) below gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF.
Page 594: Free Mode
GD32H737/757/759 User Manual In ADC sync mode, when the conversion is configured to be triggered by an external event, the external trigger must be disabled for ADC1. The converted data of routine sequence is stored in the ADC sync routine data register (ADC_SYNCDATA0 or ADC_SYNCDATA1).
Page 595: Routine Follow-Up Mode
GD32H737/757/759 User Manual ETMRC[1:0] the selected external trigger of ADC0. The triggers is selected by configuring the bits in the ADC_CTL1 register of ADC0. EOC interrupts (if enabled on the ADC interfaces) are generated at the end of conversion events according to the EOCM bit in the ADC_CTL1 register. The behavior of routine parallel mode is shown in the Figure 20-16.
Page 596: Use Dma In Adc Sync Mode
GD32H737/757/759 User Manual Figure 20-17. Routine follow-up mode on 1 channel in continuous operation mode ADC0 · · · · · · ADC1 Routine trigger Sample EOC(ADC0 ) Convert EOC(ADC1) Note: Do not convert the same channel on two ADCs at a given time (no overlapping sampling times for the two ADCs when converting the same channel).
Page 597: Adc Interrupts
GD32H737/757/759 User Manual  ADC0 and ADC1 work in routine follow-up mode (SYNCM=0111). 20.6. ADC interrupts The interrupt can be produced on one of the events:  End of conversion for routine sequence.  The analog watchdog event.  Overflow event.
Page 598: Register Definition
GD32H737/757/759 User Manual 20.7. Register definition ADC0 base address: 0x4001 2400 ADC1 base address: 0x4001 2800 ADC2 base address: 0x4001 2C00 Status register (ADC_STAT) 20.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 599: Control Register 0 (Adc_Ctl0)
GD32H737/757/759 User Manual 0: Conversion is not started 1: Conversion is started Set by hardware when routine sequence conversion starts. Cleared by software writing 0 to it. Reserved Must be kept at reset value. End flag of routine sequence conversion...
Page 600 GD32H737/757/759 User Manual 25:24 DRES[1:0] ADC data resolution for ADC0/ADC1 00: 14bit 01: 12bit 10: 10bit 11: 8bit ADC data resolution for ADC2 00: 12bit 01: 10bit 10: 8bit 11: 6bit RWD0EN Routine channel analog watchdog 0 enable 0: Routine channel analog watchdog 0 disable...
Page 601: Control Register 1 (Adc_Ctl1)
GD32H737/757/759 User Manual 00011: ADC channel 3 00100: ADC channel 4 00101: ADC channel 5 00110: ADC channel 6 00111: ADC channel 7 01000: ADC channel 8 01001: ADC channel 9 01010: ADC channel 10 01011: ADC channel 11 01100: ADC channel 12...
Page 602 GD32H737/757/759 User Manual 1: high-precision temperature sensor Channel enable Software start conversion of routine sequence . SWRCST Setting 1 on this bit starts a conversion of a routine sequence channels. It is set by software and cleared by software or by hardware immediately after the conversion starts.
Page 603 GD32H737/757/759 User Manual 0: Only at the end of a routine sequence conversions, the EOC bit is set. Overflow detection is disabled unless DMA=1. 1: At the end of each routine sequence conversion, the EOC bit is set. Overflow is...
Page 604: Watchdog High Threshold Register0 (Adc_Wdht0)
GD32H737/757/759 User Manual Watchdog high threshold register0 (ADC_WDHT0) 20.7.4. Address offset: 0x1C Reset value: 0x00FF FFFF This register has to be accessed by word (32-bit). Reserved WDHT0[23:16] WDHT0[15:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. High threshold for analog watchdog 0, For ADC0/ADC1 are WDHT0[23:0], for...
Page 605: Routine Sequence Register 1 (Adc_Rsq1)
GD32H737/757/759 User Manual Reserved RL[3:0] Reserved Reserved RSMP15[9:0] RSQ15[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 RL[3:0] Routine channel length. The total number of conversion in routine sequence equals to RL[3:0]+1. 19:15 Reserved Must be kept at reset value.
Page 606: Routine Sequence Register 2 (Adc_Rsq2)
GD32H737/757/759 User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 607: Routine Sequence Register 3 (Adc_Rsq3)
GD32H737/757/759 User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 608: Routine Sequence Register 4 (Adc_Rsq4)
GD32H737/757/759 User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 609: Routine Sequence Register 5 (Adc_Rsq5)
GD32H737/757/759 User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 610: Routine Sequence Register 6 (Adc_Rsq6)
GD32H737/757/759 User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 611: Routine Sequence Register 7 (Adc_Rsq7)
GD32H737/757/759 User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 612: Routine Sequence Register 8 (Adc_Rsq8)
GD32H737/757/759 User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 613: Routine Data Register (Adc_Rdata)
GD32H737/757/759 User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 614 GD32H737/757/759 User Manual Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:16 OVSR[9:0] Oversampling ratio This bit filed defines the number of oversampling ratio. ADC0/1 is 1x~1024x. ADC2 is 1X~256X. 10’d0: 1x(no oversampling) 10’d1: 2x 10’d2: 3x ……...
Page 615: Watchdog 1 Channel Selection Register (Adc_Wd1Sr)
GD32H737/757/759 User Manual This bit is set and cleared by software. 0: Oversampler disabled 1: Oversampler enabled Note: The software allows this bit to be written only when ADCON = 0 (this ensures that no conversion is in progress). Watchdog 1 Channel Selection Register (ADC_WD1SR) 20.7.17.
Page 616: Watchdog High Threshold Register1 (Adc_Wdht1)
GD32H737/757/759 User Manual AWD2CS[15:0] Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. 20:0 AWD2CS[20:0] Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2.
Page 617: Watchdog High Threshold Register2 (Adc_Wdht2)
GD32H737/757/759 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved WDLT1[23:16] WDLT1[15:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. Low threshold for analog watchdog 1. For ADC0/1 are WDLT1[23:0], for ADC2 is...
Page 618: Differential Mode Control Register (Adc_Difctl)
GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). Reserved WDLT2[23:16] WDLT2[15:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. Low threshold for analog watchdog 2. For ADC0/1 are WDLT2[23:0], for ADC2 is 23:0 WDLT2[23:0] WDLT2[7:0].
Page 619 GD32H737/757/759 User Manual Reset value: 0x0000 0000 This register is read only and provides a summary of the three ADCs. This register is not available in ADC1 and ADC2. This register has to be accessed by word (32-bit). ADC2_RO ADC2_ST...
Page 620: Sync Control Register (Adc_Syncctl)
GD32H737/757/759 User Manual ADC0_WDE2 This bit is the mirror image of the WDE2 bit of ADC0 ADC0_WDE1 This bit is the mirror image of the WDE1 bit of ADC0 ADC0_WDE0 This bit is the mirror image of the WDE0 bit of ADC0 Sync control register (ADC_SYNCCTL) 20.7.25.
Page 621: Sync Routine Data Register0 (Adc_Syncdata0)
GD32H737/757/759 User Manual 4'b1000:HCLK div2(sync clock mode) 4'b1001:HCLK div4(sync clock mode) 4'b1010:HCLK div6(sync clock mode) 4'b1011:HCLK div8(sync clock mode) 4'b1100:HCLK div10(sync clock mode) 4'b1101:HCLK div12(sync clock mode) 4'b1110:HCLK div14(sync clock mode) 4'b1111:HCLK div16(sync clock mode) All other values are reserved.
Page 622: Sync Routine Data Register1 (Adc_Syncdata1)
GD32H737/757/759 User Manual SYNCDATA1[15:0] SYNCDATA0[15:0] Bits Fields Descriptions 31:16 SYNCDATA1[15:0] Routine data1(slave adc routine data) in ADC sync mode. SYNCDMA[1:0] must be 2’b10. 15:0 SYNCDATA0[15:0] Routine data0 (master adc routine data) in ADC sync mode. SYNCDMA[1:0] must be 2’b10, Sync routine data register1 (ADC_SYNCDATA1) 20.7.27.
Page 623: Digital-To-Analog Converter (Dac)
GD32H737/757/759 User Manual Digital-to-analog converter (DAC) Overview 21.1. The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be set to 8-bit or 12 bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability, and DAC output buffer can be calibrated to improve output accuracy.
Page 624: Function Description
GD32H737/757/759 User Manual Figure 21-1. DAC block diagram DAC control register DTSELx[1:0] MODEx DAC_CALR extrnal OTVx trigger SWTRx DAC_ENx Control Sample logic and keep Buff DAC_OUTx Wave OUTx_DO OUTx_DH (optional) 12-bit 12-bit 12-bit Table 21-1. DAC pins Name Description Signal type...
Page 625: Dac Trigger
GD32H737/757/759 User Manual OUTx_R12DH, OUTx_L12DH and OUTx_R8DH registers. When the data is loaded by OUTx_R8DH register, only the MSB 8 bits are configurable, the LSB 4 bits are fored to 0. DAC trigger 21.3.4. The DAC external trigger is enabled by setting the DTENx bits in the DAC_CTL0 register. The...
Page 626: Dac Modes
GD32H737/757/759 User Manual Figure 21-2. DAC LFSR algorithm Triangle noise mode: in this mode, a triangle signal is added to the OUTx_DH value, and then the result is stored into the OUTx_DO register. The minimum value of the triangle signal is 0, while the maximum value of the triangle signal is (2 <<...
Page 627: Dac Output Voltage
GD32H737/757/759 User Manual samples. Without converting, the DAC output is tri-stated, so the overall power consumption can be reduced. In this mode, APB1 clock and IRC32K drive all the corresponding logic and the DAC core and registers, so that DAC can be used in Deep-sleep mode.
Page 628: Dma Request
GD32H737/757/759 User Manual Calibration will be effective when buffer is enable. During the calibration:  Buffer disconnect from external pin and on chip peripherals, and enter tri-stated.  The buffer will be used as a comparator to detect the intermediate code value 0x800,and compare it with V /2 through the internal bridge.
Page 629: Dac Low-Power Modes
GD32H737/757/759 User Manual in specific applications, two output channels can be configured in concurrent mode. In concurrent mode, the OUTx_DH and OUTx_DO value will be updated at the same time. There are three concurrent registers that can be used to load the OUTx_DH value: DACC_R8DH, DACC_R12DH and DACC_L12DH.
Page 630: Dac Registers
GD32H737/757/759 User Manual DAC registers 21.4. DAC base address: 0x4000 7400 Control register 0 (DAC_CTL0) 21.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). DDUDR DDMA Reserved CALEN1 DWBW1[3:0] DWM1[1:0] Reserved DTSEL1[1:0]...
Page 631 GD32H737/757/759 User Manual 0110: The bit width of the wave signal is 7 0111: The bit width of the wave signal is 8 1000: The bit width of the wave signal is 9 1001: The bit width of the wave signal is 10 1010: The bit width of the wave signal is 11 ≥1011: The bit width of the wave signal is 12...
Page 632: Software Trigger Register (Dac_Swt)
GD32H737/757/759 User Manual triangle is ((2<<(n-1))-1) in triangle noise mode, where n is the bit width of wave. 0000: The bit width of the wave signal is 1 0001: The bit width of the wave signal is 2 0010: The bit width of the wave signal is 3...
Page 633: Dac_Out0 12-Bit Right-Aligned Data Holding Register (Out0_R12Dh)
GD32H737/757/759 User Manual Reserved SWTR1 SWTR0 Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. SWTR1 DAC_OUT1 software trigger, cleared by hardware. 0: Software trigger disabled 1: Software trigger enabled SWTR0 DAC_OUT0 software trigger, cleared by hardware. 0: Software trigger disabled...
Page 634: Dac_Out0 8-Bit Right-Aligned Data Holding Register (Out0_R8Dh)
GD32H737/757/759 User Manual OUT0_DH[11:0] Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 OUT0_DH[11:0] DAC_OUT0 12-bit left-aligned data. These bits specify the data that is to be converted by DAC_OUT0. Reserved Must be kept at reset value.
Page 635: Dac_Out1 12-Bit Left-Aligned Data Holding Register (Out1_L12Dh)
GD32H737/757/759 User Manual 11:0 OUT1_DH[11:0] DAC_OUT1 12-bit right-aligned data. These bits specify the data that is to be converted by DAC_OUT1. DAC_OUT1 12-bit left-aligned data holding register (OUT1_L12DH) 21.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 636: Dac Concurrent Mode 12-Bit Right-Aligned Data Holding Register (Dacc_R12Dh)
GD32H737/757/759 User Manual DAC concurrent mode 12-bit right-aligned data holding register 21.4.9. (DACC_R12DH) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved OUT1_DH[11:0] Reserved OUT0_DH[11:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value.
Page 637: Dac Concurrent Mode 8-Bit Right-Aligned Data Holding Register (Dacc_R8Dh)
GD32H737/757/759 User Manual 15:4 OUT0_DH[11:0] DAC_OUT0 12-bit left-aligned data These bits specify the data that is to be converted by DAC_OUT0. Reserved Must be kept at reset value. DAC concurrent mode 8-bit right-aligned data holding register 21.4.11. (DACC_R8DH) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 638: Dac_Out1 Data Output Register (Out1_Do)
GD32H737/757/759 User Manual These bits, which are read only, storage the data that is being converted by DAC_OUT0. DAC_OUT1 data output register (OUT1_DO) 21.4.13. Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved...
Page 639: Dac Calibration Register (Dac_Calr)
GD32H737/757/759 User Manual 1: The offset correction value is lower than or equal to the calibration value. DDUDR1 DAC_OUT1 DMA underrun flag, set by hardware, cleared by software write 1. 0: no underrun occurred. 1: underrun occurred (Speed of DAC trigger is high than the DMA transfer).
Page 640 GD32H737/757/759 User Manual This register has to be accessed by word(32-bit). Reserved MODE1[2:0] Reserved MODE0[2:0] Bits Fields Descriptions 31:19 Reserved Must be kept at reset value. 18:16 MODE1[2:0] DAC_OUT1 mode. These bits can be written when bit DEN1=0 and bit CALEN1=0 in the DAC_CTL0 register, the write operation is invalid when DEN1=1 or CALEN1=1.
Page 641: Dac Sample And Keep Sample Time Register 0 (Dac_Skstr0)
GD32H737/757/759 User Manual 111: Buffer is disabled and DAC_OUT0 is connected to on chip peripherals. DAC sample and keep sample time Register 0 (DAC_SKSTR0) 21.4.17. Address offset: 0x40 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 642: Dac Sample And Keep Refresh Time Register (Dac_Skrtr)
GD32H737/757/759 User Manual Reserved TKEEP1[9: 0] rc_w1 Reserved TKEEP0[9: 0] rc_w1 Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:16 TKEEP1[9: 0] DAC_OUT1 keep time (only valid in Sample and keep mode). 15:10 Reserved Must be kept at reset value.
Page 643: Watchdog Timer (Wdgt)
GD32H737/757/759 User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 644: Function Overview
GD32H737/757/759 User Manual Function overview 22.1.3. The free watchdog consists of an 8-stage prescaler and a 12-bit down counter. Figure 22-1. Free watchdog block diagram shows the functional block of the free watchdog module. Figure 22-1. Free watchdog block diagram The free watchdog is enabled by writing the value (0xCCCC) to the control register (FWDGT_CTL), then counter starts counting down.
Page 645: Table 22-1. Min/Max Fwdgt Timeout Period At 32Khz (Irc32K)
GD32H737/757/759 User Manual Cortex™-M7 core halted (Debug mode). The FWDGT stops in Debug mode if the FWDGT_HOLD bit is set. Table 22-1. Min/max FWDGT timeout period at 32KHz (IRC32K) Min timeout (ms) RLD[11:0]= Max timeout (ms) RLD[11:0]= Prescaler divider PSC[2:0] bits...
Page 646: Register Definition
GD32H737/757/759 User Manual Register definition 22.1.4. FWDGT base address: 0x5800 4800 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 647 GD32H737/757/759 User Manual FWDGT_STAT register is set and the value read from this register is invalid. 000: 1/4 001: 1/8 010: 1/16 011: 1/32 100: 1/64 101: 1/128 110: 1/256 111: 1/256 If several prescaler values are used by the application, it is mandatory to wait until PUD bit has been reset before changing the prescaler value.
Page 648 GD32H737/757/759 User Manual Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. Watchdog counter window value update When a write operation to FWDGT_WND register ongoing, this bit is set and the value read from FWDGT_WND register is invalid.
Page 649 GD32H737/757/759 User Manual These bits are write protected. Write 0x5555 in the FWDGT_CTL register before writing these bits. If several window values are used by the application, it is mandatory to wait until WUD bit has been reset before changing the window value. However, after updating...
Page 650: Window Watchdog Timer (Wwdgt)
GD32H737/757/759 User Manual 22.2. Window watchdog timer (WWDGT) Overview 22.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 651: Figure 22-3. Window Watchdog Timing Diagram
GD32H737/757/759 User Manual The watchdog is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F(it implies that the CNT[6] bit should be set).
Page 652: Table 22-2. Min-Max Timeout Value At 150 Mhz
GD32H737/757/759 User Manual Table 22-2. Min-max timeout value at 150 MHz (f PCLK3 Min timeout value Max timeout value Prescaler divider PSC[1:0] CNT[6:0] =0x40 CNT[6:0]=0x7F 27.30 μs 1.75 ms 54.61 μs 3.50 ms 109.22 μs 6.99 ms 218.45 μs 13.98 ms If the WWDGT_HOLD bit in DBG module is cleared, the WWDGT continues to work even the ®...
Page 653: Register Definition
GD32H737/757/759 User Manual Register definition 22.2.4. WWDGT base address: 0x5000 3C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word(16-bit) or word(32-bit) Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 654 GD32H737/757/759 User Manual operation of 0 has no effect. PSC[1:0] Prescaler. The time base of the watchdog counter 00: (PCLK3 / 4096) / 1 01: (PCLK3 / 4096) / 2 10: (PCLK3 / 4096) / 4 11: (PCLK3 / 4096) / 8 WIN[6:0] The Window value.
Page 655: Real Time Clock (Rtc)
GD32H737/757/759 User Manual Real time clock (RTC) 23.1. Overview The RTC provides a time which includes hour / minute / second / sub-second and a calendar includes year / month / day / week day. The time and calendar are expressed in BCD code except sub-second.
Page 656: Function Overview
GD32H737/757/759 User Manual 23.3. Function overview Block diagram 23.3.1. Figure 23-1. Block diagram of RTC ALARM 1 Alarm-1 Flag ALARM 0 Alarm-0 Flag Alarm-0/1 Logic Output Block Diagram Selection Logic 512Hz RTC_CALIB RTC_OUT RTC_REFIN RTC_ALARM ck_apre (Default 256 Hz) ck_spre...
Page 657: Shadow Registers Introduction
GD32H737/757/759 User Manual 32(configured in RCU_CFG register). In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler. Asynchronous prescaler is mainly used for reducing power consumption.
Page 658: Configurable Periodic Auto-Wakeup Counter
GD32H737/757/759 User Manual Configurable periodic auto-wakeup counter 23.3.5. In the RTC block, there is a 16-bit down counter designed to generate periodic wakeup flag. This function is enabled by set the WTEN to 1 and can be running in power saving mode.
Page 659: Calendar Reading
GD32H737/757/759 User Manual Calendar initialization and configuration The prescaler and calendar value can be programmed by the following steps: Enter initialization mode (by setting INITM=1) and polling INITF bit until INITF=1. Program both the asynchronous and synchronous prescaler factors in RTC_PSC register.
Page 660 GD32H737/757/759 User Manual reading calendar time register and date register twice if the two values are equal, the value can be seen as the correct value if the two values are not equal, a third reading should performed the third value can be seen as the correct value RSYNF is asserted once every 2 RTC clock and at this time point, the shadow registers will be updated to current time and date.
Page 661: Resetting The Rtc
GD32H737/757/759 User Manual Resetting the RTC 23.3.8. There are two reset sources used in RTC unit: system reset and backup domain reset. System reset will affect calendar shadow registers and some bits of the RTC_STAT. When system reset is valid, the bits or registers mentioned before are reset to the default value.
Page 662: Rtc Reference Clock Detection
GD32H737/757/759 User Manual RTC reference clock detection 23.3.10. RTC reference clock detection is another way to increase the precision of RTC second. To enable this function, you should have an external clock source (50Hz or 60 Hz) which is more precise than LXTAL clock source.
Page 663 GD32H737/757/759 User Manual So using CMSK can mask clock cycles from 0 to 511 and thus the RTC frequency can be reduced by up to 487.1PPM. To increase the RTC frequency the FREQI bit can be set. If FREQI bit is set, there will be 512 additional cycles to be added during period time which means every 211/210/29(32/16/8 seconds) RTC clock insert one cycle.
Page 664: Time-Stamp Function
GD32H737/757/759 User Manual the measure is within 0.477PPM (0.5 RTCCLK cycles over 32s)  When the calibration period is 16 seconds(by setting CWND16 bit) In this configuration, CMSK[0] is fixed to 0 by hardware. Using exactly 16s period to measure the accuracy of the calibration 1Hz output can guarantee the measure is within 0.954PPM...
Page 665 GD32H737/757/759 User Manual mode or level detection mode with configurable filtering setting. The purposes of the tamper detect configuration are the following:  The default configuration will erase the RTC backup registers, BKP sram and RTDEC register  It can wakeup from DeepSleep and Standby modes, and generate an interrupt...
Page 666: Calibration Clock Output
GD32H737/757/759 User Manual detection before writing to the backup register and re-enable tamper detection after finish writing. Tamper detection is still running when V power is switched off if tamper is enabled. Note: Level detection mode with configurable filtering on tamper input detection When FLT bit is not reset to 0x0, the tamper detection is set to level detection mode and FLT bit determines the consecutive number of samples (2, 4 or 8) needed for valid level.
Page 667: Rtc Power Saving Mode Management
GD32H737/757/759 User Manual Table 23-1 RTC pin configuration and function TSEN function COEN TP0EN ALRMOUTTYPE OS[1:0] (output (time configuration (calibration (tamper (RTC_ALARM selection) stamp and pin function output) enabled) output type enabled) Alarm out 01 or 10 or 11 output open drain...
Page 668: Rtc Interrupts
GD32H737/757/759 User Manual RTC interrupts 23.3.18. All RTC interrupts are connected to the EXTI controller. Below steps should be followed if you want to use the RTC alarm/tamper/timestamp/auto wakeup interrupt: Configure enable corresponding interrupt line alarm/tamper/timestamp/auto wakeup event of EXTI and set the rising edge for triggering...
Page 669: Register Definition
GD32H737/757/759 User Manual 23.4. Register definition RTC base address: 0x5800 4000 Time register (RTC_TIME) 23.4.1. Address offset: 0x00 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register is write protected and can only be written in initialization state...
Page 670: Control Register (Rtc_Ctl)
GD32H737/757/759 User Manual Reserved YRT[3:0] YRU[3:0] DOW[2:0] MONT MONU[3:0] Reserved DAYT[1:0] DAYU[3:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 Year tens in BCD code 19:16 YRU[3:0] Year units in BCD code 15:13 DOW[2:0] Days of the week...
Page 671 GD32H737/757/759 User Manual 1: Enable Internal timestamp event COEN Calibration output enable 0: Disable calibration output 1: Enable calibration output 22:21 OS[1:0] Output selection This bit is used for selecting flag source to output 0x0: Disable output RTC_ALARM 0x1: Enable alarm0 flag output...
Page 672 GD32H737/757/759 User Manual ALRM0IE RTC alarm-0 interrupt enable 0: Disable alarm interrupt 1: Enable alarm interrupt TSEN Time-stamp function enable 0: Disable time-stamp function 1: Enable time-stamp function WTEN Auto-wakeup timer function enable 0: Disable function 1: Enable function ALRM1EN...
Page 673: Status Register (Rtc_Stat)
GD32H737/757/759 User Manual 0x6:0x7: ck_spre (default 1Hz) clock and 2 is added to wake-up counter. Status register (RTC_STAT) 23.4.4. Address offset: 0x0C System reset: Only INITM, INITF and RSYNF bits are set to 0. Others are not affected Backup domain reset value: 0x0000 0007 This register is writing protected except RTC_STAT[13:8].
Page 674 GD32H737/757/759 User Manual Wakeup timer flag Set by hardware when wakeup timer decreased to 0. Cleared by software writing 0. This flag must be cleared at least 1.5 RTC Clock periods before WTF is set to 1 again. ALRM1F Alarm-1 occurs flag Set to 1 by hardware when current time/date matches the time/date of alarm 1 setting value.
Page 675: Prescaler Register (Rtc_Psc)
GD32H737/757/759 User Manual 1: Wakeup timer update is allowed ALRM1WF Alarm 1 configuration can be write flag Set by hardware if alarm register can be wrote after ALRM1EN bit has reset. 0: Alarm registers programming is not allowed 1: Alarm registers programming is allowed...
Page 676: Alarm 0 Time And Date Register (Rtc_Alrm0Td)
GD32H737/757/759 User Manual WTRV[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 WTRV[15:0] Auto-wakeup timer reloads value. Every (WTRV[15:0]+1) ck_wut period the WTF bit is set after WTEN=1.The ck_wut is selected by WTCS[2:0] bits. Note: This configure case is forbidden: WTRV=0x0000 with WTCS[2:0]=0b011.
Page 677: Alarm 1 Time And Date Register (Rtc_Alrm1Td)
GD32H737/757/759 User Manual 1: PM 21:20 HRT[1:0] Hour tens in BCD code 19:16 HRU[3:0] Hour units in BCD code MSKM Alarm minutes mask bit 0: Not mask minutes field 1: Mask minutes field 14:12 MNT[2:0] Minutes tens in BCD code...
Page 678: Write Protection Key Register (Rtc_Wpk)
GD32H737/757/759 User Manual 0: Not mask hour field 1: Mask hour field AM/PM flag 0: AM or 24-hour format 1: PM 21:20 HRT[1:0] Hour tens in BCD code 19:16 HRU[3:0] Hour units in BCD code MSKM Alarm minutes mask bit...
Page 679: Shift Function Control Register (Rtc_Shiftctl)
GD32H737/757/759 User Manual This register has to be accessed by word (32-bit) Reserved SSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SSC[15:0] Sub second value This value is the counter value of synchronous prescaler. Second fraction value is...
Page 680: Time Of Time Stamp Register (Rtc_Tts)
GD32H737/757/759 User Manual Time of time stamp register (RTC_TTS) 23.4.12. Address offset: 0x30 Backup domain reset value: 0x0000 0000 System reset: no effect This register will record the calendar time when TSF is set to 1. Reset TSF bit will also clear this register.
Page 681: Sub Second Of Time Stamp Register (Rtc_Ssts)
GD32H737/757/759 User Manual Reserved DOW[2:0] MONT MONU[3:0] Reserved DAYT[1:0] DAYU[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:13 DOW[2:0] Days of the week MONT Month tens in BCD code 11:8 MONU[3:0] Month units in BCD code Reserved Must be kept at reset value.
Page 682: Tamper Register (Rtc_Tamp)
GD32H737/757/759 User Manual This register is write protected. This register has to be accessed by word (32-bit) Reserved FREQI CWND8 CWND16 Reserved CMSK[8:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. FREQI Increase RTC frequency by 488.5PPM...
Page 683 GD32H737/757/759 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. DISPU RTC_TAMPx pull up disable bit 0: Enable inner pull-up before sampling for pre-charge RTC_TAMPx pin 1: Disable pre-charge duration 14:13 PRCH[1:0] Pre-charge duration time of RTC_TAMPx This setting determines the pre-charge time before each sampling.
Page 684: Alarm 0 Sub Second Register (Rtc_Alrm0Ss)
GD32H737/757/759 User Manual 0: Low level triggers a tamper detection event 1: High level triggers a tamper detection event TP1EN Tamper 1 detection enable 0:Disable tamper 1 detection function 1:Enable tamper 1 detection function Reserved Must be kept at reset value.
Page 685: Alarm 1 Sub Second Register (Rtc_Alrm1Ss)
GD32H737/757/759 User Manual 0x2: SSC[1:0] is to be compared and all others are ignored 0x3: SSC[2:0] is to be compared and all others are ignored 0x4: SSC[3:0] is to be compared and all others are ignored 0x5: SSC[4:0] is to be compared and all others are ignored...
Page 686: Configuration Register (Rtc_Cfg)
GD32H737/757/759 User Manual 0x4: SSC[3:0] is to be compared and all others are ignored 0x5: SSC[4:0] is to be compared and all others are ignored 0x6: SSC[5:0] is to be compared and all others are ignored 0x7: SSC[6:0] is to be compared and all others are ignored...
Page 687: Backup Registers (Rtc_Bkpx) (X=0
GD32H737/757/759 User Manual Backup registers (RTC_BKPx) (x=0..31) 23.4.20. Address offset: 0x50~0xCC Backup domain reset: 0x0000 0000 System reset: no effect This register has to be accessed by word (32-bit) DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] Data These registers can be wrote or read by software. The content remains valid even in power saving mode because they can powered-on by VBAT.
Page 688: Timer (Timerx)
GD32H737/757/759 User Manual TIMER (TIMERx) Table 24-1. Timers (TIMERx) are divided into five sorts TIMER1/2/3/4/22/23/30/ TIMER14/40 TIMER15/ TIMER TIMER0/7 TIMER5/6/50/51 /41/42/43/44 General- TYPE Advanced General-L0 General-L3 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit(TIMER2/3/30/31) 32-bit (TIMER5/6) Counter 16-bit 16-bit 16-bit...
Page 689 GD32H737/757/759 User Manual TIMER1/2/3/4/22/23/30/ TIMER14/40 TIMER15/ TIMER TIMER0/7 TIMER5/6/50/51 /41/42/43/44 Master-slave ● ● ● × × management Inter ● ● ● × TRGO TO DAC Connection ● ● ● ● ● ● ● ● ● ● Debug Mode TIMERx ITI0...
Page 690 GD32H737/757/759 User Manual TIMERx ITI0 ITI1 ITI2 ITI3 ITI4 ITI5 ITI6 ITI7 ITI8 ITI9 ITI10 ITI11 ITI12 ITI13 ITI14 TIMER0_ TIMER2_ TIMER15 TIMER16 TIMER44 TRGO0 TRGO0 _CH0 _CH0 Only update events will generate a DMA request. TIMER5/6/50/51 do not have DMAS bit (DMA request source selection).
Page 691: Advanced Timer (Timerx, X=0, 7)
GD32H737/757/759 User Manual 24.1. Advanced timer (TIMERx, x=0, 7) Overview 24.1.1. The advanced timer module (TIMER0/7) is a eight-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 692: Block Diagram
GD32H737/757/759 User Manual Block diagram 24.1.3. Figure 24-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer, and Table 24-2. Advanced timer channel description introduces the input and output of the channels. Figure 24-1. Advanced timer block diagram...
Page 693: Figure 24-2. Normal Mode, Internal Clock Divided By 1
GD32H737/757/759 User Manual clock CK_TIMER is selected as timer clock source which is from module RCU. The default clock source is the CK_TIMER for driving the counter prescaler when TSCFGy[4:0] (y=0..9,15) = 5’b00000 in SYSCFG_TIMERxCFG(x=0,7) registers. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK.
Page 694: Figure 24-3. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32H737/757/759 User Manual source is setting the TSCFG6[4:0] to 0x8. Note that the ETI signal is derived from the ETI pin sampled by a digital filter. When the ETI signal is selected as the clock source, the trigger controller including the edge detection circuitry will generate a clock pulse on each ETI signal rising edge to clock the counter prescaler.
Page 695: Figure 24-4. Timing Diagram Of Up Counting Mode, Psc=0/2
GD32H737/757/759 User Manual TIMERx_SWEVG register, the counter value will be initialized to 0 and an update event will be generated. If the UPDIS bit in TIMERx_CTL0 register is set, the update event is disabled. When an update event occurs, all the registers (repetition counter register, auto reload register, prescaler register) are updated.
Page 696: Figure 24-5. Timing Diagram Of Up Counting Mode, Change Timerx_Car Ongoing
GD32H737/757/759 User Manual Figure 24-5. Timing diagram of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120...
Page 697: Figure 24-7. Timing Diagram Of Down Counting Mode, Change Timerx_Car Ongoing
GD32H737/757/759 User Manual Figure 24-6. Timing diagram of down counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 24-7.
Page 698: Figure 24-8. Timing Diagram Of Center-Aligned Counting Mode
GD32H737/757/759 User Manual Center-aligned counting mode In the center-aligned counting mode, the counter counts up from 0 to the counter reload value and then counts down to 0 alternatively. The timer module generates an overflow event when the counter counts to (TIMERx_CAR-1) in the count-up direction and generates an underflow event when the counter counts to 1 in the count-down direction.
Page 699 GD32H737/757/759 User Manual Figure 24-8. Timing diagram of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear...
Page 700: Figure 24-9. Repetition Counter Timing Diagram Of Center-Aligned Counting Mode
GD32H737/757/759 User Manual on the overflow or on the underflow depending on when the CREP0/1 register was written and when the counter was started. The update event is generated at overflow when the CREP0/1 was written before starting the counter and generated at underflow when the CREP0/1 was written after starting the counter.
Page 701: Figure 24-11. Repetition Counter Timing Diagram Of Down Counting Mode
GD32H737/757/759 User Manual Figure 24-11. Repetition counter timing diagram of down counting mode TIMER_CK CNT_CLK CNT_REG 00 63 00 63 00 63 00 63 Underflow Overflow TIMERx_CREP0 = 0x0 UPIF TIMERx_CREP0 = 0x1 UPIF TIMERx_CREP0 = 0x2 UPIF Capture/compare channels The advanced timer has eight independent channels which can be used as capture inputs or compare outputs.
Page 702: Figure 24-12. Input Capture Logic For Channel 0
GD32H737/757/759 User Manual Figure 24-12. Input capture logic for channel 0 Edge Detector Synchronizer Edge selector &inverter Filter Based on CH0P&MCH0P TIMER_CK CI0FE0 Rising/Falling CI0F_ED Capture CI1FE0 Clock Counter Prescaler Register Prescaler MCI0FE0 （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT...
Page 703: Figure 24-14. Output Compare Logic (When Mchxmsel = 2'00, X=0, 1, 2, 3)
GD32H737/757/759 User Manual Based on the input signal and quality of requested signal, configure compatible CHxCAPFLT or MCHxCAPFLT bit. Step2: Edge selection (CHxP and MCHxP bits in TIMERx_CHCTL2 register, MCHxFP[1:0] bits in TIMERx_MCHCTL2 register). Rising edge or falling edge, choose one by configuring CHxP and MCHxP bits or MCHxFP[1:0] bits.
Page 704: Figure 24-15. Output Compare Logic (When Mchxmsel = 2'11, X=0,1,2,3)
GD32H737/757/759 User Manual Figure 24-14. Output compare logic (when MCHxMSEL = 2’00, x=0, 1, 2, 3) OxCPRE/MOxCPRE Capture/ CNT>CHxCV/ Compare register MCHxCV CHxCV/MCHxCV Compare output Output enable and CNT=CHxCV/ CHx_O control polarity selector MCHxCV CHxCOMCTL/ CHxP,CHxEN/ CNT<CHxCV/ MCHx_O MCHxCOMCTL MCHxFP,MCHxEN...
Page 705 GD32H737/757/759 User Manual If the output of MOxCPRE is active(high) level, the output of MCHx_O is active(low) level; If the output of MOxCPRE is inactive(low) level, the output of MCHx_O is active(high) level. When MCHxMSEL=2’b11 and CHx_O and MCHx_O are output at the same time, the specific outputs of CHx_O and MCHx_O are related to the relevant bits (ROS, IOS, POE and DTCFG bits) in the TIMERx_CCHP register.
Page 706: Figure 24-16. Output-Compare In Three Modes
GD32H737/757/759 User Manual Figure 24-16. Output-compare in three modes CNT_CLK CNT_REG 03 04 03 04 03 04 Overflow OxCPRE OxCPRE OxCPRE PWM mode In the PWM output mode (by setting the CHxCOMCTL/ MCHxCOMCTL bit to 4’b0110 (PWM mode 0) or to 4’b0111(PWM mode 1)), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV/ TIMERx_MCHxCV registers.
Page 707 GD32H737/757/759 User Manual Figure 24-17. Timing diagram of EAPWM CARL CHxVAL PWM MODE0 OxCPRE PWM MODE1 OxCPRE Interrupt signal CHxIF CHxOF Figure 24-18. Timing diagram of CAPWM CARL CHxVAL PWM MO DE0 OxCPRE PWM MO DE1 OxCPRE Interrupt signal CAM=2'b01 down only...
Page 708: Table 24-3.The Composite Pwm Pulse Width
GD32H737/757/759 User Manual x output is forced high when the counter matches the value of CHxVAL. It is forced low when the counter matches the value of CHxCOMVAL_ADD. The PWM period is determined by (CARL + 0x0001) and the PWM pulse width is determined by the following table.
Page 709: Figure 24-19. Channel X Output Pwm With (Chxval < Chxcomval_Add)
GD32H737/757/759 User Manual Figure 24-19. Channel x output PWM with (CHxVAL < CHxCOMVAL_ADD) CARL CHxCOMVAL_ ADD=CARL CHxCOMVAL_ CHxVAL CHxVAL PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF...
Page 710: Figure 24-22. Channel X Output Pwm With Chxval Or Chxcomval_Add Exceeds Carl
GD32H737/757/759 User Manual CHxVAL = CARL CARL CHxVAL CHxCOMVAL_ADD CHxCOMVAL_ADD PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF CHxIF CHxCOMADDIF CHxCOMADDIF CARL CHxVAL CHxCOMVAL_ADD = 0 PWM MODE 1...
Page 711: Figure 24-24. Four Channels Outputs In Composite Pwm Mode
GD32H737/757/759 User Manual next counter next counter period period If more than one channels are configured in composite PWM mode, it is possible to fix an offset for the channel x match edge of each pair with respect to other channels. This behavior is useful in the generation of lighting PWM control signals where it is desirable that edges are not coincident with each other pair to help eliminate noise generation.
Page 712: Figure 24-25. Chx_O Output With A Pulse In Edge-Aligned Mode (Chxompsel≠2'B00)
GD32H737/757/759 User Manual  CHxOMPSEL = 2’b00, the OxCPRE signal is output normally with the configuration of CHxCOMCTL[3:0] bits; CHxOMPSEL = 2’b01, only the counter is counting up, the OxCPRE signal is output a  pulse when the match events occur, and the pulse width is one CK_TIMER clock cycle.
Page 713 GD32H737/757/759 User Manual Channel output prepare signal Figure 24-14. Output compare logic (when MCHxMSEL = 2’00, x=0, 1, 2, As is shown in Figure 24-15. Output compare logic (when MCHxMSEL = 2’11, x=0,1,2,3), when TIMERx is configured in compare match output mode, a middle signal named OxCPRE or MOxCPRE (channel x output or multi mode channel x output prepare signal) will be generated before the channel outputs signal.
Page 714: Table 24-4. Complementary Outputs Controlled By Parameters (Mchxmsel =2'B11)
GD32H737/757/759 User Manual When the the outputs of CHx_O and MCHx_O are complementary, there are three situations: output enable、output off-state and output disabled. The details are shown in Table 24-4. =2’b11). Complementary outputs controlled by parameters (MCHxMSEL Table 24-4. Complementary outputs controlled by parameters (MCHxMSEL =2’b11)
Page 715: Figure 24-27. Complementary Output With Dead Time Insertion
GD32H737/757/759 User Manual (4) ⊕: Xor calculate. (5) (!OxCPRE)：the complementary output of the OxCPRE signal. Dead time insertion The dead time insertion is enabled when MCHxMSEL=2’b11 and both CHxEN and MCHxEN are configured to 1’b1, it is also necessary to configure POEN to 1. The field named DTCFG defines the dead time delay that can be used for all channels.
Page 716: Figure 24-28. Break0 Function Logic Diagram
GD32H737/757/759 User Manual independent control of dead-time insertion function for each pair of channels. When the DTIENCHx(x=0..3) bit is “0”, the corresponding channels CHx_O and CHx_ON will not be inserted into the dead-time. Break function The MCHx_O output is the inverse of the CHx_O output when the MCHxMSEL=2’b11 (and the MCHxOMCTL bits are not used in the generation of the MCHx_O output).
Page 717: Figure 24-29. Break1 Function Logic Diagram
GD32H737/757/759 User Manual Figure 24-29. BREAK1 function logic diagram BREAK0 can be used to handle the faults of system sources, on-chip peripheral events and external sources. When a BREAK0 event occurs, the outputs is force at a inactive level, or at a predefined level (either active or inactive) after a deadtime duration.
Page 718: Figure 24-31. Output Behavior Of The Channel Outputs With The Break0 And Break1
GD32H737/757/759 User Manual used when the IOS =1 and ROS =1. Table 24-5. Output behavior of the channel in response to a BREAK0 and BREAK1 (the break input is high active) Output Status BREAK BREAK 0 inputs 1 inputs CHx_O...
Page 719: Table 24-6. Break Function Input Pins Locked/ Released Conditions
GD32H737/757/759 User Manual Locked break function The BRKINx(x=0..2) input pins of advanced timer have the locked break function, this function can be enabled by setting the BRK0LK and BRK1LK bits in the TIMERx_CCHP register. When the locked break function is enabled, the BRKINx(x=0..2) pins need to be configured to open-drain output mode with low level active (BRK0P/ BRK1P=0 and BRK0INxP/ BRK1INxP=0).
Page 720 GD32H737/757/759 User Manual Figure 24-32. BRKINx(x=0..2) pins logic with BREAK0 function CKM clock monitor LVD lock event LOCKUP_LOCK event SYSBIF BRK0G SRAM parity error event System source Flash ECC error requests BRK0EN HPDF_OUT BRK0HPDFEN Output Logic CMP0_OUT BRK0CMP0EN BRK0CMP0P Digital...
Page 721: Figure 24-33. Example Of Counter Operation In Decoder Interface Mode
GD32H737/757/759 User Manual Table 24-7. Counting direction in different quadrature decoder signals CI0FE0 CI1FE1 Counting mode Level Rising Falling Rising Falling CI1FE1=1 Down Quadrature decoder mode 0 TSCFG0[4:0]!= 5’b00000 CI1FE1=0 Down Quadrature decoder mode 1 CI0FE0=1 Down TSCFG1[4:0]!= 5’b00000 CI0FE0=0...
Page 722: Figure 24-35. Quadrature Decoder Signal Disconnection Detection Block Diagram
GD32H737/757/759 User Manual jump edges (rising or falling) of the CI0 and CI1 signals occur at the same time. When DECJDEN =1, if the level transitions of the two quadrature signals CI0 and CI1 occur simultaneously, the interrupt flag DECJIF is set, if DECJIE=1, the corresponding interrupt is generated.
Page 723: Figure 24-37. Example Of Counter Operation In Non-Quadrature Decoder Mode 1 With Ch0P=0
GD32H737/757/759 User Manual CH1P=0 When the non-quadrature decoder mode 1 is enabled, the CI0 signal is used as the count pulse( with the CH0P is used to select the counter edge) and the CI1 signal is used as the count direction selection. The more details is shown in Table 24-8.
Page 724: Figure 24-38. Hall Sensor Is Used For Bldc Motor
GD32H737/757/759 User Manual Hall sensor function Hall sensor is generally used to control BLDC motor, the advanced timer supports this function. Figure 24-38. Hall sensor is used for BLDC motor shows how to connect the timer and the motor. And two timers are needed. TIMER_in(Advanced/General L0 TIMER） is used to accept three rotor position signals of motor from hall sensors.
Page 725: Figure 24-39. Hall Sensor Timing Between Two Timers
GD32H737/757/759 User Manual Figure 24-39. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_INPUT CH1_INPUT CH2_INPUT CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead-time) CH0_O MCH0_O CH1_O MCH1_O CH2_O MCH2_O Master-slave management The TIMERx can be synchronized with a trigger in several modes including restart mode, pause mode and event mode and so on, which is selected by the TSCFGy[4:0] (y=3..7) in...
Page 726: Figure 24-40. Restart Mode
GD32H737/757/759 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 01001: CI3FE3 trigger input ETI) is used 01010: MCI0FEM0 selected as the trigger configuring ETFC and 01011: MCI1FEM1 source, configure the prescaler can be used 01100: MCI2FEM2 polarity by configuring ETPSC.
Page 727: Figure 24-42. Event Mode
GD32H737/757/759 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler count when a rising ETIFP is selected. ETFC = 0, ETI does edge of trigger input not filter. comes. Figure 24-42. Event mode TIMER_CK ETIFP CNT_REG TRGIF (1) The ETI signal can be input from an external ETI pin or provide by on-chip peripherals, plese refer Trigger selection for TIMER0_ETI register (TRIGSEL_TIMER0ETI) for more details.
Page 728: Figure 24-43. Single Pulse Mode Timerx_Chxcv=0X04, Timerx_Car=0X60
GD32H737/757/759 User Manual Figure 24-43. Single pulse mode TIMERx_CHxCV=0x04, TIMERx_CAR=0x60 TIMER_CK(CNT_CLK) Under SPM, counter stop CNT_REG O0CPRE Delayable single pulse mode Delayable single pulse mode is enabled by setting CHxCOMCTL[3:0]/ MCHxCOMCTL[3:0] in TIMERx_CHCTLx/ TIMERx_MCHCTLx registers. In this mode, the pulse width of OxCPRE/ MOxCPRE signal is determined by the TIMERx_CAR register.
Page 729: Figure 24-44. Delayable Single Pulse Mode With Timerx_Chxcv=0X00, Timerx_Car=0X60
GD32H737/757/759 User Manual greater than or equal to the value of TIMERx_CAR register. Figure 24-44. delayable single pulse mode with TIMERx_CHxCV=0x00, TIMERx_CAR=0x60 TIMER_CK (CNT_CLK) 60 00 60 00 CNT_REG O0CPRE Timers interconnection The timers can be internally connected for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the master mode while configuring another timer to be in the slave mode.
Page 730: Figure 24-45. Trigger Mode Of Timer0 Controlled By Enable Signal Of Timer2
GD32H737/757/759 User Manual 2. Configure TIMER0 in event mode and select the TIMER2 as TIMER0 input trigger source (TRCFG5[4:0] = 5b’00011 in the_SYSCFG_TIMER0CFG0 register). 3. Start TIMER2 by writing 1 to the CEN bit (TIMER2_CTL0 register). Figure 24-45. Trigger mode of TIMER0 controlled by enable signal of TIMER2 In this example, the update event can also be used as trigger source instead of enable signal.
Page 731: Figure 24-47. Pause Mode Of Timer0 Controlled By Enable Signal Of Timer2
GD32H737/757/759 User Manual divided internal clock only when TIMER2 is enabled. Both clock frequency of the counters are divided by 3 from TIMER_CK (f /3). Steps are shown as follows: PSC_CLK TIMER_CK 1. Configure TIMER2 in master mode and output enable signal as trigger output (MMC0=3’b001 in the TIMER2_CTL1 register).
Page 732: Figure 24-48. Pause Mode Of Timer0 Controlled By O0Cpre Signal Of Timer2
GD32H737/757/759 User Manual Figure 24-48. Pause mode of TIMER0 controlled by O0CPRE signal of TIMER2 TIMER2 TIMER_CK CNT_REG O0CPRE TIMER0 TRGIF CNT_REG Using an external trigger to start two timers synchronously.  The start of TIMER0 is triggered by the enable signal of TIMER2, and TIMER2 is triggered by its CI0 input rising edge.
Page 733: Figure 24-49. Trigger Timer0 And Timer2 By The Ci0 Signal Of Timer2
GD32H737/757/759 User Manual Figure 24-49. Trigger TIMER0 and TIMER2 by the CI0 signal of TIMER2 TIMER2 TIMER_CK TRGIF CNT_REG TIMER0 TRGIF CNT_CK CNT_REG Timer DMA mode Timer DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB.
Page 734 GD32H737/757/759 User Manual UPIFBU bit in the TIMERx_CNT register. This can avoid conflicts when reading the counter and interrupt processing. Timer debug mode ® When the Cortex -M7 is halted, and the TIMERx_HOLD configuration bit in DBG_CTL register is set to 1, the TIMERx counter stops.
Page 735: Registers Definition (Timerx, X=0, 7)
GD32H737/757/759 User Manual Registers definition (TIMERx, x=0, 7) 24.1.5. TIMER0 base address: 0x4001 0000 TIMER7 base address: 0x4001 0400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved...
Page 736 GD32H737/757/759 User Manual TIMERx_CHCTL0 register). Only when the counter is counting down, compare interrupt flag of channels can be set. 10: Center-aligned and counting up assert mode. The counter counts in center- aligned mode and channel is configured in output mode (CHxMS = 3’b000 in TIMERx_CHCTL0 register).
Page 737 GD32H737/757/759 User Manual pause mode or decoder mode. While in event mode, the hardware can set the CEN bit automatically. Control register 1 (TIMERx_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 738 GD32H737/757/759 User Manual Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from themaster timer. 19:16 Reserved Must be kept at reset value.
Page 739 GD32H737/757/759 User Manual CEN control bit is set or the trigger input in pause mode is high. There is a delay between the trigger input in pause mode and the TRGO0 output, except if the master-slave mode is selected. 010: Update. In this mode, the master mode controller selects the update event as TRGO0.
Page 740 GD32H737/757/759 User Manual When a channel does not have a complementary output, this bit has no effect. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SMC1...
Page 741 GD32H737/757/759 User Manual An event counter is used in the digital filter, in which a transition on the output occurs after N input events. This bit-field specifies the frequency used to sample ETIFP signal and the length of the digital filter applied to ETIFP.
Page 742 GD32H737/757/759 User Manual 0: Disabled 1: Enabled Note: This bit just used in composite PWM mode. CH2COMADDIE Channel 2 additional compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used in composite PWM mode. CH1COMADDIE Channel 1 additional compare interrupt enable...
Page 743 GD32H737/757/759 User Manual MCH3MSEL[1:0] = 2b’00). MCH2IE Multi mode channel 2 capture/compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used for channel input and output independent mode (when MCH2MSEL[1:0] = 2b’00). MCH1IE Multi mode channel 1 capture/compare interrupt enable...
Page 744 GD32H737/757/759 User Manual CH2DEN Channel 2 capture/compare DMA request enable 0: Disabled 1: Enabled CH1DEN Channel 1 capture/compare DMA request enable 0: Disabled 1: Enabled CH0DEN Channel 0 capture/compare DMA request enable 0: Disabled 1: Enabled UPDEN Update DMA request enable...
Page 745 GD32H737/757/759 User Manual Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH3COM CH2COM CH1COM CH0COM DECDISIF DECJIF MCH3OF MCH2OF MCH1OF MCH0OF MCH3IF MCH2IF MCH1IF MCH0IF Reserved ADDIF ADDIF...
Page 746 GD32H737/757/759 User Manual Refer to MCH0IF description MCH2IF Multi mode channel 2 capture/compare interrupt flag Refer to MCH0IF description MCH1IF Multi mode channel 1 capture/compare interrupt flag Refer to MCH0IF description MCH0IF Multi mode channel 0 capture/compare interrupt flag This flag is set by hardware and cleared by software.
Page 747 GD32H737/757/759 User Manual CH1OF Channel 1 over capture flag Refer to CH0OF description CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set. This flag is cleared by software.
Page 748 GD32H737/757/759 User Manual If channel 0 is in input mode, this flag is set when a capture event occurs. If channel 0 is in output mode, this flag is set when a compare event occurs. If channel 0 is set to input mode, this bit will be reset by reading TIMERx_CH0CV.
Page 749 GD32H737/757/759 User Manual Refer to MCH0G description. MCH2G Multi mode channel 2 capture or compare event generation. Refer to MCH0G description. MCH1G Multi mode channel 1 capture or compare event generation. Refer to MCH0G description. MCH0G Multi mode channel 0 capture or compare event generation.
Page 750 GD32H737/757/759 User Manual 1: Generate channel commutation update event CH3G Channel 3 capture or compare event generation Refer to CH0G description CH2G Channel 2 capture or compare event generation Refer to CH0G description CH1G Channel 1 capture or compare event generation...
Page 751 GD32H737/757/759 User Manual Bits Fields Descriptions CH1MS[2] Channel 1 I/O mode selection Refer to CH1MS[1:0]description CH0MS[2] Channel 0 I/O mode selection Refer to CH0MS[1:0] description CH1COMADDSEN Channel 1 additional compare output shadow enable Refer to CH0COMADDSEN description. CH0COMADDSEN Channel 0 additional compare output shadow enable When this bit is set, the shadow register of TIMERx_CH0COMV_ADD register which updates at each update event will be enabled.
Page 752 GD32H737/757/759 User Manual 011: Channel 1 is configured as input, IS1 is connected to ITS. This mode is working only if an internal trigger input is selected (through TSCFG15[4:0] bit-field in SYSCFG_TIMERxCFG2(x=0,7) register). 100: Channel 1 is configured as input, IS1 is connected to MCI1FE1.
Page 753 GD32H737/757/759 User Manual the O0CPRE is active. The O0CPRE is inactive again at the next update event; When counting down, the O0CPRE is active. When an trigger event occurs, the O0CPRE is inactive.The O0CPRE is active again at the next update event.
Page 754 GD32H737/757/759 User Manual Bits Fields Descriptions CH1MS[2] Channel 1 I/O mode selection Same as output compare mode. CH0MS[2] Channel 0 I/O mode selection Same as output compare mode. 29:16 Reserved Must be kept at reset value. 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description.
Page 755 GD32H737/757/759 User Manual Same as output compare mode. Channel control register 1 (TIMERx_CHCTL1) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH3COM CH2COM CH3COM CH2COM CH3MS CH2MS ADDSEN ADDSEN CTL[3] CTL[3] Reserved...
Page 756 GD32H737/757/759 User Manual Refer to CH2COMCTL[2:0] description CH3COMCEN Channel 3 output compare clear enable Refer to CH2COMCEN description 14:12 CH3COMCTL[2:0] Channel 3 compare output control Refer to CH2COMCTL[2:0] description CH3COMSEN Channel 3 output compare shadow enable Refer to CH2COMSEN description Reserved Must be kept at reset value.
Page 757 GD32H737/757/759 User Manual counter matches the output compare register TIMERx_CH2CV. 0011: Toggle on match. O2CPRE toggles when the counter matches the output compare register TIMERx_CH2CV. 0100: Force low. O2CPRE is forced low level. 0101: Force high. O2CPRE is forced high level.
Page 758 GD32H737/757/759 User Manual This bit cannot be modified when PROT[1:0] bit-field in TIMERx_CCHP register is 11 and CH2MS bit-field is 000. Reserved Must be kept at reset value. CH2MS[1:0] Channel 2 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection.
Page 759 GD32H737/757/759 User Manual 0100: f /2, N=6. SAMP 0101: f /2, N=8. SAMP 0110: f /4, N=6. SAMP 0111: f /4, N=8. SAMP 1000: f /8, N=6. SAMP 1001: f /8, N=8. SAMP 1010: f /16, N=5. SAMP 1011: f /16, N=6.
Page 760 GD32H737/757/759 User Manual CH3P Channel 3 capture/compare polarity Refer to CH0P description. CH3EN Channel 3 capture/compare enable Refer to CH0EN description. MCH2P Multi mode channel 2 output polarity Refer to MCH0P description. MCH2EN Multi mode channel 2 output enable Refer to MCH0EN description.
Page 761 GD32H737/757/759 User Manual 0: Channel 0 active high 1: Channel 0 active low When channel 0 is configured in input mode, these bits specifie the channel 0 input signal’s polarity. [MCH0P, CH0P] will select the active trigger or capture polarity for channel 0 input signals.
Page 762 GD32H737/757/759 User Manual Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock.
Page 763 GD32H737/757/759 User Manual Reserved Reserved CREP0[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP0[7:0] Counter repetition value 0 This bit-field specifies the update event generation rate. Each time the repetition counter counts down to zero, an update event will be generated. The update rate of the shadow registers is also affected by this bit-field when these shadow registers are enabled.
Page 764 GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). Reserved CH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH1VAL[15:0] Capture/compare value of channel 1 When channel 1 is configured in input mode, this bit-field indicates the counter value at the last capture event.
Page 765 GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). Reserved CH3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH3VAL[15:0] Capture/compare value of channel 3 When channel 3 is configured in input mode, this bit-field indicates the counter value at the last capture event.
Page 766 GD32H737/757/759 User Manual Note: Every write operation to this bit needs a delay of 1 APB clock to active. BRK1REL BREAK1 input released Refer to BRK0REL description. BRK0REL BREAK0 input released This bit is cleared by hardware when the BREAK0 input is invalid.
Page 767 GD32H737/757/759 User Manual 1010: f /16, N=5 SAMP 1011: f /16, N=6 SAMP 1100: f /16, N=8 SAMP 1101: f /32, N=5 SAMP 1110: f /32, N=6 SAMP 1111: f /32, N=8 SAMP This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is...
Page 768 GD32H737/757/759 User Manual input is not active. This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is BRK0P BREAK0 input signal polarity This bit specifies the polarity of the BREAK0 input signal. 0: BREAK0 input active low...
Page 769 GD32H737/757/759 User Manual 10: PROT mode 1. In addition to the registers in PROT mode 0, the CHxP/MCHxP bits in TIMERx_CHCTL2 register (if related channel is configured in output mode) , the ROS/IOS bits in TIMERx_CCHP register and the ROS/IOS bits in TIMERx_FCCHPx (x = 0..3) register are writing protected.
Page 770 GD32H737/757/759 User Manual Refer to MCH0MS[1:0] description. 29:25 Reserved Must be kept at reset value. MCH1COMCTL Multi mode channel 1 compare output control. Refer to MCH0COMCTL[2:0] description. 23:17 Reserved Must be kept at reset value. MCH0COMCTL Multi mode channel 0 compare output control.
Page 771 GD32H737/757/759 User Manual O0CPRE which drives CH0_O and MCH0_O, while the active level of CH0_O and MCH0_O depends on CH0P and MCH0P bits. 0000: Timing mode. The MO0CPRE signal keeps stable, independent of the comparison between register TIMERx_MCH0CV counter TIMERx_CNT.
Page 772 GD32H737/757/759 User Manual updates at each update event will be enabled. 0: Multi mode channel 0 output compare shadow disabled 1: Multi mode channel 0 output compare shadow enabled The PWM mode can be used without validating the shadow register only in single pulse mode (SPM bit in TIMERx_CTL0 register is set).
Page 773 GD32H737/757/759 User Manual 0010: f , N=4. SAMP CK_TIMER 0011: f , N=8. SAMP CK_TIMER 0100: f /2, N=6. SAMP 0101: f /2, N=8. SAMP 0110: f /4, N=6. SAMP 0111: f /4, N=8. SAMP 1000: f /8, N=6. SAMP 1001: f /8, N=8.
Page 774 GD32H737/757/759 User Manual Refer to MCH3MS[1:0]description. MCH2MS[2] Multi mode channel 0 I/O mode selection Refer to MCH2MS[1:0] description. 29:25 Reserved Must be kept at reset value. MCH3COMCTL Multi mode channel 3 compare output control. Refer to MCH2COMCTL[2:0] description. 23:17 Reserved Must be kept at reset value.
Page 775 GD32H737/757/759 User Manual Note: When multi mode channel 2 is configured in output mode, and the MCH2MSEL[1:0] = 2b’11, the CH2COMCTL[2:0] bit-field controls the behavior of O2CPRE which drives CH2_O and MCH2_O, while the active level of CH2_O and MCH2_O depends on CH2P and MCH2P bits.
Page 776 GD32H737/757/759 User Manual MCH2COMSEN Multi mode channel 2 output compare shadow enable When this bit is set, the shadow register of TIMERx_MCH2CV register, which updates at each update event will be enabled. 0: Multi mode channel 2 output compare shadow disabled...
Page 777 GD32H737/757/759 User Manual 0000: Filter disabled, f , N=1. SAMP 0001: f , N=2. SAMP CK_TIMER 0010: f , N=4. SAMP CK_TIMER 0011: f , N=8. SAMP CK_TIMER 0100: f /2, N=6. SAMP 0101: f /2, N=8. SAMP 0110: f /4, N=6.
Page 778 GD32H737/757/759 User Manual MCH3FP[1:0] Multi mode channel 3 capture/compare free polarity Refer to MCH0FP[1:0] description. MCH2FP[1:0] Multi mode channel 2 capture/compare free polarity Refer to MCH0FP[1:0] description. MCH1FP[1:0] Multi mode channel 1 capture/compare free polarity Refer to MCH0FP[1:0] description. MCH0FP[1:0]...
Page 779 GD32H737/757/759 User Manual 15:0 MCH0VAL[15:0] Capture/compare value of multi mode channel 0. When multi mode channel 0 is configured in input mode, this bit-field indicates the counter value at the last capture event. And this bit-field is read-only. When multi mode channel 0 is configured in output mode, this bit-field contains value to be compared to the counter.
Page 780 GD32H737/757/759 User Manual 31:16 Reserved Must be kept at reset value. 15:0 MCH2VAL[15:0] Capture/compare value of multi mode channel 2. When multi mode channel 2 is configured in input mode, this bit-field indicates the counter value at the last capture event. And this bit-field is read-only.
Page 781 GD32H737/757/759 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0COMVAL_ADD Additional compare value of channel 0 [15:0] When channel 0 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event.
Page 782 GD32H737/757/759 User Manual 31:16 Reserved Must be kept at reset value. 15:0 CH2COMVAL_ADD Additional compare value of channel 2 [15:0] When channel 2 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event.
Page 783 GD32H737/757/759 User Manual Bits Fields Descriptions CH3CPWMEN Channel 3 composite PWM mode enable 0: Disabled 1: Enabled CH2CPWMEN Channel 2 composite PWM mode enable 0: Disabled 1: Enabled CH1CPWMEN Channel 1 composite PWM mode enable 0: Disabled 1: Enabled CH0CPWMEN...
Page 784 GD32H737/757/759 User Manual 1: Quadrature decoder signal disconnection detection is enabled DECJDEN Quadrature decoder signal jump (the two signals jump at the same time) detection enable 0: Quadrature decoder signal jump detection is disabled 1: Quadrature decoder signal jump detection is enabled...
Page 785 GD32H737/757/759 User Manual CK_TIMER clock cycle. CH0OMPSEL[1:0] Channel 0 output match pulse select When the match events occurs, this bit is used to select the output of O0CPRE which drives CH0_O. 00: The O0CPRE signal is output normal with the configuration of CH0COMCTL[2:0] bits.
Page 786 GD32H737/757/759 User Manual DTIENCH0 Dead time inserted enable for channel 0 Enables the deadtime insertion in the outputs of MCH0_O and CH0_O. 0: Disabled 1: Enabled Free complementary channel protection register 0 (TIMERx_FCCHP0) Address offset: 0x7C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 787 GD32H737/757/759 User Manual state”. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. Reserved Must be kept at reset value. DTCFG[7:0] Dead time configure This bit-field controls the value of the dead-time, which is inserted before the output transitions.
Page 788 GD32H737/757/759 User Manual channel is output disabled. 1: “off-state” enabled. If the CH1EN or CH1NEN bit is reset, the corresponding channel is “off-state”. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. Idle mode “off-state” enable When POEN bit is reset (Idle mode), this bit can be set to enable the “off-state”...
Page 789 GD32H737/757/759 User Manual FCCHP2EN Free complementary channel protection register 2 enable 0: the ROS、IOS and DTCFG[7:0] bits in TIMERx_CCHP register is active 1: the ROS、IOS and DTCFG[7:0] bits in TIMERx_FCCHP2 register is active This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00.
Page 790 GD32H737/757/759 User Manual This register is used to configure the outputs of CH3_O/MCH3_O. FCCHP3 Reserved Reserved Reserved DTCFG[7:0] Bits Fields Descriptions FCCHP3EN Free complementary channel protection register 0 enable 0: the ROS、IOS and DTCFG[7:0] bits in TIMERx_CCHP register is active 1: the ROS、IOS and DTCFG[7:0] bits in TIMERx_FCCHP3 register is active...
Page 791 GD32H737/757/759 User Manual DTCFG [7:5] =3’b10x: DTvalue = (64+DTCFG [5:0])xt DTCFG [7:5] =3’b110: DTvalue = (32+DTCFG [4:0])xt DTCFG [7:5] =3’b111: DTvalue = (32+DTCFG [4:0])xt *16. This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00.
Page 792 GD32H737/757/759 User Manual 24:19 Reserved Must be kept at reset value. BRK0IN2P BREAK0 BRKIN2 alternate function input polarity This bit is used to configure the BRKIN2 input polarity, and the specitic polarity is determined by this bit and the BRK0P bit.
Page 793 GD32H737/757/759 User Manual 0: HPDF input disabled 1: HPDF input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is Reserved Must be kept at reset value. BRK0IN2EN BREAK0 BRKIN2 alternate function input enable 0: BRKIN2 alternate function input disabled...
Page 794 GD32H737/757/759 User Manual 0: CMP1 input signal will not be inverted (BRK1P =0, the input signal is active low; BRK1P =1, the input signal is active high) 1: CMP1 input signal will be inverted (BRK1P =0, the input signal is active high;...
Page 795 GD32H737/757/759 User Manual This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is 15:11 Reserved Must be kept at reset value. BRK1CMP1EN BREAK1 CMP1 enable 0: CMP1 input disabled 1: CMP1 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is...
Page 796 GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). BRK0CMP BRK0CMP Reserved Reserved BRK0IN2P BRK0IN1P BRK0IN0P BRK0HPD BRK0IN2E BRK0IN1E BRK0IN0E BRK0CMP BRK0CMP Reserved Reserved Bits Fields Descriptions 31:27 Reserved Must be kept at reset value. BRK0CMP1P BREAK0 CMP1 input polarity This bit is used to configure the CMP1 input polarity, and the specitic polarity is determined by this bit and the BRK0P bit.
Page 797 GD32H737/757/759 User Manual BRK0IN1P BREAK0 BRKIN1 alternate function input polarity This bit is used to configure the BRKIN1 input polarity, and the specitic polarity is determined by this bit and the BRK0P bit. 0: BRKIN1 input signal will not be inverted (BRK0P =0, the input signal is active low;...
Page 798 GD32H737/757/759 User Manual BRK0IN1EN BREAK0 BRKIN1 alternate function input enable 0: BRKIN1 alternate function input disabled 1: BRKIN1 alternate function input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is BRK0IN0EN BREAK0 BRKIN0 alternate function input enable...
Page 799 GD32H737/757/759 User Manual 1: CMP0 input signal will be inverted (BRK1P =0, the input signal is active high; BRK1P =1, the input signal is active low) This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is 24:19 Reserved Must be kept at reset value.
Page 800 GD32H737/757/759 User Manual 1: CMP0 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is BRK1HPDFEN BREAK1 HPDF input(hpdf_break[1]) enable 0: HPDF input disabled 1: HPDF input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is Reserved Must be kept at reset value.
Page 801 GD32H737/757/759 User Manual countinus to count to this value, the counter will timeout and the interrupt flag DECDISIF is set. If DECDISIE=1, the corresponding interrupt is generated. Note: This register is just used in quadrature decoder signal disconnection detection function(with DECDISDEN =1).
Page 802 GD32H737/757/759 User Manual This field defines the times of accessing(R/W) the TIMERx_DMATB register by DMA. 6’b000000: transfer 1 time 6’b000001: transfer 2 times … 6’b100101: transfer 38 times Reserved Must be kept at reset value. DMATA[5:0] DMA transfer access start address This field defines the start address of accessing the TIMERx_DMATB register by DMA.
Page 803 GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). Reserved CCUSEL CREPSEL CHVSEL OUTSEL Reserved Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. CCUSEL Commutation control shadow register update select This bit is valid only when the CCUC[2:0] bit-field are set to 100, 101 and 110.
Page 804: General Level0 Timer (Timerx, X=1,2,3,4,22,23,30,31)
GD32H737/757/759 User Manual 24.2. General level0 timer (TIMERx, x=1,2,3,4,22,23,30,31) Overview 24.2.1. The general level0 timer module (TIMER1/2/3/4/22/23/30/31) is a four-channel timer that supports input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The general level0 timer has a 16-bit or 32- bit counter that can be used as an unsigned counter.
Page 805: Function Overview
GD32H737/757/759 User Manual Figure 24-50. General Level 0 timer block diagram CI0F_ED,CI0FE0,CI1FE1 TIMERx_TRGO0 Trigger selector CH0_I Input Logic CH1_I Synchronizer&Filter Edge selector Prescaler CH2_I &Edge Detector CH3_I TIMERx_CHxCV Counter External Trigger Input logic On-chip ETI PSC_CLK sources Polarity selection TIMER_CK...
Page 806: Figure 24-51. Normal Mode, Internal Clock Divided By 1
GD32H737/757/759 User Manual Figure 24-51. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK 20 21 01 02 CNT_REG  TSCFG6[4:0] are setting to a nonzero value (external clock mode 0). External input pin is selected as timer clock source.
Page 807: Figure 24-52. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32H737/757/759 User Manual Figure 24-52. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK FA FB CNT_REG Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 808: Figure 24-54. Timing Chart Of Up Counting, Change Timerx_Car Ongoing
GD32H737/757/759 User Manual Figure 24-53. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 24-54.
Page 809: Figure 24-55. Timing Chart Of Down Counting Mode, Psc=0/2
GD32H737/757/759 User Manual Down counting mode In this mode, the counter counts down continuously from the counter reload value, which is defined in the TIMERx_CAR register, in a count-down direction. Once the counter reaches 0, the counter restarts to count again from the counter reload value. The counting direction bit DIR in the TIMERx_CTL0 register should be set to 1 for the down counting mode.
Page 810: Figure 24-56. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32H737/757/759 User Manual Figure 24-56. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118...
Page 811: Figure 24-57. Timing Chart Of Center-Aligned Counting Mode
GD32H737/757/759 User Manual updated. Figure 24-57. Timing chart of center-aligned counting mode shows the example of the counter behavior when TIMERx_CAR=0x99, TIMERx_PSC=0x0. Figure 24-57. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11...
Page 812: Figure 24-58. Input Capture Logic
GD32H737/757/759 User Manual enabled when CHxIE=1. Figure 24-58. Input capture logic Edge Detector Synchronizer Edge selector &inverter Filter Based on CH0P&CH0NP TIMER_CK CI0FE0 Rising/Falling CI0F_ED Capture Clock Counter CI1FE0 Register Prescaler Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other...
Page 813: Figure 24-59. Output Compare Logic (X=0,1,2,3)
GD32H737/757/759 User Manual The input capture mode can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connects to CI0 input. Select CI0 as channel 0 capture signals by setting CH0MS to 3’b001 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 814: Figure 24-60. Output-Compare Under Three Modes
GD32H737/757/759 User Manual Step3: Interrupt/DMA-request enables configuration by CHxIE/CHxDEN. Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. The TIMERx_CHxCV can be changed onging to meet the expected waveform. Step5: Start the counter by configuring CEN to 1. Figure 24-60. Output-compare under three modes shows the three compare modes toggle/set/clear.
Page 815 GD32H737/757/759 User Manual be always inactive in PWM mode 1 (CHxCOMCTL=4’b0111). Figure 24-61. Timing chart of EAPWM CARL CHxVAL PWM MODE0 OxCPRE PWM MODE1 OxCPRE Interrupt signal CHxIF CHxOF Figure 24-62. Timing chart of CAPWM CARL CHxVAL PWM MO DE0...
Page 816: Table 24-10.The Composite Pwm Pulse Width
GD32H737/757/759 User Manual If CHxCOMCTL = 4’b0111 (PWM mode 1) and DIR = 1’b0 (up counting mode), or CHxCOMCTL = 4’b0110 (PWM mode 0) and DIR = 1’b1 (down counting mode) the channel x output is forced high when the counter matches the value of CHxVAL. It is forced low when the counter matches the value of CHxCOMVAL_ADD.
Page 817: Figure 24-63. Channel X Output Pwm With (Chxval < Chxcomval_Add)
GD32H737/757/759 User Manual between 0 and CARL. Figure 24-63. Channel x output PWM with (CHxVAL < CHxCOMVAL_ADD) CARL CHxCOMVAL_ ADD=CARL CHxCOMVAL_ CHxVAL CHxVAL PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal...
Page 818: Figure 24-66. Channel X Output Pwm With Chxval Or Chxcomval_Add Exceeds Carl
GD32H737/757/759 User Manual CHxVAL = CARL CARL CHxVAL CHxCOMVAL_ADD CHxCOMVAL_ADD PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF CHxIF CHxCOMADDIF CHxCOMADDIF CARL CHxVAL CHxCOMVAL_ADD = 0 PWM MODE 1...
Page 819: Figure 24-68. Four Channels Outputs In Composite Pwm Mode
GD32H737/757/759 User Manual next counter next counter period period If more than one channels are configured in composite PWM mode, it is possible to fix an offset for the channel x match edge of each pair with respect to other channels. This behavior is useful in the generation of lighting PWM control signals where it is desirable that edges are not coincident with each other pair to help eliminate noise generation.
Page 820: Figure 24-69. Chx_O Output With A Pulse In Edge-Aligned Mode (Chxompsel≠2'B00)
GD32H737/757/759 User Manual  CHxOMPSEL = 2’b00, the OxCPRE signal is output normally with the configuration of CHxCOMCTL[3:0] bits; CHxOMPSEL = 2’b01, only the counter is counting up, the OxCPRE signal is output a  pulse when the match events occur, and the pulse width is one CK_TIMER clock cycle.
Page 821 GD32H737/757/759 User Manual Channel output prepare signal As is shown in Figure 24-59. Output compare logic (x=0,1,2,3), when TIMERx is configured in compare match output mode,a middle signal which is OxCPRE signal (Channel x output prepare signal) will be generated before the channel outputs signal. The OxCPRE signal type is defined by configuring the CHxCOMCTL bit.
Page 822: Figure 24-71. Example Of Counter Operation In Decoder Interface Mode
GD32H737/757/759 User Manual Table 24-11. Counting direction in different quadrature decoder signals CI0FE0 CI1FE1 Counting mode Level Rising Falling Rising Falling CI1FE1=1 Down Quadrature decoder mode 0 TSCFG0[4:0]!= 5’b00000 CI1FE1=0 Down Quadrature decoder mode 1 CI0FE0=1 Down TSCFG1[4:0]!= 5’b00000 CI0FE0=0...
Page 823: Figure 24-73. Quadrature Decoder Signal Disconnection Detection Block Diagram
GD32H737/757/759 User Manual DECJDEN bit (in TIMERx_CTL2register) to 1, which can be used to detect whether the level jump edges (rising or falling) of the CI0 and CI1 signals occur at the same time. When DECJDEN =1, if the level transitions of the two quadrature signals CI0 and CI1 occur simultaneously, the interrupt flag DECJIF is set, if DECJIE=1, the corresponding interrupt is generated.
Page 824: Figure 24-75. Example Of Counter Operation In Non-Quadrature Decoder Mode 1 With Ch0P=0
GD32H737/757/759 User Manual CH1P=0 When the non-quadrature decoder mode 1 is enabled, the CI0 signal is used as the count pulse( with the CH0P is used to select the counter edge) and the CI1 signal is used as the count direction selection. The more details is shown in Table 24-12.
Page 825: Table 24-13. Examples Of Slave Mode
GD32H737/757/759 User Manual Hall sensor function Refer to Advanced timer (TIMERx, x=0, 7)Hall sensor function. Master-slave management The TIMERx can be synchronized with a trigger in several modes including restart mode, pause mode and event mode and so on, which is selected by the TSCFGy[4:0] (y=3..7) in SYSCFG_TIMERxCFG(x=1..4,22,23,30,31).
Page 826: Figure 24-76. Restart Mode
GD32H737/757/759 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 24-76. Restart mode Pause mode TI0S = 0 (Non-xor) The counter will be [CH0NP=0, CH0P=0] paused when TSCFG4[4:0] CI0FE0 does not invert. Filter is bypassed in this trigger input is low, =5’b00110,...
Page 827 GD32H737/757/759 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler (1) The ETI signal can be input from an external ETI pin or provide by on-chip peripherals, plese refer Trigger selection for TIMER1_ETI register (TRIGSEL_TIMER1ETI) for more details.
Page 828: Figure 24-79. Single Pulse Mode Timerx_Chxcv = 0X04, Timerx_Car=0X60
GD32H737/757/759 User Manual Figure 24-79. Single pulse mode TIMERx_CHxCV = 0x04, TIMERx_CAR=0x60 TIMER_CK(CNT_CLK) Under SPM, counter stop CNT_REG O0CPRE Delayable single pulse mode Delayable single pulse mode is enabled by setting CHxCOMCTL[3:0] in TIMERx_CHCTLx registers. In this mode, the pulse width of OxCPRE signal is determined by the TIMERx_CAR register.
Page 829: Figure 24-80. Delayable Single Pulse Mode Timerx_Chxcv=0X00, Timerx_Car=0X60
GD32H737/757/759 User Manual Figure 24-80. delayable single pulse mode TIMERx_CHxCV=0x00, TIMERx_CAR=0x60 TIMER_CK (CNT_CLK) 60 00 60 00 CNT_REG O0CPRE Timers interconnection Please refer to Advanced timer (TIMERx, x=0, 7)Timers interconnection Timer DMA mode Timer DMA mode is the function that configures timer’s register by DMA module. The relative Corresponding registers are TIMERx_DMACFG and TIMERx_DMATB.
Page 830 GD32H737/757/759 User Manual register set to 1, the TIMERx counter stops.
Page 831: Registers Definition (Timerx, X=1,2,3,4,22,23,30,31)
GD32H737/757/759 User Manual Registers definition (TIMERx, x=1,2,3,4,22,23,30,31) 24.2.5. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 TIMER3 base address: 0x4000 0800 TIMER4 base address: 0x4000 0C00 TIMER22 base address: 0x4000 E000 TIMER23 base address: 0x4000 E400 TIMER30 base address: 0x4000 E800...
Page 832 GD32H737/757/759 User Manual ARSE Auto-reload shadow enable 0: The shadow register for TIMERx_CAR register is disabled 1: The shadow register for TIMERx_CAR register is enabled CAM[1:0] Counter align mode selection 00: No center-aligned mode (edge-aligned mode). The direction of the counter is specified by the DIR bit.
Page 833 GD32H737/757/759 User Manual – The slave mode controller generates an update event. 1: Update event disable. The buffered registers keep their value, while the counter and the prescaler are reinitialized if the UG bit is set or the slave mode controller generates a hardware reset event.
Page 834 GD32H737/757/759 User Manual 010: Update. In this mode, the master mode controller selects the update event as TRGO0. 011: Capture/compare pulse. In this mode, the master mode controller generates a TRGO0 pulse when a capture or a compare match occurs in channel 0.
Page 835 GD32H737/757/759 User Manual pause mode or event mode. But the TSCFGy[4:0](y=3,4,5) bits must not be 5b’01000 in this case. The external clock input will be ETIFP if external clock mode 0 and external clock mode 1 are enabled at the same time.
Page 836 GD32H737/757/759 User Manual DMA and interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH3COM CH2COM CH1COM CH0COM Reserved DECDISIE DECJIE ADDIE ADDIE ADDIE ADDIE Reserved TRGDEN Reserved CH3DEN CH2DEN CH1DEN CH0DEN...
Page 837 GD32H737/757/759 User Manual Note: This bit just used for quadrature decoder signal jump detection is enabled (when DECJDEN =1). Reserved Must be kept at reset value. TRGDEN Trigger DMA request enable 0: Disabled 1: Enabled Reserved Must be kept at reset value.
Page 838 GD32H737/757/759 User Manual CH0IE Channel 0 capture/compare interrupt enable 0: Disabled 1: Enabled UPIE Update interrupt enable 0: Disabled 1: Enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 839 GD32H737/757/759 User Manual enabled (when DECDISDEN =1). DECJIF Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag 0: No quadrature decoder signal jump interrupt occurred 1: Quadrature decoder signal jump interrupt occurred Note: This bit just used for quadrature decoder signal jump detection is enabled (when DECJDEN =1).
Page 840 GD32H737/757/759 User Manual If channel 0 is in input mode, this flag is set when a capture event occurs. If channel 0 is in output mode, this flag is set when a compare event occurs. If channel 0 is set to input mode, this bit will be reset by reading TIMERx_CH0CV.
Page 841 GD32H737/757/759 User Manual This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_INTF register will be set, related interrupt or DMA transfer can occur if enabled. 0: No generate a trigger event...
Page 842 GD32H737/757/759 User Manual CH1COM CH1COM CH0COM CH0COM CH1COMCTL[2:0] Reserved CH0COMCTL[2:0] Reserved CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions CH1MS[2] Channel 1 I/O mode selection Refer to CH1MS[1:0]description CH0MS[2] Channel 0 I/O mode selection Refer to CH0MS[1:0] description...
Page 843 GD32H737/757/759 User Manual 010: Channel 1 is configured as input, IS1 is connected to CI0FE1. 011: Channel 1 is configured as input, IS1 is connected to ITS. This mode is working only if an internal trigger input is selected (through TSCFG15[4:0] bit-field in SYSCFG_TIMERxCFG2(x=1..4,22,23,30,31) register).
Page 844 GD32H737/757/759 User Manual Note: In the composite PWM mode (CH0CPWMEN = 1’b1 and CH0MS = 3’b000), the PWM signal output in channel 0 is composited by TIMERx_CH0CV and TIMERx_CH0COMV_ADD. Please refer to Composite PWM mode for more details. If configured in PWM mode, the O0CPRE level changes only when the output compare mode switches from “Timing”...
Page 845 GD32H737/757/759 User Manual Same as output compare mode. CH0CAPFLT[3:0] Channel 0 input capture filter control An event counter is used in the digital filter, in which a transition on the output occurs after N input events. This bit-field specifies the frequency used to sample CI0 input signal and the length of the digital filter applied to CI0.
Page 846 GD32H737/757/759 User Manual CH3COM CH3COM CH2COM CH2COM CH3COMCTL[2:0] Reserved CH2COMCTL[2:0] Reserved CH3MS[1:0] CH2MS[1:0] CH3CAPFLT[3:0] CH3CAPPSC[1:0] CH2CAPFLT[3:0] CH2CAPPSC[1:0] Output compare mode: Bits Fields Descriptions CH3MS[2] Channel 3 I/O mode selection Refer to CH3MS[1:0]description. CH2MS[2] Channel 2 I/O mode selection Refer to CH2MS[1:0] description.
Page 847 GD32H737/757/759 User Manual 01: Channel 3 is configured as input, IS3 is connected to CI3FE3. 10: Channel 3 is configured as input, IS3 is connected to CI2FE3. 11: Channel 3 is configured as input, IS3 is connected to ITS, this mode is working only if an internal trigger input is selected (through TSCFG15[4:0] bit-field in SYSCFG_TIMERxCFG2(x=1..4,22,23,30,31) register).
Page 848 GD32H737/757/759 User Manual 1010~1111: Reserved. Note: In the composite PWM mode (CH2CPWMEN = 1’b1 and CH2MS = 3’b000), the PWM signal output in channel 2 is composited by TIMERx_CH2CV and TIMERx_CH2COMV_ADD. Please refer to Composite PWM mode for more details.
Page 849 GD32H737/757/759 User Manual Same as output compare mode. CH2CAPFLT[3:0] Channel 2 input capture filter control An event counter is used in the digital filter, in which a transition on the output occurs after N input events. This bit-field specifies the frequency used to sample CI2 input signal and the length of the digital filter applied to CI2.
Page 850 GD32H737/757/759 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH3NP Channel 3 complementary capture/compare polarity Refer to CH0NP description. Reserved Must be kept at reset value. CH3P Channel 3 capture/compare function polarity Refer to CH0P description...
Page 851 GD32H737/757/759 User Manual 0: Channel 0 active high 1: Channel 0 active low When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity. [CH0NP, CH0P] will select the active trigger or capture polarity for CI0FE0 or CI1FE0.
Page 852 GD32H737/757/759 User Manual Counter register (TIMERx_CNT)(TIMERx,x= 1,4,22,23) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CNT[31] CNT[30:16] UPIFBU rw /r CNT[15:0] UPIFBUEN = 0: Bits Fields Descriptions 31:0 CNT[31:0] This bit-field indicates the current counter value. Writing to this bit-field can change the value of the counter.
Page 853 GD32H737/757/759 User Manual 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock. The value of this bit-field will be loaded to the corresponding shadow register at every update event.
Page 854 GD32H737/757/759 User Manual When channel 0 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event. Channel 1 capture/compare value register (TIMERx_CH1CV)
Page 855 GD32H737/757/759 User Manual 15:0 CH2VAL[15:0] Capture/compare value of channel 2 When channel 2 is configured in input mode, this bit-field indicates the counter value at the last capture event. And this bit-field is read-only. When channel 2 is configured in output mode, this bit-field contains value to be compared to the counter.
Page 856 GD32H737/757/759 User Manual Bits Fields Descriptions 31:16 CH0COMVAL_ADD Additional compare value of channel 0 (bit 16 to 31) [31:16] This bit-field only for TIMER1/ 4/ 22/ 23. 15:0 CH0COMVAL_ADD Additional compare value of channel 0 [15:0] When channel 0 is configured in output mode, this bit-field contains value to be compared to the counter.
Page 857 GD32H737/757/759 User Manual Bits Fields Descriptions 31:16 CH2COMVAL_ADD Additional compare value of channel 2 (bit 16 to 31) [31:16] This bit-field only for TIMER1/ 4/ 22/ 23. 15:0 CH2COMVAL_ADD Additional compare value of channel 2 [15:0] When channel 2 is configured in output mode, this bit-field contains value to be compared to the counter.
Page 858 GD32H737/757/759 User Manual CH3OMPSEL[1:0] CH2OMPSEL[1:0] CH1OMPSEL[1:0] CH0OMPSEL[1:0] Reserved Bits Fields Descriptions CH3CPWMEN Channel 3 composite PWM mode enable 0: Disabled 1: Enabled CH2CPWMEN Channel 2 composite PWM mode enable 0: Disabled 1: Enabled CH1CPWMEN Channel 1 composite PWM mode enable...
Page 859 GD32H737/757/759 User Manual 13:12 CH2OMPSEL[1:0] Channel 2 output match pulse select When the match events occurs, this bit is used to select the output of O2CPRE which drives CH2_O. 00: The O2CPRE signal is output normal with the configuration of CH2COMCTL [2:0] bits.
Page 860 GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). WDGPER[31:16] WDGPER[15:0] Bits Fields Descriptions 31:0 WDGPER[31:0] Watchdog counter period value This register contains the period of the two watchdog counter. When the counters countinus to count to this value, the counter will timeout and the interrupt flag DECDISIF is set.
Page 861 GD32H737/757/759 User Manual specifies the address just accessed. And then the address of the second access to the TIMERx_DMATB register will be (start address + 0x4). 6’b000000: TIMERx_CTL0 6’b000001: TIMERx_CTL1 … In a word: start address = TIMERx_CTL0 + DMATA*4...
Page 862 GD32H737/757/759 User Manual CHVSEL Write CHxVAL register selection bit This bit-field is set and reset by software. 1: If the value to be written to the CHxVAL register is the same as the value of CHxVAL register, the write access is ignored.
Page 863: General Level3 Timer (Timerx, X=14,40,41,42,43,44)
GD32H737/757/759 User Manual General level3 timer (TIMERx, x=14,40,41,42,43,44) 24.3. Overview 24.3.1. The general level3 timer module (TIMER14/40/41/42/43/44) is a three-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The general level3 timer has a 16-bit counter that can be used as an unsigned counter.
Page 864: Function Overview
GD32H737/757/759 User Manual configuration of the general level3 timer. Figure 24-81. General level3 timer block diagram CI0F_ED,CI0FE0,CI1FE1 TIMERx_TRGO0 Trigger selector CH0_I Input Logic Synchronizer & Filter Edge selector Prescaler CH1_I & Edge Detector TIMERx_CHxCV/ Counter TIMERx_MCHxCV PSC_CLK TIMER_CK DMA REQ/ACK...
Page 865: Figure 24-82. Normal Mode, Internal Clock Divided By 1
GD32H737/757/759 User Manual available value, the internal clock TIMER_CK is the counter prescaler driving clock source. Figure 24-82. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG 20 21 01 02 ...
Page 866: Figure 24-83. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32H737/757/759 User Manual Figure 24-83. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK FA FB CNT_REG Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 867: Figure 24-85. Timing Diagram Of Up Counting Mode, Change Timerx_Car On The Go
GD32H737/757/759 User Manual the counter behavior for different clock prescaler factor when TIMERx_CAR=0x99. Timing diagram of up counting mode, PSC=0/2 Figure 24-84. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2...
Page 868: Figure 24-86. Repetition Timechart For Up-Counter
GD32H737/757/759 User Manual Counter repetition The general timer has two repetition counter TIMERx_CREP0/1, which can be selected by configuring the CPERSEL bit in the TIMERx_CFG register. The CPEP[7:0] bit-field is 8bits, the CPEP[31:0] bit-field is 32bits and can be read on the fly.
Page 869: Figure 24-87. Input Capture Logic For Channel 0
GD32H737/757/759 User Manual TIMERx_MCHxCV(x=0, 1) registers, at the same time the CHxIF/ MCHxIF(x=0, 1) bits are set and the channel interrupt is generated if it is enabled when CHxIE/ MCHxIE =1(x=0, 1). Figure 24-87. Input capture logic for channel 0...
Page 870: Figure 24-89. Output Compare Logic (When Mchxmsel = 2'00, X=0)
GD32H737/757/759 User Manual Based on the input signal and quality of requested signal, configure compatible CHxCAPFLT or MCHxCAPFLT bit. Step2: Edge selection (CHxP and MCHxP bits in TIMERx_CHCTL2 register, MCHxFP[1:0] bits in TIMERx_MCHCTL2 register). Rising edge or falling edge, choose one by configuring CHxP and MCHxP bits or MCHxFP[1:0] bits.
Page 871: Figure 24-90. Output Compare Logic (When Mchxmsel = 2'11, X=0)
GD32H737/757/759 User Manual Figure 24-89. Output compare logic (when MCHxMSEL = 2’00, x=0) OxCPRE/MOxCPRE Capture/ CNT>CHxCV/ Compare register MCHxCV CHxCV/MCHxCV Compare output Output enable and CNT=CHxCV/ CHx_O control polarity selector MCHxCV CHxCOMCTL/ CHxP,CHxEN/ CNT<CHxCV/ MCHx_O MCHxCOMCTL MCHxFP,MCHxEN MCHxCV Counter Figure 24-90. Output compare logic (when MCHxMSEL = 2’11, x=0) Figure 24-91.
Page 872 GD32H737/757/759 User Manual CHxEN/MCHxEN bits. Please refer to Figure 24-90. Output compare logic (when MCHxMSEL = 2’11, x=0). For examples (the MCHx_O output is independent from the CHx_O output): 3) Configure CHxP=0 (the active level of CHx_O is high, the same as OxCPRE), CHxEN=1 (the output of CHx_O is enabled): If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level;...
Page 873: Figure 24-92. Output-Compare In Three Modes
GD32H737/757/759 User Manual Figure 24-92. Output-compare in three modes CNT_CLK CNT_REG 03 04 03 04 03 04 Overflow OxCPRE OxCPRE OxCPRE PWM mode In the PWM output mode (by setting the CHxCOMCTL/ MCHxCOMCTL bit to 4’b0110 (PWM mode 0) or to 4’b0111(PWM mode 1)), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV/ TIMERx_MCHxCV registers.
Page 874 GD32H737/757/759 User Manual Figure 24-93. PWM mode timechart CARL CHxVAL PWM MO DE0 OxCPRE PWM MO DE1 OxCPRE Interrupt signal CHxIF CHxOF Composite PWM mode In the Composite PWM mode (CHxCPWMEN = 1’b1, CHxMS[2:0] = 3’b000 and CHxCOMCTL = 4’b0110 or 4’b0111), the PWM signal output in channel x (x=0, 1) is composited by CHxVAL and CHxCOMVAL_ADD bits.
Page 875: Table 24-14.The Composite Pwm Pulse Width
GD32H737/757/759 User Manual Table 24-14.The Composite PWM pulse width Condition Mode PWM pulse width (CARL + 0x0001) + PWM mode 0 CHxVAL < CHxCOMVAL_ADD (CHxVAL – CHxCOMVAL_ADD) ≤ CARL PWM mode 1 (CHxCOMVAL_ADD – CHxVAL) PWM mode 0 (CHxVAL - CHxCOMVAL_ADD) CHxCOMVAL_ADD <...
Page 876: Figure 24-94. Channel X Output Pwm With (Chxval < Chxcomval_Add)
GD32H737/757/759 User Manual Figure 24-94. Channel x output PWM with (CHxVAL < CHxCOMVAL_ADD) CARL CHxCOMVAL_ ADD=CARL CHxCOMVAL_ CHxVAL CHxVAL PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF...
Page 877: Figure 24-97. Channel X Output Pwm With Chxval Or Chxcomval_Add Exceeds Carl
GD32H737/757/759 User Manual CHxVAL = CARL CARL CHxVAL CHxCOMVAL_ADD CHxCOMVAL_ADD PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF CHxIF CHxCOMADDIF CHxCOMADDIF CARL CHxVAL CHxCOMVAL_ADD = 0 PWM MODE 1...
Page 878: Figure 24-99. Chx_O Output With A Pulse In Edge-Aligned Mode (Chxompsel =2'B00)
GD32H737/757/759 User Manual next counter next counter period period If more than one channels are configured in composite PWM mode, it is possible to fix an offset for the channel x match edge of each pair with respect to other channels. This behavior is useful in the generation of lighting PWM control signals where it is desirable that edges are not coincident with each other pair to help eliminate noise generation.
Page 879 GD32H737/757/759 User Manual CARL CHxCOMVAL_ CHxVAL OxCPRE CHxOMPSEL=2b 01 Channel output prepare signal Figure 24-89. Output compare logic (when MCHxMSEL = 2’00, As is shown in x=0), Figure 24-90. Output compare logic (when MCHxMSEL = 2’11, x=0) Figure 24-91. Output compare logic...
Page 880 GD32H737/757/759 User Manual Outputs complementary The outputs of CHx_O and MCHx_O have two situations:  MCHxMSEL=2’b00: The MCHx_O output is independent from the CHx_O output;  MCHxMSEL=2’b11: The outputs of MCHx_O and CHx_O are complementary and the MCHxOMCTL bits are not used in the generation of the MCHx_O output.
Page 881: Table 24-15. Complementary Outputs Controlled By Parameters (Mchxmsel =2'B11)
GD32H737/757/759 User Manual Table 24-15. Complementary outputs controlled by parameters (MCHxMSEL =2’b11) Complementary Parameters Output Status POEN ROS CHxEN MCHxEN CHx_O MCHx_O CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off-state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 882: Figure 24-100. Complementary Output With Dead-Time Insertion
GD32H737/757/759 User Manual Dead time insertion The dead time insertion is enabled when MCHxMSEL=2’b11 and both CHxEN and MCHxEN are configured to 1’b1, it is also necessary to configure POEN to 1. The field named DTCFG defines the dead time delay that can be used for all channels. Refer to the...
Page 883: Figure 24-101. Break0 Function Logic Diagram
GD32H737/757/759 User Manual configured by the BRK0P bit in TIMERx_CCHP register, the input is active on level. In BREAK0 function, CHx_O and MCHx_O are controlled by the POEN, OAEN, IOS and ROS bits in the TIMERx_CCHP register, ISOx and ISOxN bits in the TIMERx_CTL1 register.
Page 884 GD32H737/757/759 User Manual high active and IOS=1) BREAK0 OxCPRE CHx_O = ISOx CHxEN: 1 MCHxEN: 1 CHxP : 0 MCHxP : 0 ISOx = ~ISOxN MCHx_O = ISOxN = ISOx CHx_O CHxEN: 1 MCHxEN: 0 CHxP: 0 MCHxP : 0...
Page 885: Figure 24-103. Brkin0 Pin Logic With Break0 Function
GD32H737/757/759 User Manual break function is released. The break events is still active, becanse the break input sources are still active.  POEN=1: when the channel outputs are enabled, the BRKIN0 pin cannot be released even if the BRK0REL is set.
Page 886: Figure 24-104. Restart Mode
GD32H737/757/759 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler y=4: pause mode 00001: ITI1 MCIxFEMx(x=0), For the CIx/ MCIx, configure y=5: event mode 00010: ITI2 configure the CHxP, Filter CHxCAPFLT/ y=6:external clock 00011: ITI3 MCHxP and MCHxFP...
Page 887: Figure 24-106. Event Mode
GD32H737/757/759 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler start to count when ETIFP is selected. ETFC = 0, ETI does not a rising edge of filter. trigger input comes. Figure 24-106. Event mode Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0.
Page 888: Figure 24-107. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32H737/757/759 User Manual Figure 24-107. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 TIMER_CK(CNT_CLK) Under SPM, counter stop CNT_REG O0CPRE Delayable single pulse mode Delayable single pulse mode is enabled by setting CHxCOMCTL[3:0]/ MCHxCOMCTL[3:0] in TIMERx_CHCTLx/ TIMERx_MCHCTLx registers. In this mode, the pulse width of OxCPRE/ MOxCPRE signal is determined by the TIMERx_CAR register.
Page 889: Figure 24-108. Delayable Single Pulse Mode Timerx_Chxcv=0X00, Timerx_Car=0X60
GD32H737/757/759 User Manual greater than or equal to the value of TIMERx_CAR register. Figure 24-108. delayable single pulse mode TIMERx_CHxCV=0x00, TIMERx_CAR=0x60 TIMER_CK (CNT_CLK) 60 00 60 00 CNT_REG O0CPRE Timers interconnection Please refer to Advanced timer (TIMERx, x=0, 7)Timers interconnection Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module.
Page 890: Register Definition(Timerx, X=14,40,41,42,43,44)
GD32H737/757/759 User Manual set to 1, the TIMERx counter stops. Register definition(TIMERx, x=14,40,41,42,43,44) 24.3.5. TIMER14 base address: 0x4001 4000 TIMER40 base address: 0x4001 D000 TIMER41 base address: 0x4001 D400 TIMER42 base address: 0x4001 D800 TIMER43 base address: 0x4001 DC00 TIMER44 base address: 0x4001 F000...
Page 891 GD32H737/757/759 User Manual 0: The shadow register for TIMERx_CAR register is disabled 1: The shadow register for TIMERx_CAR register is enabled Reserved Must be kept at reset value. Single pulse mode 0: Single pulse mode is disabled. Counter continues after an update event.
Page 892 GD32H737/757/759 User Manual Reserved ISO1 ISO0N ISO0 TI0S MMC0[2:0] DMAS CCUC[0] Reserved CCSE Bits Fields Descriptions 31:30 CCUC[2:1] Commutation control shadow register update control Refer to CCUC [0] description. 29:11 Reserved Must be kept at reset value. ISO1 Idle state of channel 1 output...
Page 893 GD32H737/757/759 User Manual 101: Compare. In this mode, the master mode controller selects the O1CPRE signal as TRGO0. 110: Reserved. 111: Reserved. DMAS DMA request source selection 0: DMA request of CHx/MCHx is sent when capture/compare event occurs. 1: DMA request of channel CHx/MCHx is sent when update event occurs.
Page 894 GD32H737/757/759 User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. Master-slave mode This bit can be used to synchronize the selected timers to begin counting at the same time. The TRGI is used as the start event, and through TRGO, timers are connected.
Page 895 GD32H737/757/759 User Manual 23:21 Reserved Must be kept at reset value. MCH0IE Multi mode channel 0 capture/compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used for channel input and output independent mode (when MMCH0SEL[1:0] = 2b’00). 19:15 Reserved Must be kept at reset value.
Page 896 GD32H737/757/759 User Manual 0: Disabled 1: Enabled UPIE Update interrupt enable 0: Disabled 1: Enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH1COM CH0COM Reserved Reserved MCH0OF...
Page 897 GD32H737/757/759 User Manual If multi mode channel 0 is in input mode, this flag is set when a capture event occurs. If multi mode channel 0 is in output mode, this flag is set when a compare event occurs. If multi mode channel 0 is set to input mode, this bit will be reset by reading TIMERx_MCH0CV.
Page 898 GD32H737/757/759 User Manual If channel 0 is in input mode, this flag is set when a capture event occurs. If channel 0 is in output mode, this flag is set when a compare event occurs. If channel 0 is set to input mode, this bit will be reset by reading TIMERx_CH0CV.
Page 899 GD32H737/757/759 User Manual enabled. In addition, if multi mode channel 0 is configured in input mode, the current value of the counter is captured to TIMERx_MCH0CV register, and the MCH0OF flag is set if the MCH0IF flag has been set.
Page 900 GD32H737/757/759 User Manual counter is cleared at the same time. 0: No generate an update event 1: Generate an update event Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 901 GD32H737/757/759 User Manual 23:17 Reserved Must be kept at reset value. CH0COMCTL[3] Channel 0 compare output control Refer to CH0COMCTL[2:0] description Reserved Must be kept at reset value. 14:12 CH1COMCTL[2:0] Channel 1 compare output control Refer to CH0COMCTL[2:0] description CH1COMSEN...
Page 902 GD32H737/757/759 User Manual 0101: Force high. O0CPRE is forced high level. 0110: PWM mode 0. When counting up, O0CPRE is active as long as the counter is smaller than TIMERx_CH0CV, otherwise it is inactive. When counting down, O0CPRE is inactive as long as the counter is larger than TIMERx_CH0CV, otherwise it is active.
Page 903 GD32H737/757/759 User Manual CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. The CH0MS[2:0] bit-field is writable only when the channel is not active (When MCH0MSEL[1:0] = 2b’00, the CH1EN bit in TIMERx_CHCTL2 register is reset;...
Page 904 GD32H737/757/759 User Manual 1001: f /8, N=8. SAMP 1010: f /16, N=5. SAMP 1011: f /16, N=6. SAMP 1100: f /16, N=8. SAMP 1101: f /32, N=5. SAMP 1110: f /32, N=6. SAMP 1111: f /32, N=8. SAMP CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input.
Page 905 GD32H737/757/759 User Manual When Multi mode channel 0 is configured in output mode, and the MCH0MSEL[1:0] = 2b’11, this bit specifies the MCH0_O output signal polarity. 0: Multi mode channel 0 output active high 1: Multi mode channel 0 output active low When CH0 is configured in input mode, in conjunction with CH0P, this bit is used to define the polatity of CH0.
Page 906 GD32H737/757/759 User Manual UPIFBU Reserved CNT[15:0] Bits Fields Descriptions UPIFBU UPIF bit backup This bit is a backup of UPIF bit in TIMERx_INTF register, and read-only. This bit is only valid when UPIFBUEN = 1. If the UPIFBUEN =0, this bit is reserved and read the result is 0.
Page 907 GD32H737/757/759 User Manual Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-field specifies the auto reload value of the counter. Counter repetition register 0 (TIMERx_CREP0) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 908 GD32H737/757/759 User Manual CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0VAL[15:0] Capture/compare value of channel 0 When channel 0 is configured in input mode, this bit-field indicates the counter value at the last capture event. And this bit-field is read-only.
Page 909 GD32H737/757/759 User Manual POEN OAEN BRK0P BRK0EN PROT[1:0] DTCFG[7:0] Bits Fields Descriptions 31:29 Reserved Must be kept at reset value. BRK0LK BREAK0 input locked 0: BREAK0 input in input mode 1: BREAK0 input in locked mode When the BRK0LK is set to 1, the BREAK0 input is configured in open drain output mode.
Page 910 GD32H737/757/759 User Manual 1011: f /16, N=6 SAMP 1100: f /16, N=8 SAMP 1101: f /32, N=5 SAMP 1110: f /32, N=6 SAMP 1111: f /32, N=8 SAMP This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is...
Page 911 GD32H737/757/759 User Manual 1: “off-state” enabled. If the CHxEN or CHxNEN bit is reset, the corresponding channel is “off-state”. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. Idle mode “off-state” enable When POEN bit is reset (Idle mode), this bit can be set to enable the “off-state” for the channels which has been configured in output mode.
Page 912 GD32H737/757/759 User Manual Multi mode channel control register 0 (TIMERx_MCHCTL0) Address offset: 0x48 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). MCH0CO MCH0 Reserved Reserved MCTL[3] MS[2] Reserved MCH0CO Reserved MCH0COMCTL[2:0] Reserved MSEN Reserved MCH0MS[1:0]...
Page 913 GD32H737/757/759 User Manual 0011: Toggle on match. MO0CPRE toggles when the counter matches the output compare register TIMERx_MCH0CV. 0100: Force low. MO0CPRE is forced low level. 0101: Force high. MO0CPRE is forced high level. 0110: PWM mode 0. When counting up, MO0CPRE is active as long as the counter is smaller than TIMERx_MCH0CV, otherwise it is inactive.
Page 914 GD32H737/757/759 User Manual MCH0MS[1:0] Multi mode channel 0 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. This bit-field is writable only when the channel is not active (MCH0EN bit in TIMERx_CHCTL2 register is reset).
Page 915 GD32H737/757/759 User Manual MCH0CAPPSC[1:0] Multi mode channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when MCH0EN bit in TIMERx_CHCTL2 register is cleared. 00: Prescaler disabled, capture is done on each channel input edge.
Page 916 GD32H737/757/759 User Manual This bit cannot be modified when PROT[1:0] bit-field in TIMERx_CCHP register is 11 or 10. Multi mode channel 0 capture/compare value register (TIMERx_MCH0CV) Address offset: 0x54 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 917 GD32H737/757/759 User Manual shadow register updates by every update event. Note: This register just used in composite PWM mode(when CH0CPWMEN=1). Channel 1 additional compare value register (TIMERx_CH1COMV_ADD) Address offset: 0x68 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 918 GD32H737/757/759 User Manual 1: Enabled CH0CPWMEN Channel 0 composite PWM mode enable 0: Disabled 1: Enabled 27:22 Reserved Must be kept at reset value. 21:20 MCH0MSEL[1:0] Multi mode channel 0 mode select 00: Independent mode, MCH0 is independent of CH0...
Page 919 GD32H737/757/759 User Manual BRK0CMP BRK0CMP Reserved Reserved BRK0IN0P BRK0HPD BRK0IN0E BRK0CMP BRK0CMP Reserved Reserved Bits Fields Descriptions 31:27 Reserved Must be kept at reset value. BRK0CMP1P BREAK0 CMP1 input polarity This bit is used to configure the CMP1 input polarity, and the specitic polarity is determined by this bit and the BRK0P bit.
Page 920 GD32H737/757/759 User Manual 0: CMP1 input disabled 1: CMP1 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is BRK0CMP0EN BREAK0 CMP0 enable 0: CMP0 input disabled 1: CMP0 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is...
Page 921 GD32H737/757/759 User Manual Note: This bit-field just used with CREPSEL =1(in TIMERx_CFG register). DMA configuration register (TIMERx_DMACFG) Address offset: 0xE0 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved DMATC[5:0] Reserved DMATA[5:0] Bits Fields...
Page 922 GD32H737/757/759 User Manual DMATB[31:16] DMATB[15:0] Bits Fields Descriptions 31:0 DMATB[31:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address ranges from (start address) to (start address + transfer count * 4) will be accessed.
Page 923 GD32H737/757/759 User Manual 0: No effect. OUTSEL The output value selection bit This bit-field is set and reset by software. 1: If POEN bit and IOS bit are 0, the output is disabled. 0: No effect.
Page 924: Figure 24-109. General Level4 Timer Block Diagram
GD32H737/757/759 User Manual 24.4. General level4 timer (TIMERx, x=15,16) Overview 24.4.1. The general level4 timer module (TIMER15/16) is a two-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 925 GD32H737/757/759 User Manual configuration of the general level4 timer. Figure 24-109. General level4 timer block diagram Input Logic Synchronizer&Filter Edge selector Prescaler CH0_I &Edge Detector MCH0_I TIMERx_CHxCV/ CK_TIMER Counter TIMERx_MCHxCV PSC_CLK Counter Control TIMER_CK DMA REQ/ACK DMA controller TIMERx_CH0 TIMERx_UP...
Page 926: Figure 24-110. Normal Mode, Internal Clock Divided By 1
GD32H737/757/759 User Manual Figure 24-110. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG 20 21 01 02 Prescaler The prescaler can divide the timer clock (TIMER_CK) to a counter clock (PSC_CLK) by any factor between 1 and 65536.
Page 927: Figure 24-112. Timing Diagram Of Up Counting Mode, Psc=0/2
GD32H737/757/759 User Manual Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter restarts from 0. If the repetition counter is set, the update events will be generated after (TIMERx_CREP0/1+1) times of overflow.
Page 928: Figure 24-113. Timing Diagram Of Up Counting Mode, Change Timerx_Car On The Go
GD32H737/757/759 User Manual Timing diagram of up counting mode, Figure 24-113. change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG...
Page 929: Figure 24-114. Repetition Timechart For Up-Counter
GD32H737/757/759 User Manual Figure 24-114. Repetition timechart for up-counter TIMER_CK CNT_CLK 61 62 63 00 01 62 63 00 01 62 63 00 01 62 63 00 01 62 63 00 01 CNT_REG 62 63 00 01 Underflow Overflow TIMERx_CREP0 = 0x0...
Page 930: Figure 24-115. Input Capture Logic For Channel 0
GD32H737/757/759 User Manual Figure 24-115. Input capture logic for channel 0 Edge Detector Synchronizer Edge selector &inverter Based on CH0P&MCH0P TIMER_CK CI0FE0 Rising/Falling Capture Clock Register MCI0FE0 Prescaler Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channals Figure 24-116.
Page 931: Figure 24-117. Output Compare Logic (When Mchxmsel = 2'00, X=0)
GD32H737/757/759 User Manual CHxCAPFLT or MCHxCAPFLT bit. Step2: Edge selection (CHxP and MCHxP bits in TIMERx_CHCTL2 register, MCHxFP[1:0] bits in TIMERx_MCHCTL2 register). Rising edge or falling edge, choose one by configuring CHxP and MCHxP bits or MCHxFP[1:0] bits. Step3: Capture source selection (CHxMS bit in TIMERx_CHCTL0 register, MCHxMS bit in TIMERx_MCHCTL0 register).
Page 932: Figure 24-118. Output Compare Logic (When Mchxmsel = 2'11, X=0)
GD32H737/757/759 User Manual Figure 24-118. Output compare logic (when MCHxMSEL = 2’11, x=0) OxCPRE Capture/ compare register CNT>CHxCV Output Output enable CHxCV CHx_O Compare complementary and polarity CNT=CHxCV output control protection selector MCHx_O register CHxP,CHxEN/ CNT<CHxCV CHxCOMCTL MCHxP,MCHxEN &Dead-Time Counter...
Page 933: Figure 24-119. Output-Compare In Three Modes
GD32H737/757/759 User Manual counter reaches the value in the TIMERx_CHxCV/ TIMERx_MCHxCV register, the CHxIF/ MCHxIF bit will be set and the channel (n) interrupt is generated if CHxIE/ MCHxIE = 1. And the DMA request will be asserted, if CHxDEN/ MCHxDEN =1.
Page 934: Figure 24-120. Pwm Mode Timechart
GD32H737/757/759 User Manual The EAPWM’s period is determined by TIMERx_CAR and the duty cycle is determined by TIMERx_CHxCV/ TIMERx_MCHxCV. Figure 24-120. PWM mode timechart shows the EAPWM output and interrupts waveform. In up counting mode, if the value of TIMERx_CHxCV/ TIMERx_MCHxCV is greater than the value of TIMERx_CAR, the output will be always active in PWM mode 0 (CHxCOMCTL/ MCHxCOMCTL =4’b0110).
Page 935: Table 24-18. Complementary Outputs Controlled By Parameters (Mchxmsel =2'B11)
GD32H737/757/759 User Manual and the TIMERx_CHxCV content. Refer to the definition of relative bit for more details. Another special function of the OxCPRE signal is forced output which can be achieved by configuring the CHxCOMCTL field to 0x04/ 0x05. The output can be forced to an inactive/active level irrespective of the comparison condition between the values of the counter and the TIMERx_CHxCV.
Page 936 GD32H737/757/759 User Manual Complementary Parameters Output Status POEN ROS CHxEN MCHxEN CHx_O MCHx_O MCHx_O=OxCPRE⊕ CHx_O = LOW MCHxP CHx_O output disable. MCHx_O output enable. MCHx_O = LOW CHx_O=OxCPRE⊕CHxP CHx_O output enable. MCHx_O output disable. ⊕ MCHx_O=(!OxCPRE) CHx_O=OxCPRE⊕CHxP MCHxP. CHx_O output enable.
Page 937: Figure 24-121. Complementary Output With Dead-Time Insertion
GD32H737/757/759 User Manual Sometimes, we can see corner cases about the dead time insertion. For example: the dead time delay is greater than or equal to the duty cycle of the CHx_O signal, then the CHx_O signal is always inactive (As shown in Figure 24-121.
Page 938: Figure 24-122. Break0 Function Logic Diagram
GD32H737/757/759 User Manual from the TRIGSEL module, which can select by TRICSEL_TIMERxBTKIN registers. Figure 24-122. BREAK0 function logic diagram When a BREAK0 event occurs, the outputs is force at a inactive level, or at a predefined level (either active or inactive) after a deadtime duration.
Page 939: Table 24-19. Break Function Input Pins Locked/ Released Conditions
GD32H737/757/759 User Manual When a break occurs, the BRKIF bit in the TIMERx_INTF register will be set. If BRKIE is 1, an interrupt will be generated. Locked break function The BRKIN0 input pin of general timer have the locked break function, this function can be enabled by setting the BRK0LK bit in the TIMERx_CCHP register.
Page 940: Figure 24-124. Brkin0 Pin Logic With Break0 Function
GD32H737/757/759 User Manual Figure 24-124. BRKIN0 pin logic with BREAK0 function CKM clock monitor LVD lock event LOCKUP_LOCK event SYSBIF BRK0G SRAM parity error event System source Flash ECC error requests BRK0EN HPDF_OUT BRK0HPDFEN Output Logic CMP0_OUT BRK0CMP0EN BRK0CMP0P Digital...
Page 941 GD32H737/757/759 User Manual Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB. Of course, you have to enable a DMA request which will be asserted by some internal event. When the interrupt event was asserted, TIMERx will send a request to DMA, which is configured to M2P mode and PADDR is TIMERx_DMATB, then DMA will access the TIMERx_DMATB.
Page 942 GD32H737/757/759 User Manual Register definition(TIMERx, x=15,16) 24.4.5. TIMER15 base address: 0x4001 4400 TIMER16 base address: 0x4001 4800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved UPIFBUE Reserved...
Page 943 GD32H737/757/759 User Manual counter stops at next update event. Update source This bit is used to select the update event sources by software. 0: Any of the following events generates an update interrupt or a DMA request: – The UPG bit is set.
Page 944 GD32H737/757/759 User Manual 29:10 Reserved Must be kept at reset value. ISO0N Idle state of multi mode channel 0 complementary output 0: When POEN bit is reset, MCH0_O is set low. 1: When POEN bit is reset, MCH0_O is set high.
Page 945 GD32H737/757/759 User Manual MCH0 Reserved Reserved MCH0IE Reserved Reserved CH0DEN UPDEN BRKIE Reserved CMTIE Reserved CH0IE UPIE Bits Fields Descriptions 31:25 Reserved Must be kept at reset value. MCH0DEN Multi mode channel 0 capture/compare DMA request enable 0: Disabled 1: Enabled Note: This bit just used for channel input and output independent mode (when MMCH0SEL[1:0] = 2b’00).
Page 946 GD32H737/757/759 User Manual 1: Enabled UPIE Update interrupt enable 0: Disabled 1: Enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved MCH0OF Reserved MCH0IF Reserved rc_w0 rc_w0...
Page 947 GD32H737/757/759 User Manual 0: No over capture interrupt occurred 1: Over capture interrupt occurred Reserved Must be kept at reset value. BRK0IF BREAK0 interrupt flag This flag is set by hardware when the BREAK0 input is active, and cleared by software if the BREAK0 input is not at active level.
Page 948 GD32H737/757/759 User Manual Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. MCH0G Multi mode channel 0 capture or compare event generation. This bit is set by software to generate a capture or compare event in multi mode channel 0, it is automatically cleared by hardware.
Page 949 GD32H737/757/759 User Manual 0: No generate an update event 1: Generate an update event Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH0COM Reserved CH0MS[2] Reserved Reserved...
Page 950 GD32H737/757/759 User Manual counter matches the output compare register TIMERx_CH0CV. 0011: Toggle on match. O0CPRE toggles when the counter matches the output compare register TIMERx_CH0CV. 0100: Force low. O0CPRE is forced low level. 0101: Force high. O0CPRE is forced high level.
Page 951 GD32H737/757/759 User Manual 011: Reserved 100: Channel 0 is configured as input, IS0 is connected to MCI0FE0. 101~111: Reserved. Input capture mode: Bits Fields Descriptions Reserved Must be kept at reset value. CH0MS[2] Channel 0 I/O mode selection Refer to CH0MS[1:0] description.
Page 952 GD32H737/757/759 User Manual Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved MCH0P MCH0EN CH0P CH0EN Bits Fields Descriptions 31:4 Reserved Must be kept at reset value.
Page 953 GD32H737/757/759 User Manual 11: Noninverted/both channel 0 input signal’s edges. This bit cannot be modified when PROT[1:0] bit-field in TIMERx_CCHP register is 11 or 10. CH0EN Channel 0 capture/compare enable When channel 0 is configured in output mode, setting this bit enables CH0_O signal in active state.
Page 954 GD32H737/757/759 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock. The value of this bit-field will be loaded to the corresponding shadow register at every update event.
Page 955 GD32H737/757/759 User Manual CREP0[7:0] Counter repetition value 0 This bit-field specifies the update event generation rate. Each time the repetition counter counts down to zero, an update event will be generated. The update rate of the shadow registers is also affected by this bit-field when these shadow registers are enabled.
Page 956 GD32H737/757/759 User Manual 31:29 Reserved Must be kept at reset value. BRK0LK BREAK0 input locked 0: BREAK0 input in input mode 1: BREAK0 input in locked mode When the BRK0LK is set to 1, the BREAK0 input is configured in open drain output mode.
Page 957 GD32H737/757/759 User Manual POEN Primary output enable This bit is set by software or automatically set by hardware depending on the OAEN bit. It is cleared asynchronously by hardware as soon as the break input is active. When one of channels is configured in output mode, setting this bit enables the channel outputs (CHx_O and MCHx_O) if the corresponding enable bits (CHxEN, MCHxEN in TIMERx_CHCTL2 register) have been set.
Page 958 GD32H737/757/759 User Manual the channels which has been configured in output mode. Please refer to Table 24-15. Complementary outputs controlled by parameters (MCHxMSEL =2’b11). 0: “off-state” disabled. If the CHxEN/CHxNEN bits are both reset, the channels are output disabled. 1: “off-state” enabled. No matter the CHxEN/CHxNEN bits, the channels are “off- state”.
Page 959 GD32H737/757/759 User Manual Reserved MCH0CO Reserved MCH0COMCTL[2:0] Reserved MSEN Reserved MCH0MS[1:0] MCH0CAPPSC MCH0CAPFLT[3:0] [1:0] Output compare mode: Bits Fields Descriptions Reserved Must be kept at reset value. MCH0MS[2] Multi mode channel 0 I/O mode selection Refer to MCH0MS[1:0] description. 29:17 Reserved Must be kept at reset value.
Page 960 GD32H737/757/759 User Manual 0111: PWM mode 1. When counting up, MO0CPRE is inactive as long as the counter is smaller than TIMERx_MCH0CV, otherwise it is active. When counting down, MO0CPRE is active as long as the counter is larger than TIMERx_MCH0CV, otherwise it is inactive.
Page 961 GD32H737/757/759 User Manual An event counter is used in the digital filter, in which a transition on the output occurs after N input events. This bit-field specifies the frequency used to sample MCI0 input signal and the length of the digital filter applied to MCI0.
Page 962 GD32H737/757/759 User Manual 31:2 Reserved Must be kept at reset value. MCH0FP[1:0] Multi mode channel 0 capture/compare free polarity When multi mode channel 0 is configured in output mode, and the MCH0MSEL[1:0] = 2b’00, these bits specifie the multi mode channel 0 output signal polarity.
Page 963 GD32H737/757/759 User Manual enabled, the shadow register updates by every update event. Control register 2 (TIMERx_CTL2) Address offset: 0x74 Reset value: 0x0030 0000 This register has to be accessed by word (32-bit). MCH0MSEL[1:0] Reserved Reserved Reserved Bits Fields Descriptions 31:22 Reserved Must be kept at reset value.
Page 964 GD32H737/757/759 User Manual BRK0CMP1P BREAK0 CMP1 input polarity This bit is used to configure the CMP1 input polarity, and the specitic polarity is determined by this bit and the BRK0P bit. 0: CMP1 input signal will not be inverted (BRK0P =0, the input signal is active low;...
Page 965 GD32H737/757/759 User Manual signal) enable 0: HPDF input disabled 1: HPDF input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is Reserved Must be kept at reset value. BRK0IN0EN BREAK0 BRKIN0 alternate function input enable...
Page 966 GD32H737/757/759 User Manual Reserved DMATC[5:0] Reserved DMATA[5:0] Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:8 DMATC[5:0] DMA transfer count This field defines the times of accessing(R/W) the TIMERx_DMATB register by DMA. 6’b000000: transfer 1 time 6’b000001: transfer 2 times …...
Page 967 GD32H737/757/759 User Manual The transfer count is calculated by hardware, and ranges from 0 to DMATC. Configuration register (TIMERx_CFG) Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CCUSEL CREPSEL CHVSEL OUTSEL...
Page 968: Figure 24-126. Basic Timer Block Diagram
GD32H737/757/759 User Manual 24.5. Basic timer (TIMERx, x=5,6,50,51) Overview 24.5.1. The basic timer module(TIMER5/6/50/51) has a 32-bit or 64-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate a DMA request and a TRGO0 to connect to DAC.
Page 969: Figure 24-127. Normal Mode, Internal Clock Divided By 1
GD32H737/757/759 User Manual Figure 24-127. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG 20 21 01 02 Prescaler The prescaler can divide the timer clock (TIMER_CK) to a counter clock (PSC_CLK) by any factor ranging from 1 to 65536.
Page 970: Figure 24-129. Timing Chart Of Up Counting Mode, Psc=0/2 (Timerx, X=5,6)
GD32H737/757/759 User Manual Up counting mode In this mode, the counter counts up continuously from 0 to the counter reload value, which is defined in the TIMERx_CAR/ TIMERx_CARL/ TIMERx_CARH register, in a count-up direction. Once the counter reaches the counter reload value, the counter restarts from 0. The update event is generated each time when counter overflows.
Page 971 GD32H737/757/759 User Manual (TIMERx, x=5,6) TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF)
Page 972 GD32H737/757/759 User Manual Registers definition (TIMERx, x=5,6,50,51) 24.5.5. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 TIMER50 base address: 0x4000 F000 TIMER51 base address: 0x4000 F400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 973 GD32H737/757/759 User Manual This bit is used to select the update event sources by software. 0: When enabled, any of the following events generates an update interrupt or a DMA request: – The UPG bit is set – The counter generates an overflow event –...
Page 974 GD32H737/757/759 User Manual slave timer for synchronization function. 000: Reset. When the UPG bit in the TIMERx_SWEVG register is set or a reset is generated by the slave mode controller, a TRGO0 pulse occurs. And in the latter case, the signal on TRGO0 is delayed compared to the actual reset.
Page 975 GD32H737/757/759 User Manual This register has to be accessed by word (32-bit). Reserved Reserved UPIF rc_w0 Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. UPIF Update interrupt flag This bit is set by hardware when an update event occurs and cleared by software.
Page 976 GD32H737/757/759 User Manual UPIFBU rw/ r CNT[15:0] UPIFBUEN = 0: Bits Fields Descriptions 31:0 CNT[31:0] This bit-field indicates the current counter value. Writing to this bit-field can change the value of the counter. UPIFBUEN = 1: Bits Fields Descriptions UPIFBU UPIF bit backup This bit is a backup of UPIF bit in TIMERx_INTF register, and read-only.
Page 977 GD32H737/757/759 User Manual Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock. The value of this bit-field will be loaded to the corresponding shadow register at every update event.
Page 978 GD32H737/757/759 User Manual Bits Fields Descriptions 31:0 CARLL[31:0] Counter auto reload low value This bit-field specifies the auto reload low value of the counter. Counter high register (TIMERx_CNTH) (TIMERx, x=50,51) Address offset: 0xD0 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 979 GD32H737/757/759 User Manual Bits Fields Descriptions 31:0 CARLH[63:32] Counter auto reload high value This bit-field specifies the auto reload high value of the counter.
Page 980 GD32H737/757/759 User Manual Universal synchronous / asynchronous receiver / transmitter (USART) 25.1. Overview The Universal Synchronous / Asynchronous Receiver / Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK (CK_APBx, CK_AHB, CK_LXTAL or CK_IRC64MDIV) to produces a dedicated wide range baudrate clock for the USART transmitter and receiver.
Page 981 GD32H737/757/759 User Manual  Parity control: Transmits parity bit. – Checks parity of received data byte. – LIN break generation and detection.   IrDA support.  Synchronous mode and transmitter clock output for synchronous transmission.  ISO 7816-3 compliant smartcard interface: Character mode (T = 0).
Page 982: Figure 25-1. Usart Module Block Diagram
GD32H737/757/759 User Manual 25.3. Function overview The interface is externally connected to another device by the main pins listed in Table 25-1. Description of USART important pins. Table 25-1. Description of USART important pins Type Description Input Receive Data Output I/O (single-wire / Transmit Data.
Page 983: Figure 25-2. Usart Character Frame (8 Bits Data And 1 Stop Bit)
GD32H737/757/759 User Manual register. Figure 25-2. USART character frame (8 bits data and 1 stop bit) In transmission and reception, the number of stop bits can be configured by the STB[1:0] bits in the USART_CTL1 register. Table 25-2. Configuration of stop bits...
Page 984 GD32H737/757/759 User Manual USARTDIV=33 + 13 / 16 = 33.81. Get the value of USART_BAUD by calculating the value of USARTDIV: If USARTDIV = 30.37, then INTDIV = 30 (0x1E). 16*0.37 = 5.92, the nearest integer is 6, so FRADIV = 6 (0x6).
Page 985: Figure 25-3. Usart Transmit Procedure
GD32H737/757/759 User Manual Figure 25-3. USART transmit procedure It is necessary to wait for the TC bit to be asserted before disabling the USART or entering the power saving mode. The TC bit can be cleared by set the TCC bit in USART_INTC register.
Page 986: Figure 25-4. Oversampling Method Of A Receive Frame Bit (Osb = 0)
GD32H737/757/759 User Manual bit in USART_CTL2 register is set. If the OSB bit in USART_CTL2 register is set, the receiver gets only one sample to evaluate a bit value. In this situation, no noisy error will be detected. Figure 25-4. Oversampling method of a receive frame bit (OSB = 0) If the parity check function is enabled by setting the PCEN bit in the USART_CTL0 register, the receiver calculates the expected parity value while receiving a frame.
Page 987: Figure 25-5. Configuration Step When Using Dma For Usart Transmission
GD32H737/757/759 User Manual and the DENR bit in USART_CTL2 is used to enable the DMA reception. When DMA is used for USART transmission, DMA transfers data from internal SRAM to the transmit data buffer of the USART. The configuration step are shown in Figure 25-5.
Page 988: Figure 25-6. Configuration Step When Using Dma For Usart Reception
GD32H737/757/759 User Manual Figure 25-6. Configuration step when using DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA...
Page 989: Figure 25-8. Hardware Flow Control
GD32H737/757/759 User Manual RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full.
Page 990 GD32H737/757/759 User Manual The idle frame wake up method is selected by default. If the RWU bit is reset, an idle frame is detected on the RX pin, the IDLEF bit in USART_STAT will be set. If the RWU bit is set, an idle frame is detected on the RX pin, the hardware clears the RWU bit and exits the mute mode.
Page 991: Figure 25-9. Break Frame Occurs During Idle State
GD32H737/757/759 User Manual by 1 stop bit. The break detection function is totally independent of the normal USART receiver. So a break frame can be detected during the idle state or during a frame. The expected length of a break frame can be selected by configuring LBLEN in USART_CTL1.
Page 992: Figure 25-11. Example Of Usart In Synchronous Mode
GD32H737/757/759 User Manual The clock is synchronized with the data transmitted. The receiver in synchronous mode samples the data on the transmitter clock without any oversampling. Figure 25-11. Example of USART in synchronous mode Data output Data input USART Device...
Page 993: Figure 25-13. Irda Sir Endec Module
GD32H737/757/759 User Manual Figure 25-13. IrDA SIR ENDEC module Inside chip Outside chip RX pin Receive Decoder Infrared Normal IREN USART TX pin Transmit Encoder SIR MODULE In IrDA mode, the polarity of the TX and RX pins is different. The TX pin is usually at low state, while the RX pin is usually at high state.
Page 994: Figure 25-15. Iso7816-3 Frame Format
GD32H737/757/759 User Manual Half-duplex communication mode 25.3.11. The half-duplex communication mode is enabled by setting the HDEN bit in USART_CTL2. The LMEN, CKEN bits in USART_CTL1 and SCEN, IREN bits in USART_CTL2 should be cleared in half-duplex communication mode. Only one wire is used in half-duplex mode. The TX and RX pins are connected together internally.
Page 995 GD32H737/757/759 User Manual can automatically resend data according to the protocol for SCRTNUM times. An interframe gap of 2.5 bits time will be inserted before the start of a resented frame. At the end of the last repeated character the TC bit is set immediately without guard time. The USART will stop transmitting and assert the frame error status if it still receives the NACK signal after the programmed number of retries.
Page 996 GD32H737/757/759 User Manual third character. The total block length (including prologue, epilogue and information fields) equals BL+4. The end of the block is signaled to the software through the EBF flag and interrupt (when EBIE bit is set). The RT interrupt may occur in case of an error in the block length.
Page 997: Figure 25-16. Usart Receive Fifo Structure
GD32H737/757/759 User Manual an interrupt is generated if the RFTIE bit is set. An interrupt will be generated when receive FIFO is not empty if RFNEIE bit is set. Figure 25-16. USART receive FIFO structure If the software read receive data buffer in the routing of the RBNE interrupt, the RBNEIE bit should be reset at the beginning of the routing and set after all of the receive data is read out.
Page 998: Table 25-3. Usart Interrupt Requests
GD32H737/757/759 User Manual interrupt or the WUM interrupt. The UESM bit must be set and the USART clock must be set to CK_IRC64MDIV or CK_LXTAL (refer to the reset and clock unit RCU section). When using the standard RBNE interrupt, the RBNEIE bit must be set before entering deep- sleep mode.
Page 999: Figure 25-18. Usart Interrupt Mapping Diagram
GD32H737/757/759 User Manual Interrupt event Event flag Enable Control bit Reception errors (noise flag, NERR or ORERR or FERR ERRIE overrun error, framing error) ADDR0 match AMF0 AMIE0 ADDR1 match AMF1 AMIE1 Receiver timeout error RTIE End of Block EBIE...
Page 1000 GD32H737/757/759 User Manual 25.4. Register definition USART0 base address: 0x4001 1000 USART1 base address: 0x4000 4400 USART2 base address: 0x4000 4800 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 USART5 base address: 0x4001 1400 UART6 base address: 0x4000 7800...

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