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EFR32xG1 Wireless Gecko
Reference Manual
The Wireless Gecko portfolio of SoCs (EFR32) include the
EFR32MG1, EFR32BG1, and EFR32FG1 families. With support
for Bluetooth Low Energy (BLE), Zigbee
protocols, the Wireless Gecko portfolio is ideal for enabling ener-
gy-friendly wireless networking for IoT devices.
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable high-power amplifier, an integrated balun and no-compromise MCU
features.
Core / Memory
ARM Cortex
TM
M4 processor
with DSP extensions and FPU
Flash Program
RAM Memory
Memory
Radio Transceiver
Sub GHz
I
LNA
RF Frontend
PA
Q
2.4 GHz
I
LNA
RF Frontend
BALUN
PA
Q
Lowest power mode with peripheral operational:
EM0—Active
silabs.com | Building a more connected world.
®
, Thread and proprietary
Memory
Protection Unit
Debug Interface
DMA Controlller
Peripheral Reflex System
DEMOD
PGA
IFADC
To Sub GHz
receive I/Q
AGC
mixers and PA
Frequency
MOD
Synthesizer
To 2.4 GHz receive
To Sub GHz
I/Q mixers and PA
and 2.4 GHz PA
EM1—Sleep
EM2—Deep Sleep
Copyright © 2022 by Silicon Laboratories
Clock Management
High Frequency
High Frequency
Crystal Oscillator
RC Oscillator
Auxiliary High
Low Frequency
Frequency RC
RC Oscillator
Oscillator
Ultra Low
Low Frequency
Frequency RC
Crystal Oscillator
Oscillator
32-bit bus
Serial
I/O Ports
Interfaces
External
USART
Interrupts
Low Energy
General
TM
UART
Purpose I/O
I
2
C
Pin Reset
Pin Wakeup
EM3—Stop
KEY FEATURES
• 32-bit ARM® Cortex-M4 core with 40 MHz
maximum operating frequency
• Scalable Memory and Radio configuration
options available in several footprint
compatible QFN packages
• 12-channel Peripheral Reflex System
enabling autonomous interaction of MCU
peripherals
• Autonomous Hardware Crypto Accelerator
and Random Number Generator
• Integrated balun for 2.4 GHz and
integrated PA with up to 19.5 dBm
transmit power for 2.4 GHz and 20 dBm
transmit power for Sub-GHz radios
• Integrated dc-dc with RF noise mitigation
Energy Management
Voltage
Voltage Monitor
Regulators
DC/DC Regulator
Power-On Reset
Brown-Out
Detector
Timers and Triggers
Timer/Counter
Protocol Timer
Low Energy
Watchdog Timer
Timer
Real Time
Pulse Counter
Counter and
Calendar
Cryotimer
EM4—Hibernate
Other
CRYPTO
CRC
Analog
Interfaces
ADC
Analog
Comparator
IDAC
EM4—Shutoff
Rev. 1.3
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Table of Contents
Related Manuals for Silicon Laboratories EFR32 G1 Series
Summary of Contents for Silicon Laboratories EFR32 G1 Series
- Page 1 To 2.4 GHz receive To Sub GHz I/Q mixers and PA and 2.4 GHz PA Lowest power mode with peripheral operational: EM0—Active EM1—Sleep EM2—Deep Sleep EM3—Stop EM4—Hibernate EM4—Shutoff silabs.com | Building a more connected world. Copyright © 2022 by Silicon Laboratories Rev. 1.3...
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Page 2: Table Of Contents
Table of Contents 1. About This Document ......23 1.1 Introduction .......23 1.2 Conventions . - Page 3 4.3.1 Writing .......46 4.3.2 Reading .......48 4.3.3 FREEZE Register .
- Page 4 4.7.41 DCDCLPVCTRL0 - DCDC Low-power VREF Trim Register 0 ... .85 4.7.42 DCDCLPVCTRL1 - DCDC Low-power VREF Trim Register 1 ... .86 4.7.43 DCDCLPVCTRL2 - DCDC Low-power VREF Trim Register 2 .
- Page 5 8. MSC - Memory System Controller ..... . 1 24 8.1 Introduction ......124 8.2 Features .
- Page 6 9.3.6 Arbitration ......158 9.3.7 Channel Descriptor Data Structure ..... 160 9.3.8 Interaction With the EMU .
- Page 7 10.3.4 Brown-Out Detector (BOD) ..... . . 199 10.3.5 RESETn Pin Reset......200 10.3.6 Watchdog Reset .
- Page 8 11.5.14 EMU_PWRCFG - Power Configuration Register ....245 11.5.15 EMU_PWRCTRL - Power Control Register ....245 11.5.16 EMU_DCDCCTRL - DCDC Control .
- Page 9 12.5.9 CMU_HFXOTIMEOUTCTRL - HFXO Timeout Control ... . .303 12.5.10 CMU_LFXOCTRL - LFXO Control Register ....306 12.5.11 CMU_ULFRCOCTRL - ULFRCO Control Register .
- Page 10 13.3.5 Register Lock ......3 54 13.3.6 Oscillator Failure Detection ..... . . 354 13.3.7 Retention Registers .
- Page 11 14.5.5 WDOG_IF - Watchdog Interrupt Flags ....385 14.5.6 WDOG_IFS - Interrupt Flag Set Register ....386 14.5.7 WDOG_IFC - Interrupt Flag Clear Register .
- Page 12 16.5.1 PCNTn_CTRL - Control Register (Async Reg) ....430 16.5.2 PCNTn_CMD - Command Register (Async Reg) ....434 16.5.3 PCNTn_STATUS - Status Register .
- Page 13 17.5.10 I2Cn_RXDATAP - Receive Buffer Data Peek Register ... . . 480 17.5.11 I2Cn_RXDOUBLEP - Receive Buffer Double Data Peek Register ..481 17.5.12 I2Cn_TXDATA - Transmit Buffer Data Register .
- Page 14 18.5.19 USARTn_IFC - Interrupt Flag Clear Register ....554 18.5.20 USARTn_IEN - Interrupt Enable Register ....556 18.5.21 USARTn_IRCTRL - IrDA Control Register .
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Page 15: Functional Description
19.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg) ..610 19.5.17 LEUARTn_FREEZE - Freeze Register ....611 19.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register . - Page 16 21.2 Features ......682 21.3 Functional Description ......683 21.3.1 Timer .
- Page 17 23. ACMP - Analog Comparator ......7 22 23.1 Introduction ......7 22 23.2 Features .
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Page 18: Register Map
24.3.12 DMA Request ......771 24.3.13 Calibration ......771 24.3.14 EM2 DeepSleep or EM3 Stop Operation . - Page 19 25.3.5 Interrupts ......819 25.3.6 Minimizing Output Transition ..... . 8 19 25.3.7 Duty Cycle Configuration.
- Page 20 27.4.2 Instructions and Execution ..... . . 845 27.4.3 Repeated Sequence ......850 27.4.4 AES .
- Page 21 27.6.34 CRYPTO_DDATA2 - DDATA2 Register Access (No Bit Access) (Actionable Reads) . . . 892 27.6.35 CRYPTO_DDATA3 - DDATA3 Register Access (No Bit Access) (Actionable Reads) . . . 892 27.6.36 CRYPTO_DDATA4 - DDATA4 Register Access (No Bit Access) (Actionable Reads) . . . 893 27.6.37 CRYPTO_DDATA0BIG - DDATA0 Register Big Endian Access (No Bit Access) (Actionable Reads) .
- Page 22 28.5.17 GPIO_IFS - Interrupt Flag Set Register ....939 28.5.18 GPIO_IFC - Interrupt Flag Clear Register ....940 28.5.19 GPIO_IEN - Interrupt Enable Register .
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Page 23: About This Document
Reference Manual About This Document 1. About This Document 1.1 Introduction This document contains reference material for the EFR32xG1 Wireless Gecko devices. All modules and peripherals in the EFR32xG1 Wireless Gecko devices are described in general terms. Not all modules are present in all devices and the feature set for each device might vary. -
Page 24: Related Documentation
Reference Manual About This Document Access Type Description RW(a), R(a), etc. "(a)" suffix indicates that register has actionable reads (see 7.3.6 Debugger Reads of Actionable Registers) Number format 0x prefix is used for hexadecimal numbers 0b prefix is used for binary numbers Numbers without prefix are in decimal representation. -
Page 25: System Overview
Reference Manual System Overview 2. System Overview Quick Facts What? The EFR32 Wireless Gecko is a highly integrated, configurable and low power wireless System-on- Chip (SoC) with a robust set of MCU and radio pe- ripherals. Why? The Radio enables support for Bluetooth Smart (BLE), ZigBee, Thread and Proprietary Protocols in 2.4 GHz and sub-GHz frequency bands while the MCU system allows customized protocols and appli-... -
Page 26: Block Diagrams
Reference Manual System Overview 2.2 Block Diagrams The block diagram for the EFR32xG1 Wireless Gecko System-On-Chip series is shown in (Figure 2.1 EFR32xG1 Wireless Gecko Sys- tem-On-Chip Block Diagram on page 26). Core / Memory Clock Management Energy Management Other High Frequency High Frequency Voltage... -
Page 27: Mcu Features Overview
Reference Manual System Overview 2.3 MCU Features Overview • ARMCortex-M4 CPU platform • High Performance 32-bit processor @ up to 40 MHz • Memory Protection Unit • Wake-up Interrupt Controller • Flexible Energy Management System • 5 Energy Modes from EM0 to EM4 provide flexibility between higher performance and low power •... -
Page 28: Oscillators And Clocks
Reference Manual System Overview • Ultra low power precision analog peripherals • 12-bit 1 Msamples/s Analog to Digital Converter • 8 input channels and on-chip temperature sensor • Single ended or differential operation • Conversion tailgating for predictable latency • Current Digital to Analog Converter •... -
Page 29: Rf Frequency Synthesizer
Reference Manual System Overview 2.5 RF Frequency Synthesizer The Fractional-N RF Frequency Synthesizer (SYNTH) provides a low phase noise LO signal to be used in both receive and transmit modes. The capabilities of the SYNTH include: • High performance, low phase noise •... -
Page 30: Data Buffering
Reference Manual System Overview 2.9 Data Buffering EFR32xG1 Wireless Gecko supports buffered transmit and receive modes through its buffer controller (BUFC), with four individually configurable buffers. The BUFC uses the system RAM as storage, and each buffer can be individually configured with parameters such •... -
Page 31: Convolutional Encoding / Decoding
Reference Manual System Overview 2.13 Convolutional Encoding / Decoding EFR32xG1 Wireless Gecko includes hardware support for convolutional encoding and decoding, for forward error correction (FEC). This feature is performed by the Frame Controller (FRC) module: • Constraint length configurable up to 7, for the highest robustness •... -
Page 32: Timers
Reference Manual System Overview 2.16 Timers EFR32xG1 Wireless Gecko includes multiple timers, as can be seen from Table 2.3 EFR32xG1 Wireless Gecko Timers Overview on page Table 2.3. EFR32xG1 Wireless Gecko Timers Overview Timer Number of instances Typical clock source Overview RTCC Low frequency (LFXO or... -
Page 33: System Processor
Reference Manual System Processor 3. System Processor Quick Facts What? The industry leading Cortex-M4 processor from ARM is the CPU in the EFR32xG1 Wireless Gecko devices. Why? The ARM Cortex-M4 is designed for exceptionally short response time, high code density, and high 32- CM4 Core bit throughput while maintaining a strict cost and power consumption budget. -
Page 34: Features
Reference Manual System Processor 3.2 Features • Harvard architecture • Separate data and program memory buses (No memory bottleneck as in a single bus system) • 3-stage pipeline • Thumb-2 instruction set • Enhanced levels of performance, energy efficiency, and code density •... -
Page 35: Interrupt Operation
Reference Manual System Processor 3.3.1 Interrupt Operation Module Cortex-M NVIC IFS[n] IFC[n] IEN[n] SETENA[n]/CLRENA[n] Active interrupt Interrupt clear Interrupt request IF[n] condition clear SETPEND[n]/CLRPEND[n] Software generated interrupt Figure 3.1. Interrupt Operation The interrupt request (IRQ) lines are connected to the Cortex-M4. Each of these lines (shown in Table 3.1 Interrupt Request Lines (IRQ) on page 36) is connected to one or more interrupt flags in one or more modules. -
Page 36: Interrupt Request Lines (Irq)
Reference Manual System Processor 3.3.2 Interrupt Request Lines (IRQ) Table 3.1. Interrupt Request Lines (IRQ) IRQ # Source(s) WDOG0 LDMA GPIO_EVEN TIMER0 USART0_RX USART0_TX ACMP0 ACMP1 ADC0 IDAC0 I2C0 GPIO_ODD TIMER1 USART1_RX USART1_TX LEUART0 PCNT0 CRYPTO LETIMER0 RTCC CRYOTIMER FPUEH silabs.com | Building a more connected world. -
Page 37: Memory And Bus System
Reference Manual Memory and Bus System 4. Memory and Bus System Quick Facts What? A low latency memory system including low energy Flash and RAM with data retention which makes the energy modes attractive. Why? RAM retention reduces the need for storing data in Flash and enables frequent use of the ultra low en- ergy modes EM2 DeepSleep and EM3 Stop. -
Page 38: Introduction
Reference Manual Memory and Bus System 4.1 Introduction The EFR32xG1 Wireless Gecko contains an AMBA AHB Bus system to allow bus masters to access the memory mapped address space. A multilayer AHB bus matrix connects the 5 master bus interfaces to the AHB slaves (Figure 4.1 EFR32xG1 Wireless Gecko Bus System on page 38). -
Page 39: Functional Description
Reference Manual Memory and Bus System 4.2 Functional Description The memory segments are mapped together with the internal segments of the Cortex-M4 into the system memory map shown by Fig- ure 4.2 System Address Space With Core and Code Space Listing on page Figure 4.2. - Page 40 Reference Manual Memory and Bus System Figure 4.3. System Address Space With Peripheral Listing The embedded SRAM is located at address 0x20000000 in the memory map of the EFR32xG1 Wireless Gecko. When running code located in SRAM starting at this address, the Cortex-M4 uses the System bus interface to fetch instructions. This results in reduced performance as the Cortex-M4 accesses stack, other data in SRAM and peripherals using the System bus interface.
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Page 41: Peripheral Non-Word Access Behavior
Reference Manual Memory and Bus System 4.2.1 Peripheral Non-Word Access Behavior When writing to peripheral registers, all accesses are treated as 32-bit accesses. This means that writes to a register need to be large enough to cover all bits of register, otherwise, any uncovered bits may become corrupted from the partial-word transfer. Thus, the saf- est practice is to always do 32-bit writes to peripheral registers. -
Page 42: Peripheral Bit Set And Clear
Reference Manual Memory and Bus System 4.2.3 Peripheral Bit Set and Clear The EFR32xG1 Wireless Gecko supports bit set and bit clear access to all peripherals except those listed in Table 4.1 Peripherals that Do Not Support Bit Set and Bit Clear on page 42. -
Page 43: Peripherals
Reference Manual Memory and Bus System 4.2.4 Peripherals The peripherals are mapped into the peripheral memory segment, each with a fixed size address range according to Table 4.2 Periph- erals on page Table 4.3 Low Energy Peripherals on page 43 , and Table 4.4 Core Peripherals on page Table 4.2. - Page 44 Reference Manual Memory and Bus System 4.2.5.1 Arbitration The Bus Matrix uses a round-robin arbitration algorithm which enables high throughput and low latency, while starvation of simultane- ous accesses to the same bus slave are eliminated. Round-robin does not assign a fixed priority to each bus master. The arbiter does not insert any bus wait-states during peak interaction.
- Page 45 Reference Manual Memory and Bus System 4.2.5.2.2 WS1 Mode In general, when accessing a peripheral, the latency in number of HFCLK cycles, not including master arbitration, is given by: × f + 2, best-case write accesses bus cycles slave cycles HFCLK PERCLK ×...
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Page 46: Access To Low Energy Peripherals (Asynchronous Registers)
Reference Manual Memory and Bus System 4.3 Access to Low Energy Peripherals (Asynchronous Registers) The Low Energy Peripherals are capable of running when the high frequency oscillator and core system is powered off, i.e. in energy mode EM2 DeepSleep and in some cases also EM3 Stop. This enables the peripherals to perform tasks while the system energy con- sumption is minimal. - Page 47 Reference Manual Memory and Bus System 4.3.1.1 Delayed Synchronization After writing data to a register which value is to be synchronized into the Low Energy Peripheral using delayed synchronization, a corre- sponding busy flag in the <module_name>_SYNCBUSY register (e.g. LETIMER_SYNCBUSY) is set. This flag is set as long as syn- chronization is in progress and is cleared upon completion.
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Page 48: Reading
Reference Manual Memory and Bus System 4.3.2 Reading When reading from a Low Energy Peripheral, the data read is synchronized regardless if it originates in the Low Energy clock domain or High Frequency clock domain. See Figure 4.13 Read Operation From Low Energy Peripherals on page 48 for an overview of the reading operation. -
Page 49: Sram
Reference Manual Memory and Bus System 4.5 SRAM The primary task of the SRAM memory is to store application data. Additionally, it is possible to execute instructions from SRAM, and the DMA may be set up to transfer data between the SRAM, flash and peripherals. •... -
Page 50: Di Page Entry Map
Reference Manual Memory and Bus System 4.6 DI Page Entry Map The DI page contains production calibration data as well as device identification information. See the peripheral chapters for how each calibration value is to be used with the associated peripheral. The offset address is relative to the start address of the DI page (see 8.3 Functional Description). -
Page 51: Di Page Entry Description
Reference Manual Memory and Bus System Offset Name Type Description 0x110 AUXHFRCOCAL12 AUXHFRCO Calibration Register (38 MHz) 0x140 VMONCAL0 VMON Calibration Register 0 0x144 VMONCAL1 VMON Calibration Register 1 0x148 VMONCAL2 VMON Calibration Register 2 0x158 IDAC0CAL0 IDAC0 Calibration Register 0 0x15C IDAC0CAL1 IDAC0 Calibration Register 1... -
Page 52: Moduleinfo - Module Trace Information
Reference Manual Memory and Bus System 4.7.2 MODULEINFO - Module trace information Offset Bit Position 0x004 Access Name Name Access Description 31:20 RESERVED1 Reserved for future use HFXOCALVAL HFXO Calibration Valid Value Mode Description VALID XOCAL_HFXOCTUNE is valid NOTVALID XOCAL_HFXOCTUNE is not valid LFXOCALVAL LFXO Calibration Valid Value... -
Page 53: Modxocal - Module Crystal Oscillator Calibration
Reference Manual Memory and Bus System Name Access Description 14:8 MODNUMBER Module Numbers, indicates radio performance and frequency band. ANTENNA Module Antenna Type Value Mode Description BUILTIN Built-in Antenna CONNECTOR RF Connector RFPAD RF Pad HWREV Module Hardware Revision. Starting from 0. 4.7.3 MODXOCAL - Module Crystal Oscillator Calibration Offset Bit Position... -
Page 54: Extinfo - External Component Description
Reference Manual Memory and Bus System 4.7.4 EXTINFO - External Component description Offset Bit Position 0x020 Access Name Name Access Description 31:24 Reserved Reserved for future use 23:16 MCM Revision Value Mode Description REV1 Revision 1 NONE No external component present 15:8 CONNECTION Connection protocal to external interface... -
Page 55: Eui48L - Eui48 Oui And Unique Identifier
Reference Manual Memory and Bus System 4.7.5 EUI48L - EUI48 OUI and Unique identifier Offset Bit Position 0x028 Access Name Name Access Description 31:24 OUI48L Lower Octet of EUI48 Organizationally Unique Identifier 23:0 UNIQUEID Unique identifier 4.7.6 EUI48H - OUI Offset Bit Position 0x02C... -
Page 56: Meminfo - Flash Page Size And Misc. Chip Information
Reference Manual Memory and Bus System 4.7.8 MEMINFO - Flash page size and misc. chip information Offset Bit Position 0x034 Access Name Name Access Description 31:24 FLASH_PAGE_SIZE Flash page size in bytes coded as 2 ^ ((MEM_IN- FO_PAGE_SIZE + 10) & 0xFF). Ie. the value 0xFF = 512 bytes. 23:16 PINCOUNT Device pin count as unsigned integer (eg. -
Page 57: Uniquel - Low 32 Bits Of Device Unique Number
Reference Manual Memory and Bus System 4.7.9 UNIQUEL - Low 32 bits of device unique number Offset Bit Position 0x040 Access Name Name Access Description 31:0 UNIQUEL Low 32 bits of device unique number 4.7.10 UNIQUEH - High 32 bits of device unique number Offset Bit Position 0x044... -
Page 58: Part - Part Description
Reference Manual Memory and Bus System 4.7.12 PART - Part description Offset Bit Position 0x04C Access Name Name Access Description 31:24 PROD_REV Production revision as unsigned integer 23:16 DEVICE_FAMILY Device Family Value Mode Description EFR32MG1P EFR32 Gecko Family Series 1 Device Config 1 EFR32MG1B EFR32 Gecko Family Series 1 Device Config 1 EFR32MG1V... - Page 59 Reference Manual Memory and Bus System Name Access Description EFR32BG13V EFR32 Gecko Family Series 1 Device Config 3 EFR32ZG13P EFR32 Gecko Family Series 1 Device Config 3 EFR32FG13P EFR32 Gecko Family Series 1 Device Config 3 EFR32FG13B EFR32 Gecko Family Series 1 Device Config 3 EFR32FG13V EFR32 Gecko Family Series 1 Device Config 3 EFR32MG14P...
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Page 60: Devinforev - Device Information
Reference Manual Memory and Bus System Name Access Description EZR32WG EZR32 Gecko Device Family EZR32HG EZR32 Gecko Device Family 15:0 DEVICE_NUMBER Part number as unsigned integer (e.g., 233 for EFR32BG1P233F256GM48-B0) 4.7.13 DEVINFOREV - Device information page revision Offset Bit Position 0x050 Access Name... -
Page 61: Adc0Cal0 - Adc0 Calibration Register 0
Reference Manual Memory and Bus System 4.7.15 ADC0CAL0 - ADC0 calibration register 0 Offset Bit Position 0x060 Access Name Name Access Description Reserved Reserved for future use 30:24 GAIN2V5 Gain for 2.5V reference 23:20 NEGSEOFFSET2V5 Negative single ended offset for 2.5V reference 19:16 OFFSET2V5 Offset for 2.5V reference... -
Page 62: Adc0Cal1 - Adc0 Calibration Register 1
Reference Manual Memory and Bus System 4.7.16 ADC0CAL1 - ADC0 calibration register 1 Offset Bit Position 0x064 Access Name Name Access Description Reserved Reserved for future use 30:24 GAIN5VDIFF Gain for for 5V differential reference 23:20 NEGSEOFFSET5VDIFF Negative single ended offset with for 5V differential reference 19:16 OFFSET5VDIFF Offset for 5V differential reference... -
Page 63: Adc0Cal2 - Adc0 Calibration Register 2
Reference Manual Memory and Bus System 4.7.17 ADC0CAL2 - ADC0 calibration register 2 Offset Bit Position 0x068 Access Name Name Access Description Reserved Reserved for future use 30:24 Reserved Reserved for future use 23:20 Reserved Reserved for future use 19:16 Reserved Reserved for future use 15:8... -
Page 64: Hfrcocal0 - Hfrco Calibration Register (4 Mhz)
Reference Manual Memory and Bus System 4.7.19 HFRCOCAL0 - HFRCO Calibration Register (4 MHz) Offset Bit Position 0x080 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Refer- ence FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide... -
Page 65: Hfrcocal3 - Hfrco Calibration Register (7 Mhz)
Reference Manual Memory and Bus System 4.7.20 HFRCOCAL3 - HFRCO Calibration Register (7 MHz) Offset Bit Position 0x08C Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Refer- ence FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide... -
Page 66: Hfrcocal6 - Hfrco Calibration Register (13 Mhz)
Reference Manual Memory and Bus System 4.7.21 HFRCOCAL6 - HFRCO Calibration Register (13 MHz) Offset Bit Position 0x098 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Refer- ence FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide... -
Page 67: Hfrcocal7 - Hfrco Calibration Register (16 Mhz)
Reference Manual Memory and Bus System 4.7.22 HFRCOCAL7 - HFRCO Calibration Register (16 MHz) Offset Bit Position 0x09C Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Refer- ence FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide... -
Page 68: Hfrcocal8 - Hfrco Calibration Register (19 Mhz)
Reference Manual Memory and Bus System 4.7.23 HFRCOCAL8 - HFRCO Calibration Register (19 MHz) Offset Bit Position 0x0A0 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Refer- ence FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide... -
Page 69: Hfrcocal10 - Hfrco Calibration Register (26 Mhz)
Reference Manual Memory and Bus System 4.7.24 HFRCOCAL10 - HFRCO Calibration Register (26 MHz) Offset Bit Position 0x0A8 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Refer- ence FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide... -
Page 70: Hfrcocal11 - Hfrco Calibration Register (32 Mhz)
Reference Manual Memory and Bus System 4.7.25 HFRCOCAL11 - HFRCO Calibration Register (32 MHz) Offset Bit Position 0x0AC Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Refer- ence FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide... -
Page 71: Hfrcocal12 - Hfrco Calibration Register (38 Mhz)
Reference Manual Memory and Bus System 4.7.26 HFRCOCAL12 - HFRCO Calibration Register (38 MHz) Offset Bit Position 0x0B0 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Refer- ence FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide... -
Page 72: Auxhfrcocal0 - Auxhfrco Calibration Register (4 Mhz)
Reference Manual Memory and Bus System 4.7.27 AUXHFRCOCAL0 - AUXHFRCO Calibration Register (4 MHz) Offset Bit Position 0x0E0 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide... -
Page 73: Auxhfrcocal3 - Auxhfrco Calibration Register (7 Mhz)
Reference Manual Memory and Bus System 4.7.28 AUXHFRCOCAL3 - AUXHFRCO Calibration Register (7 MHz) Offset Bit Position 0x0EC Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide... -
Page 74: Auxhfrcocal6 - Auxhfrco Calibration Register (13 Mhz)
Reference Manual Memory and Bus System 4.7.29 AUXHFRCOCAL6 - AUXHFRCO Calibration Register (13 MHz) Offset Bit Position 0x0F8 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide... -
Page 75: Auxhfrcocal7 - Auxhfrco Calibration Register (16 Mhz)
Reference Manual Memory and Bus System 4.7.30 AUXHFRCOCAL7 - AUXHFRCO Calibration Register (16 MHz) Offset Bit Position 0x0FC Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide... -
Page 76: Auxhfrcocal8 - Auxhfrco Calibration Register (19 Mhz)
Reference Manual Memory and Bus System 4.7.31 AUXHFRCOCAL8 - AUXHFRCO Calibration Register (19 MHz) Offset Bit Position 0x100 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide... -
Page 77: Auxhfrcocal10 - Auxhfrco Calibration Register (26 Mhz)
Reference Manual Memory and Bus System 4.7.32 AUXHFRCOCAL10 - AUXHFRCO Calibration Register (26 MHz) Offset Bit Position 0x108 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide... -
Page 78: Auxhfrcocal11 - Auxhfrco Calibration Register (32 Mhz)
Reference Manual Memory and Bus System 4.7.33 AUXHFRCOCAL11 - AUXHFRCO Calibration Register (32 MHz) Offset Bit Position 0x10C Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide... -
Page 79: Auxhfrcocal12 - Auxhfrco Calibration Register (38 Mhz)
Reference Manual Memory and Bus System 4.7.34 AUXHFRCOCAL12 - AUXHFRCO Calibration Register (38 MHz) Offset Bit Position 0x110 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide... -
Page 80: Vmoncal0 - Vmon Calibration Register 0
Reference Manual Memory and Bus System 4.7.35 VMONCAL0 - VMON Calibration Register 0 Offset Bit Position 0x140 Access Name Name Access Description 31:28 ALTAVDD2V98THRESCOARSE ALTAVDD 2.98 V Coarse Threshold Adjust 27:24 ALTAVDD2V98THRESFINE ALTAVDD 2.98 V Fine Threshold Adjust 23:20 ALTAVDD1V86THRESCOARSE ALTAVDD 1.86 V Coarse Threshold Adjust 19:16 ALTAVDD1V86THRESFINE... -
Page 81: Vmoncal1 - Vmon Calibration Register 1
Reference Manual Memory and Bus System 4.7.36 VMONCAL1 - VMON Calibration Register 1 Offset Bit Position 0x144 Access Name Name Access Description 31:28 IO02V98THRESCOARSE IO0 2.98 V Coarse Threshold Adjust 27:24 IO02V98THRESFINE IO0 2.98 V Fine Threshold Adjust 23:20 IO01V86THRESCOARSE IO0 1.86 V Coarse Threshold Adjust 19:16 IO01V86THRESFINE... -
Page 82: Vmoncal2 - Vmon Calibration Register 2
Reference Manual Memory and Bus System 4.7.37 VMONCAL2 - VMON Calibration Register 2 Offset Bit Position 0x148 Access Name Name Access Description 31:28 FVDD2V98THRESCOARSE FVDD 2.98 V Coarse Threshold Adjust 27:24 FVDD2V98THRESFINE FVDD 2.98 V Fine Threshold Adjust 23:20 FVDD1V86THRESCOARSE FVDD 1.86 V Coarse Threshold Adjust 19:16 FVDD1V86THRESFINE... -
Page 83: Idac0Cal0 - Idac0 Calibration Register 0
Reference Manual Memory and Bus System 4.7.38 IDAC0CAL0 - IDAC0 Calibration Register 0 Offset Bit Position 0x158 Access Name Name Access Description 31:24 SOURCERANGE3TUNING Calibrated middle step (16) of current source mode range 3 23:16 SOURCERANGE2TUNING Calibrated middle step (16) of current source mode range 2 15:8 SOURCERANGE1TUNING Calibrated middle step (16) of current source mode range 1... -
Page 84: Idac0Cal1 - Idac0 Calibration Register 1
Reference Manual Memory and Bus System 4.7.39 IDAC0CAL1 - IDAC0 Calibration Register 1 Offset Bit Position 0x15C Access Name Name Access Description 31:24 SINKRANGE3TUNING Calibrated middle step (16) of current sink mode range 3 23:16 SINKRANGE2TUNING Calibrated middle step (16) of current sink mode range 2 15:8 SINKRANGE1TUNING Calibrated middle step (16) of current sink mode range 1... -
Page 85: Dcdclpvctrl0 - Dcdc Low-Power Vref Trim Register 0
Reference Manual Memory and Bus System 4.7.41 DCDCLPVCTRL0 - DCDC Low-power VREF Trim Register 0 Offset Bit Position 0x16C Access Name Name Access Description 31:24 1V8LPATT0LPCMPBIAS1 DCDC LPVREF Trim for 1.8V output, LPATT=0, LPCMPBIAS=1 23:16 1V2LPATT0LPCMPBIAS1 DCDC LPVREF Trim for 1.2V output, LPATT=0, LPCMPBIAS=1 15:8 1V8LPATT0LPCMPBIAS0 DCDC LPVREF Trim for 1.8V output, LPATT=0, LPCMPBIAS=0... -
Page 86: Dcdclpvctrl1 - Dcdc Low-Power Vref Trim Register 1
Reference Manual Memory and Bus System 4.7.42 DCDCLPVCTRL1 - DCDC Low-power VREF Trim Register 1 Offset Bit Position 0x170 Access Name Name Access Description 31:24 1V8LPATT0LPCMPBIAS3 DCDC LPVREF Trim for 1.8V output, LPATT=0, LPCMPBIAS=3 23:16 1V2LPATT0LPCMPBIAS3 DCDC LPVREF Trim for 1.2V output, LPATT=0, LPCMPBIAS=3 15:8 1V8LPATT0LPCMPBIAS2 DCDC LPVREF Trim for 1.8V output, LPATT=0, LPCMPBIAS=2... -
Page 87: Dcdclpvctrl2 - Dcdc Low-Power Vref Trim Register 2
Reference Manual Memory and Bus System 4.7.43 DCDCLPVCTRL2 - DCDC Low-power VREF Trim Register 2 Offset Bit Position 0x174 Access Name Name Access Description 31:24 3V0LPATT1LPCMPBIAS1 DCDC LPVREF Trim for 3.0V output, LPATT=1, LPCMPBIAS=1 23:16 1V8LPATT1LPCMPBIAS1 DCDC LPVREF Trim for 1.8V output, LPATT=1, LPCMPBIAS=1 15:8 3V0LPATT1LPCMPBIAS0 DCDC LPVREF Trim for 3.0V output, LPATT=1, LPCMPBIAS=0... -
Page 88: Dcdclpvctrl3 - Dcdc Low-Power Vref Trim Register 3
Reference Manual Memory and Bus System 4.7.44 DCDCLPVCTRL3 - DCDC Low-power VREF Trim Register 3 Offset Bit Position 0x178 Access Name Name Access Description 31:24 3V0LPATT1LPCMPBIAS3 DCDC LPVREF Trim for 3.0V output, LPATT=1, LPCMPBIAS=3 23:16 1V8LPATT1LPCMPBIAS3 DCDC LPVREF Trim for 1.8V output, LPATT=1, LPCMPBIAS=3 15:8 3V0LPATT1LPCMPBIAS2 DCDC LPVREF Trim for 3.0V output, LPATT=1, LPCMPBIAS=3... -
Page 89: Dcdclpcmphyssel1 - Dcdc Lpcmphyssel Trim Register 1
Reference Manual Memory and Bus System 4.7.46 DCDCLPCMPHYSSEL1 - DCDC LPCMPHYSSEL Trim Register 1 Offset Bit Position 0x180 Access Name Name Access Description 31:24 LPCMPHYSSELLPCMPBIAS3 DCDC LPCMPHYSSEL Trim, LPCMPBIAS=3 23:16 LPCMPHYSSELLPCMPBIAS2 DCDC LPCMPHYSSEL Trim, LPCMPBIAS=2 15:8 LPCMPHYSSELLPCMPBIAS1 DCDC LPCMPHYSSEL Trim, LPCMPBIAS=1 LPCMPHYSSELLPCMPBIAS0 DCDC LPCMPHYSSEL Trim, LPCMPBIAS=0 silabs.com | Building a more connected world. -
Page 90: Serial Flash
Reference Manual Serial Flash 5. Serial Flash Quick Facts What? A 512 kB serial flash memory is included in the package for certain part numbers. Why? The serial flash memory extends the non-volatile storage capabilites of the device while maintaining a small PCB footprint. -
Page 91: Functional Description
Reference Manual Serial Flash 5.3 Functional Description The serial flash is powered from IOVDD and bonded to internal GPIO which are not available externally. USART1 is connected to the associated GPIO pins and functions as a SPI interface to the flash. It is recommended to use the software libraries supplied by Silicon Laboratories for interfacing to the serial flash. -
Page 92: Memory Organization
Reference Manual Serial Flash 5.3.1 Memory Organization The memory array of the serial flash is divided into uniform 4 kB sectors or uniform 32/64 kB blocks consisting of eight or sixteen adja- cent sectors, respectively. Table 5.1 Block and Sector Addresses on page 92 diagrams the organization of this memory space. -
Page 93: Serial Interface
Reference Manual Serial Flash 5.3.2 Serial Interface Serial flash operations are controlled through a SPI interface on the flash. Internal to the package, the flash interface I/O are connected to GPIO on the MCU. USART1 may be routed to the serial interface for hardware-controlled bus writes and reads. USART1 (SPI Mode 0) GPIO Name Serial Flash... - Page 94 Reference Manual Serial Flash 5.3.2.2 Timing All data is shifted into and out of the serial flash MSB-first. Data is shifted on the falling edge of SCK and latched on the rising edge of SCK. Transfer format for a single byte is shown in Figure 5.2 Serial Interface Data Format on page DI 7 DI 6...
- Page 95 Reference Manual Serial Flash Parameter Symbol Units Output Disable Time 5.3.2.3 Hold Operation When the device is selected with CEn and a serial sequence is underway, HOLDn can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, bring the HOLDn signal low while the SCK signal is low. When HOLDn is asserted, inputs to SI will be ignored, and SO will be high impedance.
- Page 96 Reference Manual Serial Flash 5.3.2.4 Power Up and Power Down The serial flash is powered by the IOVDD supply pin, and will inhibit certain operations while it is powering on. Software should not attempt to access the serial flash for at least 1 ms after IOVDD reaches 2.3 V. Additionally, program and erase operations will be rejec- ted for up to 10 ms from the time IOVDD reaches 2.1 V.
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Page 97: Instruction Set
Reference Manual Serial Flash 5.3.3 Instruction Set The serial flash utilizes an 8-bit instruction register. See Table 5.3 Instruction Set Summary on page 97 for details on instructions and instruction codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on the Serial Data Input (SI). - Page 98 Reference Manual Serial Flash STATUS - Serial Flash Status Register Default Access Non-Volatile Non-Volatile Non-Volatile Volatile Volatile Name SRWD Reserved Name Default Access Description SRWD Status Register Write Disable. Non-Vol- atile The SRWD bit operates in conjunction with the Write Protection (WPn) signal to provide a hardware protection mode. When SRWD is cleared to 0, the STATUS register is not write-protected.
- Page 99 Reference Manual Serial Flash FUNCTION - Serial Flash Function Register Default Access Volatile Volatile Name IRL3 IRL2 IRL1 IRL0 ESUS PSUS Reserved Name Default Access Description IRL3 Information Row 3 Lock. This bit is used to lock information row 3. When set to 1, information row 3 cannot be programmed. This bit is one-time programmable (OTP).
- Page 100 Reference Manual Serial Flash 5.3.4.1 Read Status Register (RDSR, 0x05) 8 clocks 8 clocks 0x05 Read Data Figure 5.6. RDSR Instruction Format 5.3.4.2 Write Status Register (WRSR, 0x01) 8 clocks 8 clocks 0x01 Write Data Figure 5.7. WRSR Instruction Format 5.3.4.3 Read Function Register (RDFR, 0x48) 8 clocks 8 clocks...
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Page 101: Reading Memory
Reference Manual Serial Flash 5.3.4.4 Write Function Register (WRFR, 0x42) 8 clocks 8 clocks 0x42 Write Data Figure 5.9. WRFR Instruction Format 5.3.5 Reading Memory Reads of the serial flash memory space are performed with either the Read Data (RD) or Fast Read (FR) instruction. The Fast Read command is intended to allow for higher serial clock frequencies to be used for reading the serial flash data. -
Page 102: Programming And Erasing Memory
Reference Manual Serial Flash 5.3.5.2 Fast Read Data (FR, 0x0B) 8 clocks 24 clocks 8 clocks N x 8 clocks 0x0B Address (3 bytes) Dummy Read N data bytes Figure 5.11. FR Instruction Format 5.3.6 Programming and Erasing Memory The serial flash memory can be programmed (clearing bits to 0) in 1 to 256-byte pages. The entire 512 kB memory array may be erased (setting bits to 1) with a single command, or memory may be erased in defined 4 kB, 32 kB, or 64 kB blocks. - Page 103 Reference Manual Serial Flash Erase Sequence The memory array of the serial flash is organized into uniform 4Kbyte sectors or 32/64Kbyte uniform blocks (a block consists of eight/ sixteen adjacent sectors respectively). Before a byte is reprogrammed, the sector or block that contains the byte must be erased (eras- ing sets bits to 1).
- Page 104 Reference Manual Serial Flash 5.3.6.2 Write Enable (WREN, 0x06) 8 clocks 0x06 Figure 5.12. WREN Instruction Format 5.3.6.3 Write Disable (WRDI, 0x04) 8 clocks 0x04 Figure 5.13. WRDI Instruction Format 5.3.6.4 Page Program (PP, 0x02) 8 clocks 24 clocks N x 8 clocks 0x02 Address (3 bytes) Write N data bytes...
- Page 105 Reference Manual Serial Flash 5.3.6.5 Sector Erase (SER, 0xD7 / 0x20) 8 clocks 24 clocks 0xD7 or 0x20 Address (3 bytes) Figure 5.15. SER Instruction Format 5.3.6.6 Block Erase 32k (BER32, 0x52) 8 clocks 24 clocks 0x52 Address (3 bytes) Figure 5.16.
- Page 106 Reference Manual Serial Flash 5.3.6.8 Chip Erase (CER, 0xC7 / 0x60) 8 clocks 0xC7 or 0x60 Figure 5.18. CER Instruction Format 5.3.6.9 Program/Erase Suspend (PERSUS, 0x75 / 0xB0) 8 clocks 0x75 or 0xB0 Figure 5.19. PERSUS Instruction Format 5.3.6.10 Program/Erase Resume (PERRSM, 0x7A / 0x30) 8 clocks 0x7A or 0x30 Figure 5.20.
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Page 107: Write Protection
Reference Manual Serial Flash 5.3.7 Write Protection The serial flash supports both hardware and software write protection mechanisms to prevent accidental program or erasure. The block protect (BP) field in the STATUS register allows part or all of the memory area to be designated as write-protected. If a block is write- protected, no program or erase operations will affect the memory contents, unless a SECUNLOCK command is issued to first unlock the target sector. -
Page 108: Security Information Row And Unique Id
Reference Manual Serial Flash 5.3.7.1 Sector Unlock (SECUNLOCK, 0x26) 8 clocks 24 clocks 0x26 Address (3 bytes) Figure 5.21. SECUNLOCK Instruction Format 5.3.7.2 Sector Lock (SECLOCK, 0x24) 8 clocks 0x24 Figure 5.22. SECLOCK Instruction Format 5.3.8 Security Information Row and Unique ID The serial flash has some additional storage outside of the general memory array: one 16-byte pre-programmed, read-only Unique ID space, and a Security Information Row space comprised of an additional 4 x 256 bytes of one-time programmable information. - Page 109 Reference Manual Serial Flash Reading the Information Rows The Information Row Read (IRRD) instruction is used to read data stored in the securiy information rows. The IRRD instruction oper- ates like the FR instruction, but targets the information row space. , with each bit latched-in during the rising edge of SCK.
- Page 110 Reference Manual Serial Flash 5.3.8.1 Information Row Program (IRP, 0x62) 8 clocks 24 clocks N x 8 clocks 0x62 Address (3 bytes) Write N data bytes Figure 5.23. IRP Instruction Format 5.3.8.2 Information Row Read (IRRD, 0x68) 8 clocks 24 clocks 8 clocks N x 8 clocks 0x68...
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Page 111: Power Down
Reference Manual Serial Flash 5.3.9 Power Down The serial flash may be put into a low-power state using the Deep Power-down (DP) instruction. When a DP instruction is issued, the power-down state will be entered within a maximum of 3 μs after CEn is driven high. To wake the serial flash and ready it for new instructions, the Release Deep Power Down (RDPD) is used. - Page 112 Reference Manual Serial Flash 5.3.10.1 Reset Enable (RSTEN, 0x66) 8 clocks 0x66 Figure 5.28. RSTEN Instruction Format 5.3.10.2 Reset (RST, 0x99) 8 clocks 0x99 Figure 5.29. RST Instruction Format silabs.com | Building a more connected world. Rev. 1.3 | 112...
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Page 113: Radio Transceiver
Reference Manual Radio Transceiver 6. Radio Transceiver Quick Facts What? The Radio Transceiver provides access to transmit and receive data, radio settings and control inter- face. Why? The Radio Transceiver enables the user to commu- nicate using a wide range of data rates, modulation and frame formats. -
Page 114: Introduction
Reference Manual Radio Transceiver 6.1 Introduction The Radio Transceiver of the EFR32 enables the user to control a wide range of settings and options for tailoring radio operation pre- cisely to the users need. It provides access to the transmit and receive data buffers and supports both dynamic and static frame lengths, as well as automatic address filtering and CRC insertion/verification. -
Page 115: Dbg - Debug Interface
Reference Manual DBG - Debug Interface 7. DBG - Debug Interface Quick Facts What? The Debug Interface is used to program and debug EFR32xG1 Wireless Gecko devices. Why? The Debug Interface makes it easy to re-program and update the system in the field, and allows de- bugging with minimal I/O pin usage. -
Page 116: Debug Pins
Reference Manual DBG - Debug Interface 7.3.1 Debug Pins The following pins are the debug connections for the device: • Serial Wire Clock Input and Test Clock Input (SWCLKTCK) : This pin is enabled after power-up and has a built-in pull down. •... -
Page 117: Debug Lock
Reference Manual DBG - Debug Interface 7.3.3.5 User Flash Page CRC The CRCREQ command initiates a CRC calculation on a given Flash Page. The CRC is only available on the Main, User Data, and Lock Bit pages. It is highly recommended that the system bus is stalled before any CRCREQ commands are issued. The CRC calcula- tion uses the on chip CRC block configured in 32 bit CRC mode. -
Page 118: Debugger Reads Of Actionable Registers
Reference Manual DBG - Debug Interface 7.3.6 Debugger Reads of Actionable Registers Some peripheral registers cause particular actions when read, e.g FIFOs which pop and IFC registers which clear the IF flags when read. This can cause problems when debugging and the user wants to read the value without triggering the read action. For this rea- son, by default, the peripherals will not execute these triggered actions when an attached debugger is performing the read accesses through the AAP. -
Page 119: Register Description
Reference Manual DBG - Debug Interface 7.5 Register Description 7.5.1 AAP_CMD - Command Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SYSRESETREQ... -
Page 120: Aap_Status - Status Register
Reference Manual DBG - Debug Interface 7.5.3 AAP_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LOCKED AAP Locked... -
Page 121: Aap_Crccmd - Crc Command Register
Reference Manual DBG - Debug Interface 7.5.5 AAP_CRCCMD - CRC Command Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CRCREQ CRC Request... -
Page 122: Aap_Crcaddr - Crc Address Register
Reference Manual DBG - Debug Interface 7.5.7 AAP_CRCADDR - CRC Address Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:0 CRCADDR 0x00000000 Starting Page Address for CRC Execution Set this to the address the CRC executes on. 7.5.8 AAP_CRCRESULT - CRC Result Register Offset Bit Position... -
Page 123: Aap_Idr - Aap Identification Register
Reference Manual DBG - Debug Interface 7.5.9 AAP_IDR - AAP Identification Register Offset Bit Position 0x0FC Reset Access Name Name Reset Access Description 31:0 0x26E60011 AAP Identification Register Access port identification register in compliance with the ARM ADI v5 specification (JEDEC Manufacturer ID) . silabs.com | Building a more connected world. -
Page 124: Msc - Memory System Controller
Reference Manual MSC - Memory System Controller 8. MSC - Memory System Controller Quick Facts What? The user can perform flash memory read, read con- figuration and write operations through the Memory System Controller (MSC) . Why? 01000101011011100110010101110010 The MSC allows the application code, user data and flash lock bits to be stored in non-volatile flash mem- 01100111011110010010000001001101 ory. -
Page 125: Features
Reference Manual MSC - Memory System Controller 8.2 Features • AHB read interface • Scalable access performance to optimize the Cortex-M4 code interface • Zero wait-state access up to 25 MHz • Advanced energy optimization functionality • Conditional branch target prefetch suppression •... -
Page 126: Functional Description
Reference Manual MSC - Memory System Controller 8.3 Functional Description The size of the main block is device dependent. The largest size available is 256 KB (128 pages). The information block has 2 KB available for user data. The information block also contains chip configuration data located in a reserved area. The main block is map- ped to address 0x00000000 and the information block is mapped to address 0x0FE00000. -
Page 127: Lock Bits (Lb)
Reference Manual MSC - Memory System Controller 8.3.2 Lock Bits (LB) Page Description This page contains the following information: • Main block Page Lock Words (PLWs) • User data page Lock Word (ULWs) • Debug Lock Word (DLW) • Mass erase Lock Word (MLW) •... -
Page 128: Bootloader
Reference Manual MSC - Memory System Controller 8.3.4 Bootloader There is no separate bootloader area available on this device family. 8.3.5 Post-reset Behavior Calibration values are automatically written to registers by the MSC before application code startup. The values are also available to read from the DI page for later reference by software. -
Page 129: Suppressed Conditional Branch Target Prefetch (Scbtp)
Reference Manual MSC - Memory System Controller 8.3.7.3 Operation Above To run at frequencies higher than 25 MHz, MODE in MSC_READCTRL must be set to WS1 or WS1SCBTP. 8.3.8 Suppressed Conditional Branch Target Prefetch (SCBTP) MSC offers a special instruction fetch mode which optimizes energy consumption by cancelling Cortex-M4 conditional branch target prefetches. -
Page 130: Instruction Cache
Reference Manual MSC - Memory System Controller 8.3.10 Instruction Cache The MSC includes an instruction cache. The instruction cache for the internal flash memory is enabled by default, but can be disabled by setting IFCDIS in MSC_READCTRL. When enabled, the instruction cache typically reduces the number of flash reads significantly, thus saving energy. -
Page 131: Erase And Write Operations
Reference Manual MSC - Memory System Controller the interrupt routine. So, for example, if a cached function is called from the interrupt routine, the instructions for that function will be taken from the cache. The cache content is not retained in EM2, EM3 and EM4. The cache is therefore invalidated regardless of the setting of AIDIS in MSC_READCTRL when entering these energy modes. -
Page 132: Register Map
Reference Manual MSC - Memory System Controller 8.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 MSC_CTRL Memory System Control Register 0x004 MSC_READCTRL Read Control Register 0x008 MSC_WRITECTRL Write Control Register 0x00C MSC_WRITECMD Write Command Register... -
Page 133: Register Description
Reference Manual MSC - Memory System Controller 8.5 Register Description 8.5.1 MSC_CTRL - Memory System Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions IFCREADCLEAR... -
Page 134: Msc_Readctrl - Read Control Register
Reference Manual MSC - Memory System Controller 8.5.2 MSC_READCTRL - Read Control Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SCBTP... -
Page 135: Msc_Writectrl - Write Control Register
Reference Manual MSC - Memory System Controller Name Reset Access Description AIDIS Automatic Invalidate Disable When this bit is set the cache is not automatically invalidated when a write or page erase is performed. IFCDIS Internal Flash Cache Disable Disable instruction cache for internal flash memory. Reserved To ensure compatibility with future devices, always write bits to 0. -
Page 136: Msc_Writecmd - Write Command Register
Reference Manual MSC - Memory System Controller 8.5.4 MSC_WRITECMD - Write Command Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLEARWDATA... -
Page 137: Msc_Addrb - Page Erase/Write Address Buffer
Reference Manual MSC - Memory System Controller 8.5.5 MSC_ADDRB - Page Erase/Write Address Buffer Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:0 ADDRB 0x00000000 Page Erase or Write Address Buffer This register holds the page address for the erase or write operation. This register is loaded into the internal MSC_ADDR register when the LADDRIM field in MSC_WRITECMD is set. -
Page 138: Msc_Status - Status Register
Reference Manual MSC - Memory System Controller 8.5.7 MSC_STATUS - Status Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PCRUNNING Performance Counters Running... -
Page 139: Msc_If - Interrupt Flag Register
Reference Manual MSC - Memory System Controller 8.5.8 MSC_IF - Interrupt Flag Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICACHERR... -
Page 140: Msc_Ifs - Interrupt Flag Set Register
Reference Manual MSC - Memory System Controller 8.5.9 MSC_IFS - Interrupt Flag Set Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICACHERR... -
Page 141: Msc_Ifc - Interrupt Flag Clear Register
Reference Manual MSC - Memory System Controller 8.5.10 MSC_IFC - Interrupt Flag Clear Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICACHERR... -
Page 142: Msc_Ien - Interrupt Enable Register
Reference Manual MSC - Memory System Controller 8.5.11 MSC_IEN - Interrupt Enable Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICACHERR... -
Page 143: Msc_Lock - Configuration Lock Register
Reference Manual MSC - Memory System Controller 8.5.12 MSC_LOCK - Configuration Lock Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0... -
Page 144: Msc_Cachecmd - Flash Cache Command Register
Reference Manual MSC - Memory System Controller 8.5.13 MSC_CACHECMD - Flash Cache Command Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions STOPPC... -
Page 145: Msc_Cachemisses - Cache Misses Performance Counter
Reference Manual MSC - Memory System Controller 8.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 19:0... -
Page 146: Msc_Masslock - Mass Erase Lock Register
Reference Manual MSC - Memory System Controller 8.5.16 MSC_MASSLOCK - Mass Erase Lock Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0... -
Page 147: Msc_Startup - Startup Control
Reference Manual MSC - Memory System Controller 8.5.17 MSC_STARTUP - Startup Control Offset Bit Position 0x05C Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 30:28 STWS... -
Page 148: Msc_Cmd - Command Register
Reference Manual MSC - Memory System Controller 8.5.18 MSC_CMD - Command Register Offset Bit Position 0x074 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PWRUP Flash Power Up Command... -
Page 149: Ldma - Linked Dma Controller
Reference Manual LDMA - Linked DMA Controller 9. LDMA - Linked DMA Controller Quick Facts What? The LDMA controller can move data without CPU in- tervention, effectively reducing the energy consump- tion for a data transfer. Why? The LDMA can perform data transfers more energy efficiently than the CPU and allows autonomous op- Flash eration in low energy modes. -
Page 150: Features
Reference Manual LDMA - Linked DMA Controller 9.1.1 Features • Flexible Source and Destination transfers • Memory-to-memory • Memory-to-peripheral • Peripheral-to-memory • Peripheral-to-peripheral • DMA transfers triggered by peripherals, software, or linked list • Single or multiple data transfers for each peripheral or software request •... -
Page 151: Block Diagram
Reference Manual LDMA - Linked DMA Controller 9.2 Block Diagram An overview of the LDMA and the modules it interacts with is shown in Figure 9.1 LDMA Block Diagram on page 151. Cortex Interrupts LDMA Core Error Channel done Channel 0 Peripheral Channel 1 Peripheral... -
Page 152: Functional Description
Reference Manual LDMA - Linked DMA Controller 9.3 Functional Description The Linked DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement from the processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of data or avoiding frequent interrupts to service peripherals needing more data or having available data. - Page 153 Reference Manual LDMA - Linked DMA Controller 9.3.1.3 Block Size The block size defines the amount of data transferred in one arbitration. It consists of one or more DMA transfers. See 9.3.6.1 Arbitra- tion Priority for more details. 9.3.1.4 Transfer Count The descriptor transfer count defines how many DMA transfers to perform.
- Page 154 Reference Manual LDMA - Linked DMA Controller 9.3.1.8 Byte Swap Enabling byte swap reverses the endianness of the incoming source data read into the LDMA’s FIFO. Byte swap is only valid for trans- fer sizes of word and half-word. Note that linked structure reads are not byte swapped. B3b7 B3b0 B2b7...
- Page 155 Reference Manual LDMA - Linked DMA Controller 9.3.1.9 DMA Size and Source/Destination Increment Programming The DMA channels’ SIZE, SRCINC, and DSTINC bit-fields are programmed to best utilize memory resources. They provide a means for memory packing and unpacking, as well as for matching the size of data being transmitted to or received from an IO peripheral. The following figure shows how 32-bit words of data are read from a memory source into the DMA’s internal transfer FIFO, and then written out to the memory destination.
- Page 156 Reference Manual LDMA - Linked DMA Controller Memory Memory source source 0x200 0x200 First read transmit data= First read transmit data= DMA Controller FIFO DMA Controller FIFO destination destination 0x400 0x400 First write transmit data= First write transmit data= size[1:0] = HALF size[1:0] = HALF src_inc[1:0] = WORD src_inc[1:0] = HALF...
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Page 157: Channel Configuration
Reference Manual LDMA - Linked DMA Controller 9.3.2 Channel Configuration Each DMA channel has associated configuration and loop counter registers for controlling direction of address increment , arbitration slots, and descriptor looping. 9.3.2.1 Address Increment/Decrement Normally DMA transfers increment the source and destination addresses after each DMA transfer. Each channel is also capable of dec- rementing the source and/or destination addresses after each DMA transfer. -
Page 158: Managing Transfer Errors
Reference Manual LDMA - Linked DMA Controller 9.3.4.1 Peripheral Transfer Requests By default peripherals issue a Single Request (SREQ) when any data is present. For peripherals with a data buffer or FIFO this occurs any time the FIFO is not empty. Upon receiving an SREQ the LDMA will perform one DMA transfer and stop till another request is made. - Page 159 Reference Manual LDMA - Linked DMA Controller Table 9.1. Arbitration Slot Order Arbslot order Arbslot1 Arbslot2 Arbslot4 Arbslot8 The top row shows the order at which the arbitration slots are executed. The remaining part of the table shows a more visual interpreta- tion of the arbitration order.
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Page 160: Channel Descriptor Data Structure
Reference Manual LDMA - Linked DMA Controller 9.3.6.2 DMA Transfer Arbitration In addition to the inter channel arbitration, software can configure when the controller arbitrates during a DMA transfer. This provides reduced latency to higher priority channels when configuring low priority transfers with more arbitration cycles. The LDMA provides four bits that configure how many DMA transfers occur before it re-arbitrates. - Page 161 Reference Manual LDMA - Linked DMA Controller 9.3.7.1 XFER Descriptor Structure This descriptor defines a typical data transfer which may be a Normal, Link, or Loop transfer. Only this structure type can be written directly into LDMA's registers by the CPU. All descriptors may be linked to. Refer to the register descriptions for additional information.
- Page 162 Reference Manual LDMA - Linked DMA Controller 9.3.7.2 SYNC Descriptor Structure This descriptor defines an intra-channel synchronizing structure. It allows the channel to wait for some external stimulus before continu- ing on to the next descriptor. This structure is also used to provide stimulus to another channel to indicate that it may continue. For example channel 1 may be configured to transfer a header into a buffer while channel 2 is simultaneously transferring data into the same structure.
- Page 163 Reference Manual LDMA - Linked DMA Controller Name Description This bit-field serves as the SYNCTRIG match value. A sync match triggers the load of the next linked DMA structure as specified by link_mode, when: (SYNCTRIG & MATCHEN) == (MATCHVAL & MATCHEN). 9.3.7.3 WRI Descriptor Structure This descriptor defines a write-immediate structure.
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Page 164: Interaction With The Emu
Reference Manual LDMA - Linked DMA Controller 9.3.8 Interaction With the EMU The LDMA interacts with the Energy Management Unit (EMU) to allow transfers from a low energy peripheral while in EM2 DeepSleep. For example, when using the LEUART in EM2 DeepSleep the EMU can wake up the LDMA sufficiently long to allow data transfers to occur. -
Page 165: Single Direct Register Dma Transfer
Reference Manual LDMA - Linked DMA Controller 9.4.1 Single Direct Register DMA Transfer This simple example uses only the Channel Descriptor registers directly and does not use linking. Software writes directly to the LDMA channel registers. This example does not use a memory based descriptor list. This example is suitable for most simple transfers that are limited to transferring one block of data. -
Page 166: Descriptor Linked List
Reference Manual LDMA - Linked DMA Controller 9.4.2 Descriptor Linked List This example shows how to use a Linked List of descriptors. Each descriptor has a link address which points to the next descriptor in the list. A descriptor may be removed from the Linked list by altering the Link address of the one before it to point to the one after it. Descriptor Linked lists are useful when handling an array of buffers for communication data. - Page 167 Reference Manual LDMA - Linked DMA Controller To start execution of the linked list of descriptors: • Write the absolute address of the first descriptor to the LINKADR field of the LDMA_CH0_LINK register • Set the LINK bit of LDMA_CH0_LINK register. •...
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Page 168: Single Descriptor Looped Transfer
Reference Manual LDMA - Linked DMA Controller 9.4.3 Single Descriptor Looped Transfer This example demonstrates how to use looping using a single descriptor. This method allows a single DMA transfer to be repeated a specified number of times. The looping descriptor is stored in memory and reloaded by hardware. After a specified number of iterations, the transfer stops. -
Page 169: Descriptor List With Looping
Reference Manual LDMA - Linked DMA Controller 9.4.4 Descriptor List With Looping This example uses a descriptor list in memory with looping over multiple descriptors. This example also uses the looping feature and continues on with the next sequential descriptor after looping completes. The descriptor list in memory is shown in figure Figure 9.7 Descriptor List With Looping on page 169. -
Page 170: Simple Inter-Channel Synchronization
Reference Manual LDMA - Linked DMA Controller 9.4.5 Simple Inter-Channel Synchronization The LDMA controller features synchronization structures which allow differing channels and/or hardware events to pause a DMA se- quence, and wait for a synchronizing event to restart it. In this example DMA channel 0 and 1 are tasked with the transfer of different sets of data. Channel 0 has two transfer structures, and channel 1 just one, but channel 0 must wait until channel 1 has completed its transfer before it starts its second transfer structure. - Page 171 Reference Manual LDMA - Linked DMA Controller SYNC[7] STRUCTTYPE=-SYNC STRUCTTYPE=XFER wait SYNCTRIG[7]=1 STRUCTTYPE=XFER C not fetched until sync_trig[7] is set STRUCTTYPE=SYNC STRUCTTYPE=XFER set SYNC[7] Time Figure 9.8. Simple Intra-channel Synchronization Example Both A and Y effectively start at the same time. A finishes earlier, then it links to B, which waits for the SYNCTRIG[7] bit to be set before loading C.
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Page 172: Copy
Reference Manual LDMA - Linked DMA Controller 9.4.6 2D Copy The LDMA can easily perform a 2D copy using a descriptor list with looping. This set up is visualized in Figure 9.9 2D Copy on page 172. For an application working with graphics, this would mean the ability to copy a rectangle of a given width and height from one picture to another. - Page 173 Reference Manual LDMA - Linked DMA Controller Because the first descriptor already transferred one row, the number of looping repeats should be the desired height minus two. There- fore, LOOPCNT should be set to HEIGHT minus two before initiating the transfer. This same method is easily extended to copy multiple rectangles by linking descriptors together.
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Page 174: Ping-Pong
Reference Manual LDMA - Linked DMA Controller 9.4.7 Ping-Pong Communication peripherals often use ping-pong buffers. Ping-pong buffers allow the CPU to process data in one buffer while a periph- eral transmits or receives data in the other buffer. Both transmit and receive ping-pong buffers are easily implemented using the LDMA. In either case, this requires two descriptors as shown in Figure 9.10 Infinite Ping-Pong Example on page 174. -
Page 175: Scatter-Gather
Reference Manual LDMA - Linked DMA Controller continue to the second buffer. The LINK bit should be cleared to zero. Once software has loaded the first buffer, it will use the LINK- LOAD bit to load the first descriptor and transmit the data. The DONIFS need not be set in each descriptor. The DMA will stop and then generate an interrupt at the completion of each descriptor. -
Page 176: Register Map
Reference Manual LDMA - Linked DMA Controller 9.5 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LDMA_CTRL DMA Control Register 0x004 LDMA_STATUS DMA Status Register 0x008 LDMA_SYNC DMA Synchronization Trigger Register (Single-Cycle RMW) 0x020 LDMA_CHEN DMA Channel Enable Register (Single-Cycle RMW) -
Page 177: Register Description
Reference Manual LDMA - Linked DMA Controller Offset Name Type Description 0x1E4 LDMA_CH7_DST Channel Descriptor Destination Data Address Register 0x1E8 LDMA_CH7_LINK Channel Descriptor Link Structure Address Register 9.6 Register Description 9.6.1 LDMA_CTRL - DMA Control Register Offset Bit Position 0x000 Reset Access Name... -
Page 178: Ldma_Status - Dma Status Register
Reference Manual LDMA - Linked DMA Controller 9.6.2 LDMA_STATUS - DMA Status Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 28:24... -
Page 179: Ldma_Sync - Dma Synchronization Trigger Register (Single-Cycle Rmw)
Reference Manual LDMA - Linked DMA Controller 9.6.3 LDMA_SYNC - DMA Synchronization Trigger Register (Single-Cycle RMW) Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SYNCTRIG... -
Page 180: Ldma_Chbusy - Dma Channel Busy Register
Reference Manual LDMA - Linked DMA Controller 9.6.5 LDMA_CHBUSY - DMA Channel Busy Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions BUSY... -
Page 181: Ldma_Dbghalt - Dma Channel Debug Halt Register
Reference Manual LDMA - Linked DMA Controller 9.6.7 LDMA_DBGHALT - DMA Channel Debug Halt Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DBGHALT... -
Page 182: Ldma_Reqdis - Dma Channel Request Disable Register
Reference Manual LDMA - Linked DMA Controller 9.6.9 LDMA_REQDIS - DMA Channel Request Disable Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions REQDIS... -
Page 183: Ldma_Linkload - Dma Channel Link Load Register
Reference Manual LDMA - Linked DMA Controller 9.6.11 LDMA_LINKLOAD - DMA Channel Link Load Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LINKLOAD... -
Page 184: Ldma_If - Interrupt Flag Register
Reference Manual LDMA - Linked DMA Controller 9.6.13 LDMA_IF - Interrupt Flag Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description ERROR Transfer Error Interrupt Flag The ERRORIF flag is set when a read or write error occurs. The CHERROR field in the LDMA_STATUS register reflects the number of the channel which had the last error. -
Page 185: Ldma_Ifc - Interrupt Flag Clear Register
Reference Manual LDMA - Linked DMA Controller 9.6.15 LDMA_IFC - Interrupt Flag Clear Register Offset Bit Position 0x068 Reset Access Name Name Reset Access Description ERROR (R)W1 Clear ERROR Interrupt Flag Write 1 to clear the ERROR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.). -
Page 186: Ldma_Chx_Reqsel - Channel Peripheral Request Select Register
Reference Manual LDMA - Linked DMA Controller 9.6.17 LDMA_CHx_REQSEL - Channel Peripheral Request Select Register Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16... - Page 187 Reference Manual LDMA - Linked DMA Controller Name Reset Access Description 0b0000 ADC0SINGLE ADC0SINGLE REQ/SREQ 0b0001 ADC0SCAN ADC0SCAN REQ/SREQ SOURCESEL = 0b001100 (USART0) 0b0000 USART0RXDATAV USART0RXDATAV REQ/SREQ 0b0001 USART0TXBL USART0TXBL REQ/SREQ 0b0010 USART0TXEMPTY USART0TXEMPTY SOURCESEL = 0b001101 (USART1) 0b0000 USART1RXDATAV USART1RXDATAV REQ/SREQ 0b0001 USART1TXBL...
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Page 188: Ldma_Chx_Cfg - Channel Configuration Register
Reference Manual LDMA - Linked DMA Controller Name Reset Access Description 0b0011 CRYPTODATA1WR CRYPTODATA1WR 0b0100 CRYPTODATA1RD CRYPTODATA1RD 9.6.18 LDMA_CHx_CFG - Channel Configuration Register Offset Bit Position 0x084 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DSTINCSIGN... -
Page 189: Ldma_Chx_Loop - Channel Loop Counter Register
Reference Manual LDMA - Linked DMA Controller 9.6.19 LDMA_CHx_LOOP - Channel Loop Counter Register Offset Bit Position 0x088 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LOOPCNT... -
Page 190: Ldma_Chx_Ctrl - Channel Descriptor Control Word Register
Reference Manual LDMA - Linked DMA Controller 9.6.20 LDMA_CHx_CTRL - Channel Descriptor Control Word Register Offset Bit Position 0x08C Reset Access Name Name Reset Access Description DSTMODE Destination Addressing Mode This field specifies the destination addressing mode of linked descriptors. After loading a linked descriptor, reading this field will indicate the destination addressing mode of the linked descriptor. - Page 191 Reference Manual LDMA - Linked DMA Controller Name Reset Access Description 27:26 SIZE Unit Data Transfer Size This field specifies the size of data transferred. Value Mode Description BYTE Each unit transfer is a byte HALFWORD Each unit transfer is a half-word WORD Each unit transfer is a word 25:24...
- Page 192 Reference Manual LDMA - Linked DMA Controller Name Reset Access Description UNIT8 Eight unit transfers per arbitration UNIT16 Sixteen unit transfers per arbitration UNIT32 32 unit transfers per arbitration UNIT64 64 unit transfers per arbitration UNIT128 128 unit transfers per arbitration UNIT256 256 unit transfers per arbitration UNIT512...
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Page 193: Ldma_Chx_Src - Channel Descriptor Source Data Address Register
Reference Manual LDMA - Linked DMA Controller 9.6.21 LDMA_CHx_SRC - Channel Descriptor Source Data Address Register Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:0 SRCADDR 0x00000000 Source Data Address Writing to this register sets the source address. Reading from this register during a DMA transfer will indicate the next source read address. -
Page 194: Ldma_Chx_Link - Channel Descriptor Link Structure Address Register
Reference Manual LDMA - Linked DMA Controller 9.6.23 LDMA_CHx_LINK - Channel Descriptor Link Structure Address Register Offset Bit Position 0x098 Reset Access Name Name Reset Access Description 31:2 LINKADDR 0x00000000 Link Structure Address To use linking, write the address of the the first linked descriptor to this register. When a linked descriptor is loaded, it may also be linked to another descriptor. -
Page 195: Rmu - Reset Management Unit
Reference Manual RMU - Reset Management Unit 10. RMU - Reset Management Unit Quick Facts What? The RMU ensures correct reset operation. It is re- sponsible for connecting the different reset sources to the reset lines of the EFR32xG1 Wireless Gecko. Why? A correct reset sequence is needed to ensure safe RESETn... -
Page 196: Functional Description
Reference Manual RMU - Reset Management Unit 10.3 Functional Description The RMU monitors each of the reset sources of the EFR32xG1 Wireless Gecko. If one or more reset sources go active, the RMU ap- plies reset to the EFR32xG1 Wireless Gecko. When the reset sources go inactive the EFR32xG1 Wireless Gecko starts up. At startup the EFR32xG1 Wireless Gecko loads the stack pointer and program entry point from memory, and starts execution. -
Page 197: Reset Levels
Reference Manual RMU - Reset Management Unit 10.3.1 Reset Levels The reset sources on EFR32xG1 Wireless Gecko can be divided in two main groups; Hard resets and Soft resets. The soft resets can be configured to be either DISABLED, LIMITED, EXTENDED or FULL. The reset level for soft reset sources is configured in the xxxRMODE bitfields in RMU_CTRL. -
Page 198: Rmu_Rstcause Register
Reference Manual RMU - Reset Management Unit 10.3.2 RMU_RSTCAUSE Register Whenever a reset source is active, the corresponding bit in the RMU_RSTCAUSE register is set. At startup the program code may investigate this register in order to determine the cause of the reset. The register is cleared upon POR and software write to RMU_CMD_RCCLR. -
Page 199: Power-On Reset (Por)
Reference Manual RMU - Reset Management Unit 10.3.3 Power-On Reset (POR) The POR ensures that the EFR32xG1 Wireless Gecko does not start up before the AVDD supply voltage has reached the threshold voltage VPORthr (roughly 1.2V). Before the POR threshold voltage is reached, the EFR32xG1 Wireless Gecko is kept in reset state. The operation of the POR is illustrated in Figure 10.2 RMU Power-on Reset Operation on page 199, with the active low POWERONn... - Page 200 Reference Manual RMU - Reset Management Unit 10.3.5 RESETn Pin Reset The pin reset on EFR32xG1 Wireless Gecko can be configured to be either hard or soft. By default, pin reset is configured as a soft reset source. To configure it as a hard reset, clear the PINRESETSOFT bit in CLW0 in the Lock bit page, see 8.3.2 Lock Bits (LB) Page Description for details.
- Page 201 Reference Manual RMU - Reset Management Unit 10.3.10.1 Registers With Alternate Reset Table 10.3. Alternate Reset for Registers in RMU RMU Reset Levels POR and hard pin reset RMU_CTRL_WDOGRMODE RMU_CTRL_LOCKUPRMODE RMU_CTRL_SYSRMODE RMU_CTRL_PINRMODE RMU_CTRL_RESETSTATE FULL reset RMU_LOCK_LOCKKEY Table 10.4. Alternate Reset for Registers in CMU CMU Reset Levels FULL reset CMU_LFRCOCTRL...
- Page 202 Reference Manual RMU - Reset Management Unit EMU Reset Levels EXTENDED reset EMU_VMONAVDDCTRL EMU_VMONALTAVDDCTRL EMU_VMONDVDDCTRL EMU_VMONIO0CTRL EMU_VMONPAVDDCTRL FULL reset EMU_EM4CTRL 10.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 RMU_CTRL Control Register 0x004 RMU_RSTCAUSE...
- Page 203 Reference Manual RMU - Reset Management Unit 10.5 Register Description 10.5.1 RMU_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 25:24...
- Page 204 Reference Manual RMU - Reset Management Unit Name Reset Access Description LOCKUPRMODE Core LOCKUP Reset Mode Controls the reset level for Core LOCKUP reset request. Value Mode Description DISABLED Reset request is blocked. LIMITED The CRYOTIMER, DEBUGGER, RTCC, are not reset. EXTENDED The CRYOTIMER, DEBUGGER are not reset.
- Page 205 Reference Manual RMU - Reset Management Unit 10.5.2 RMU_RSTCAUSE - Reset Cause Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM4RST...
- Page 206 Reference Manual RMU - Reset Management Unit Name Reset Access Description PORST Power on Reset Set if a power on reset has been performed. Must be cleared by software. See Table 10.2 RMU Reset Cause Register Interpretation on page 198 for details on how to interpret this bit.
- Page 207 Reference Manual RMU - Reset Management Unit 10.5.5 RMU_LOCK - Configuration Lock Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
- Page 208 Reference Manual EMU - Energy Management Unit 11. EMU - Energy Management Unit Quick Facts What? The EMU (Energy Management Unit) handles the different low energy modes in EFR32xG1 Wireless Gecko Why? The need for performance and peripheral functions varies over time in most applications. By efficiently scaling the available resources in real time to match the demands of the application, the energy con- sumption can be kept at a minimum.
- Page 209 Reference Manual EMU - Energy Management Unit 11.3 Functional Description The EMU is responsible for managing the wide range of energy modes available in EFR32xG1 Wireless Gecko. The block works in harmony with the entire platform to easily transition between energy modes in the most efficient manner possible. The following dia- gram Figure 11.1 EMU Overview on page 209, shows the relative connectivity to the various blocks in the system.
- Page 210 Reference Manual EMU - Energy Management Unit 11.3.1 Energy Modes EFR32xG1 Wireless Gecko features six main energy modes, referred to as Energy Mode 0 (EM0 Active) through Energy Mode 4 (EM4 Shutoff). The Cortex-M4 is only available for program execution in EM0 Active. In EM0 Active/EM1 Sleep any peripheral function can be enabled.
- Page 211 Reference Manual EMU - Energy Management Unit EM2 Deep- EM3 Stop EM4 Hiber- EM4 Shutoff Active/EM1 Sleep nate Sleep High Frequency Oscillators (HFRCO, HFXO) and Available — — — — Clocks (HFSRCLK, HFCLK, HFCORECLK, HFBUSCLK, HFPERCLK, HFRADIOCLK, HFCLKLE) Auxiliary High Frequency Oscillator (AUXHFR- Available —...
- Page 212 Reference Manual EMU - Energy Management Unit EM2 Deep- EM3 Stop EM4 Hiber- EM4 Shutoff Active/EM1 Sleep nate Sleep Note: 1. Approximate time. Refer to the data sheet 2. Leaving the debugger connected when in EM2 or EM3 will cause the system to enter a higher power EM2 mode in which the high frequency clocks are still enabled and certain core functionality is still powered-up in order to maintain debug-functionality.
- Page 213 Reference Manual EMU - Energy Management Unit 11.3.1.3 EM2 DeepSleep This is the first level into the low power energy modes. Most of the high frequency peripherals are disabled or have reduced functionali- ty. Memory and registers retain their values. •...
- Page 214 Reference Manual EMU - Energy Management Unit 11.3.1.5 EM4 Hibernate The majority of peripherals are shutoff to reduce leakage power. A few selected peripherals are available. System memory and regis- ters do not retain values. GPIO PAD state and RTCC RAM are retained. Wake-up from EM4 Hibernate requires a reset to the system, returning it back to EM0 Active •...
- Page 215 Reference Manual EMU - Energy Management Unit 11.3.2.2 Entry Into EM2 DeepSleep or EM3 Stop Energy mode EM2 DeepSleep or EM3 Stop may be entered when all of the following conditions are true: • Radio RAC state machine is in OFF state •...
- Page 216 Reference Manual EMU - Energy Management Unit 11.3.3 Exiting a Low Energy Mode A system in EM2 DeepSleep and EM3 Stop can be woken up to EM0 Active through regular interrupt requests from active peripherals. Since state and RAM retention is available, the EFR32 is fully restored and can continue to operate as before it went into the Low Ener- gy Mode.
- Page 217 Reference Manual EMU - Energy Management Unit 11.3.4 Power Configurations The EFR32xG1 Wireless Gecko allows several power configurations with additional options giving flexible power architecture selection. In order to provide the lowest power consuming radio solutions, the EFR32xG1 Wireless Gecko comes with a DC-DC module to power internal circuits.
- Page 218 Reference Manual EMU - Energy Management Unit 11.3.4.1 Power Configuration 0: STARTUP Upon power-on reset (POR) or entry into EM4 Shutoff, the system is configured in a safe Startup Configuration that supports all of the available Power Configurations. The Startup Configuration is shown in the simplified diagram below. In the Startup Configuration: •...
- Page 219 Reference Manual EMU - Energy Management Unit 11.3.4.2 Power Configuration 1: No DC-DC In Power Configuration 1, the DC-DC converter is programmed in Off mode and the Bypass switch is Off. The DVDD pin must be pow- ered externally - typically, DVDD is connected to the main supply. IOVDD and AVDD are powered from the main supply as well. RFVDD and PAVDD, which power the radio, are shorted to the main supply as well.
- Page 220 Reference Manual EMU - Energy Management Unit 11.3.4.3 Power Configuration 2: DC-DC For the lowest power applications, the DC-DC converter can be used to power the DVDD supply, as well as RFVDD and PAVDD. In Power Configuration 2, the DC-DC Output (V ) is connected to DVDD.
- Page 221 Reference Manual EMU - Energy Management Unit Main Supply – IOVDD VREGVDD AVDD Bypass Switch FLASH DCDC DC-DC Driver VREGSW Analog DC-DC Blocks VREGVSS ANASW DVDD Digital Digital Power Logic Analog Amplifier DECOUPLE RFVDD PAVDD Figure 11.5. DC-DC High RF Power Configuration 11.3.5 DC-to-DC Interface The EFR32xG1 Wireless Gecko devices feature a DC-DC buck converter which requires a single external inductor and a single exter- nal capacitor.
- Page 222 Reference Manual EMU - Energy Management Unit 11.3.5.1 Bypass Mode In Bypass mode, the VREGVDD input voltage is directly shorted to the DC-DC converter output through an internal switch. Out of reset, the DC-DC converter defaults to Bypass mode. Consult the data sheet for the Bypass switch impedance specification. The Bypass Current Limit limits the maximum current drawn from the input supply in Bypass mode.
- Page 223 Reference Manual EMU - Energy Management Unit 11.3.5.3.2 Low Noise (LN) Discontinuous Conduction Mode (DCM) To enable DCM, the LNFORCECCM bit in EMU_DCDCMISCCTRL must be cleared before entering LN. Typically, this configuration would occur while the part was in Bypass mode. Once DCM is enabled, the DC-DC should operate in DCM at light load currents. How- ever, as the load current increases, the DC-DC will automatically transition into CCM without software intervention.
- Page 224 Reference Manual EMU - Energy Management Unit 11.3.8.1 AVDD BOD The EFR32xG1 Wireless Gecko has a fast response BOD on AVDD that is always active. This BOD ensures the minimal supply is provided to the AVDD supply (typically also connected to VREGVDD). Once triggered, the BOD will cause the system to reset. Note: In EM4 Hibernate/Shutoff a low power version of the AVDD BOD, called EM4BOD, is available to trigger a reset at level lower than in other energy modes.
- Page 225 Reference Manual EMU - Energy Management Unit 11.3.9 Voltage Monitor (VMON) The EFR32 features an extremely low energy Voltage Monitor (VMON) capable of running down to EM4 Hibernate. Trigger points are preloaded but may be reconfigured. • AVDD X 2 •...
- Page 226 Reference Manual EMU - Energy Management Unit • Using the above numbers and the VMON calibration equations: • T = 35 1.86 • T = 87 2.98 • V = 21.53 mV • V = 1.106 V • Using the VMON threshold equations (with Y=2.2 V), Thres = 51 (rounded from 50.8) and Y = 2.204 V calib...
- Page 227 Reference Manual EMU - Energy Management Unit 11.3.12 Registers latched in EM4 The following registers will be latched when entering EM4. After wake-up from EM4, these registers will be reset and require reprog- ramming prior to writing the EMU_CMD_EM4UNLATCH command. •...
- Page 228 Reference Manual EMU - Energy Management Unit 11.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 EMU_CTRL Control Register 0x004 EMU_STATUS Status Register 0x008 EMU_LOCK Configuration Lock Register 0x00C EMU_RAM0CTRL Memory Control Register 0x010 EMU_CMD...
- Page 229 Reference Manual EMU - Energy Management Unit 11.5 Register Description 11.5.1 EMU_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM2BLOCK...
- Page 230 Reference Manual EMU - Energy Management Unit 11.5.2 EMU_STATUS - Status Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RACACTIVE Radio Controller Active...
- Page 231 Reference Manual EMU - Energy Management Unit Name Reset Access Description VMONALTAVDD Alternate VMON AVDD Channel Indicates the status of the Alternate AVDD channel of the VMON. VMONAVDD VMON AVDD Channel Indicates the status of the AVDD channel of the VMON. VMONRDY VMON Ready VMON status.
- Page 232 Reference Manual EMU - Energy Management Unit 11.5.4 EMU_RAM0CTRL - Memory Control Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RAMHPOWER-...
- Page 233 Reference Manual EMU - Energy Management Unit 11.5.5 EMU_CMD - Command Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM4UNLATCH EM4 Unlatch...
- Page 234 Reference Manual EMU - Energy Management Unit 11.5.6 EMU_EM4CTRL - EM4 Control Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 17:16...
- Page 235 Reference Manual EMU - Energy Management Unit 11.5.7 EMU_TEMPLIMITS - Temperature Limits for Interrupt Generation Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM4WUEN...
- Page 236 Reference Manual EMU - Energy Management Unit 11.5.9 EMU_IF - Interrupt Flag Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description TEMPHIGH Temperature High Limit Reached Set when the value of a periodic temperature measurement is higher or equal than TEMPHIGH in EMU_TEMPLIMITS TEMPLOW Temperature Low Limit Reached Set when the value of a periodic temperature measurement is lower or equal than TEMPHIGH in EMU_TEMPLIMITS...
- Page 237 Reference Manual EMU - Energy Management Unit Name Reset Access Description VMONFVDDFALL VMON VDDFLASH Channel Fall A falling edge on VMON VDDFLASH channel has been detected. VMONPAVDDRISE VMON PAVDD Channel Rise A rising edge on VMON PAVDD channel has been detected. VMONPAVDDFALL VMON PAVDD Channel Fall A falling edge on VMON PAVDD channel has been detected.
- Page 238 Reference Manual EMU - Energy Management Unit 11.5.10 EMU_IFS - Interrupt Flag Set Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description TEMPHIGH Set TEMPHIGH Interrupt Flag Write 1 to set the TEMPHIGH interrupt flag TEMPLOW Set TEMPLOW Interrupt Flag Write 1 to set the TEMPLOW interrupt flag TEMP Set TEMP Interrupt Flag...
- Page 239 Reference Manual EMU - Energy Management Unit Name Reset Access Description VMONFVDDFALL Set VMONFVDDFALL Interrupt Flag Write 1 to set the VMONFVDDFALL interrupt flag VMONPAVDDRISE Set VMONPAVDDRISE Interrupt Flag Write 1 to set the VMONPAVDDRISE interrupt flag VMONPAVDDFALL Set VMONPAVDDFALL Interrupt Flag Write 1 to set the VMONPAVDDFALL interrupt flag 11:8 Reserved...
- Page 240 Reference Manual EMU - Energy Management Unit 11.5.11 EMU_IFC - Interrupt Flag Clear Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description TEMPHIGH (R)W1 Clear TEMPHIGH Interrupt Flag Write 1 to clear the TEMPHIGH interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
- Page 241 Reference Manual EMU - Energy Management Unit Name Reset Access Description PFETOVERCUR- (R)W1 Clear PFETOVERCURRENTLIMIT Interrupt Flag RENTLIMIT Write 1 to clear the PFETOVERCURRENTLIMIT interrupt flag. Reading returns the value of the IF and clears the corre- sponding interrupt flags (This feature must be enabled globally in MSC.). VMONFVDDRISE (R)W1 Clear VMONFVDDRISE Interrupt Flag...
- Page 242 Reference Manual EMU - Energy Management Unit 11.5.12 EMU_IEN - Interrupt Enable Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description TEMPHIGH TEMPHIGH Interrupt Enable Enable/disable the TEMPHIGH interrupt TEMPLOW TEMPLOW Interrupt Enable Enable/disable the TEMPLOW interrupt TEMP TEMP Interrupt Enable Enable/disable the TEMP interrupt...
- Page 243 Reference Manual EMU - Energy Management Unit Name Reset Access Description VMONFVDDFALL VMONFVDDFALL Interrupt Enable Enable/disable the VMONFVDDFALL interrupt VMONPAVDDRISE VMONPAVDDRISE Interrupt Enable Enable/disable the VMONPAVDDRISE interrupt VMONPAVDDFALL VMONPAVDDFALL Interrupt Enable Enable/disable the VMONPAVDDFALL interrupt 11:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions VMONIO0RISE...
- Page 244 Reference Manual EMU - Energy Management Unit 11.5.13 EMU_PWRLOCK - Regulator and Supply Lock Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
- Page 245 Reference Manual EMU - Energy Management Unit 11.5.14 EMU_PWRCFG - Power Configuration Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PWRCFG...
- Page 246 Reference Manual EMU - Energy Management Unit 11.5.16 EMU_DCDCCTRL - DCDC Control Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DCDCMODEEM4 DCDC Mode EM4H...
- Page 247 Reference Manual EMU - Energy Management Unit 11.5.17 EMU_DCDCMISCCTRL - DCDC Miscellaneous Control Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:28...
- Page 248 Reference Manual EMU - Energy Management Unit Name Reset Access Description 11:8 PFETCNT PFET Switch Number Selection PFET power switch count number. The selected number of switches are PFETCNT+1. This value applies to both LN and LP mode. Because of this, when transitioning from LN to LP mode, software may need to update the PFETCNT setting desired for LP mode while still in LN mode.
- Page 249 Reference Manual EMU - Energy Management Unit 11.5.19 EMU_DCDCCLIMCTRL - DCDC Power Train PFET Current Limiter Control Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions BYPLIMEN...
- Page 250 Reference Manual EMU - Energy Management Unit 11.5.20 EMU_DCDCLNCOMPCTRL - DCDC Low Noise Compensator Control Register Offset Bit Position 0x058 Reset Access Name Name Reset Access Description 31:28 COMPENC3 Low Noise Mode Compensator C3 Trim Value LN mode compensator C3 trim, 0.5pF-8pF in 0.5pF steps. Reset with POR, Hard Pin Reset, or BOD Reset. Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 251 Reference Manual EMU - Energy Management Unit 11.5.21 EMU_DCDCLNVCTRL - DCDC Low Noise Voltage Register Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 14:8...
- Page 252 Reference Manual EMU - Energy Management Unit 11.5.22 EMU_DCDCTIMING - DCDC Controller Timing Value Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 30:29...
- Page 253 Reference Manual EMU - Energy Management Unit 11.5.23 EMU_DCDCLPVCTRL - DCDC Low Power Voltage Register Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LPVREF...
- Page 254 Reference Manual EMU - Energy Management Unit 11.5.24 EMU_DCDCLPCTRL - DCDC Low Power Control Register Offset Bit Position 0x06C Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 26:25...
- Page 255 Reference Manual EMU - Energy Management Unit 11.5.25 EMU_DCDCLNFREQCTRL - DCDC Low Noise Controller Frequency Control Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 28:24...
- Page 256 Reference Manual EMU - Energy Management Unit 11.5.27 EMU_VMONAVDDCTRL - VMON AVDD Channel Control Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 23:20...
- Page 257 Reference Manual EMU - Energy Management Unit 11.5.28 EMU_VMONALTAVDDCTRL - Alternate VMON AVDD Channel Control Offset Bit Position 0x094 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:12...
- Page 258 Reference Manual EMU - Energy Management Unit 11.5.29 EMU_VMONDVDDCTRL - VMON DVDD Channel Control Offset Bit Position 0x098 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:12...
- Page 259 Reference Manual EMU - Energy Management Unit 11.5.30 EMU_VMONIO0CTRL - VMON IOVDD0 Channel Control Offset Bit Position 0x09C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:12...
- Page 260 Reference Manual EMU - Energy Management Unit 11.5.31 EMU_VMONPAVDDCTRL - VMON PAVDD Channel Control Offset Bit Position 0x0A8 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:12...
- Page 261 Reference Manual EMU - Energy Management Unit 11.5.32 EMU_BIASCONF - Configurations Related to the Bias Offset Bit Position 0x164 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LPEM23...
- Page 262 Reference Manual EMU - Energy Management Unit 11.5.33 EMU_TESTLOCK - Test Lock Register Offset Bit Position 0x190 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
- Page 263 Reference Manual EMU - Energy Management Unit 11.5.34 EMU_BIASTESTCTRL - Test Control Register for Regulator and BIAS Offset Bit Position 0x19C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions BIAS_RIP_RESET...
- Page 264 Reference Manual CMU - Clock Management Unit 12. CMU - Clock Management Unit Quick Facts What? The CMU controls oscillators and clocks. EFR32xG1 Wireless Gecko supports 6 different oscillators with minimized power consumption and short start-up time. The CMU has HW support for calibration of RC oscillators.
- Page 265 Reference Manual CMU - Clock Management Unit 12.3 Functional Description An overview of the high frequency portion of the CMU is shown in Figure 12.1 CMU Overview - High Frequency Portion on page 265. An overview of the low frequency portion is shown in Figure 12.2 CMU Overview - Low Frequency Portion on page 266.
- Page 266 Reference Manual CMU - Clock Management Unit HFBUSCLK CMU_HFBUSCLKEN0.LE Clock HFBUSCLK Gate HFCLKLE Prescaler ( /2, /4 ) CMU_HFPRESC.HFCLKLEPRESC CMU_LFACLKEN0.LETIMER0 LFACLK LETIMER0 Clock clock LFACLK Gate prescaler switch CMU_LFAPRESC0.LETIMER0 PCNTn_S0 CMU_LFACLKSEL.LFA PCNTnCLK CMU_PCNTCTRL.PCNTnCLKSEL LFXO Timeout CMU_LFBCLKSEL.LFB CMU_LFBPRESC0.LEUART0 LFBCLK CMU_LFBCLKEN0.LEUART0 LEUART0 Clock LFBCLK clock...
- Page 267 Reference Manual CMU - Clock Management Unit 12.3.1.2 HFCORECLK - High Frequency Core Clock HFCORECLK is a prescaled version of HFCLK. This clock drives the Core Modules, which consists of the CPU and modules that are tightly coupled to the CPU (e.g., the cache). The prescale factor for prescaling HFCLK into HFCORECLK is set using the CMU_HFCOREPRESC register.
- Page 268 Reference Manual CMU - Clock Management Unit 12.3.1.8 LFBCLK - Low Frequency B Clock LFBCLK is the selected clock for the Low Energy B Peripherals. There are several selectable sources for LFBCLK: LFRCO, LFXO, HFCLKLE and ULFRCO. In addition, the LFBCLK can be disabled, which is the default setting. The selection is configured using the LFB field in CMU_LFBCLKSEL.
- Page 269 Reference Manual CMU - Clock Management Unit 12.3.2.1 Enabling and Disabling The different oscillators can typically be enabled and disabled via both hardware and software mechanisms. Enabling via software is done by setting the corresponding enable bit in the CMU_OSCENCMD register. Disabling via software is done by setting the corre- sponding disable bit in CMU_OSCENCMD.
- Page 270 Reference Manual CMU - Clock Management Unit 12.3.2.1.1 LFRCO and LFXO The LFXO and LFRCO can be enabled and disabled by software via the CMU_OSCENCMD register. WDOGn can be configured to force the LFXO or LFRCO to become (and remain) enabled when such an oscillator is selected as its clock source via the CLKSEL bitfield in the WDOGn_CTRL register while SWOSCBLOCK is set.
- Page 271 Reference Manual CMU - Clock Management Unit CMU->OSCENCMD = CMU_OSCENCMD_LFRCOEN; while ((CMU->STATUS & CMU_STATUS_LFRCORDY) != CMU_STATUS_LFRCORDY); CMU->OSCENCMD = CMU_OSCENCMD_LFRCODIS; while ((CMU->STATUS & CMU_STATUS_LFRCORDY) == CMU_STATUS_LFRCORDY); When the LFXO is disabled, the interface to the LFXTAL_N and LFXTAL_P pins are set in a high-Z state. The XTAL oscillations will not stop immediately when LFXO is disabled, but typically die out gradually over some 100 ms.
- Page 272 Reference Manual CMU - Clock Management Unit 12.3.2.1.5 AUXHFRCO The AUXHFRCO can be enabled and disabled by software via the CMU_OSCENCMD register. The AUXHFRCO is disabled automati- cally when entering EM2, EM3, or EM4. Hardware based AUXHFRCO enabling and disabling is however performed by the ADC mod- ule when AUXCLK is selected for its operation making it available even when being in EM2/EM3.
- Page 273 Reference Manual CMU - Clock Management Unit 12.3.2.2 Oscillator Start-up Time and Time-out The start-up time differs per oscillator and the usage of an oscillator clock can further be delayed by a time-out. The LFRCO, LFXO and the HFXO have a configurable time-out which is set by software in the (various) TIMEOUT bitfields of the CMU_LFRCOCTRL, CMU_LFXOCTRL and CMU_HFXOTIMEOUTCTRL registers respectively.
- Page 274 Reference Manual CMU - Clock Management Unit 12.3.2.3 Switching Clock Source The HFRCO oscillator is a low energy oscillator with extremely short start-up time. Therefore, this oscillator is always chosen by hard- ware as the clock source for HFCLK when the device starts up (e.g., after reset and after waking up from EM2 DeepSleep and EM3 Stop).
- Page 275 Reference Manual CMU - Clock Management Unit HFXO CMU_CMD.HFCLKSEL CMU_OSCENCMD.HFRCOEN CMU_OSCENCMD.HFRCODIS CMU_OSCENCMD.HFXOEN CMU_OSCENCMD.HFXODIS CMU_STATUS.HFRCORDY CMU_STATUS.HFRCOENS CMU_STATUS.HFRCOSEL CMU_STATUS.HFXORDY CMU_STATUS.HFXOENS CMU_STATUS.HFXOSEL HFCLK HFRCO HFXO HFXO time-out period Figure 12.5. CMU Switching from HFRCO to HFXO after HFXO is ready Switching clock source for LFACLK, LFBCLK, and LFECLK is done by setting the LFA, LFB and LFE bitfields in CMU_LFACLKSEL, CMU_LFBCLKSEL and CMU_LFECLKSEL respectively.
- Page 276 Reference Manual CMU - Clock Management Unit 12.3.2.4 HFXO Configuration The High Frequency Crystal Oscillator needs to be configured to ensure safe startup for the given crystal. Refer to the device data sheet and application notes for guidelines in selecting correct components and crystals as well as for configuration trade-offs. The HFXO crystal is connected to the HFXTAL_N/HFXTAL_P pins as shown in Figure 12.6 HFXO Pin Connection on page 276 Gecko Device...
- Page 277 Reference Manual CMU - Clock Management Unit Reset || EM2/EM3 entry || (CMU->OSCENCMD = CMU_OSCENCMD_HFXODIS) HFXO major mode configuration from CMU->HFXOCTRL: · MODE · LOWPOWER CMU->OSCENCMD = CMU_OSCENCMD_HFXOEN Using Startup state configuration from CMU->HFXOSTARTUPCTRL: · IBTRIMXOCORE · CTUNE · REGISH STARTUP ·...
- Page 278 Reference Manual CMU - Clock Management Unit state configuration depending on the crystal's CL, RESR and oscillation frequency. This configuration is programmed into the IBTRIM- XOCORE, REGISH and CTUNE bitfields of the CMU_HFXOSTEADYSTATECTRL register. The minimum duration of the steady phase is configured in the STEADYTIMEOUT bitfield of the CMU_HFXOTIMEOUTCTRL register.
- Page 279 Reference Manual CMU - Clock Management Unit 12.3.2.4.1 Automatic HFXO Start The enabling of the HFXO and its selection as HFSRCCLK source can be performed automatically by hardware. Automatic HFXO ena- ble and select can for example be used upon wake-up of the Radio Controller (RAC). Automatic control of the HFXO is controlled via the AUTOSTARTRDYSELRAC, AUTOSTARTSELEM0EM1 and AUTOSTARTEM0EM1 bits in the CMU_HFXOCTRL register.
- Page 280 Reference Manual CMU - Clock Management Unit RAC wake-up with CMU_HFXOCTRL.AUTOSTARTRDYSELRAC = 1 EM0/EM1 entry with CMU_HFXOCTRL.AUTOSTARTSELEM0EM1 = 1 HFXO ready Automatic switch to HFXO (and disable of HFRCO) CMU_STATUS.HFRCORDY CMU_STATUS.HFRCOENS CMU_HFCLKSTATUS.HF = HFRCO CMU_STATUS.HFXORDY CMU_STATUS.HFXOENS CMU_HFCLKSTATUS.HF = HFXO HFCLK HFRCO HFXO Figure 12.8.
- Page 281 Reference Manual CMU - Clock Management Unit EM0/EM1 Entry && CMU_HFXOCTRL.AUTOSTARTSELEM0EM1 = 0 RAC wake-up with CMU_HFXOCTRL.AUTOSTARTRDYSELRAC = 1 HFXO ready Automatic switch to HFXO and disable of HFRCO HFRCO selected CMU_STATUS.HFRCORDY CMU_STATUS.HFRCOENS CMU_HFCLKSTATUS.HF = HFRCO CMU_STATUS.HFXORDY CMU_STATUS.HFXOENS CMU_HFCLKSTATUS.HF = HFXO HFCLK HFRCO HFXO...
- Page 282 Reference Manual CMU - Clock Management Unit 12.3.2.5 LFXO Configuration The Low Frequency Crystal Oscillator (LFXO) is default configured to ensure safe startup for all crystals. In order to optimize startup time and power consumption for a given crystal, it is possible to adjust the startup gain in the oscillator by programming the GAIN field in CMU_LFXOCTRL.
- Page 283 Reference Manual CMU - Clock Management Unit must then of course be reduced accordingly. Note that the ADC0 (24. ADC - Analog to Digital Converter) includes an embedded tem- perature sensor and that the EMU (11. EMU - Energy Management Unit) offers a temperature management interface, both of which can be used in combination with this LFXO temperature compensation scheme.
- Page 284 Reference Manual CMU - Clock Management Unit 12.3.2.8 RC Oscillator Calibration The CMU has built-in HW support to efficiently calibrate the RC oscillators (LFRCO, HFRCO, AUXHFRCO, etc) at run-time. For a com- plete list of supported oscillators, refer to DOWNSEL and UPSEL fields in CMU_CALCTRL. See Figure 12.13 HW-support for RC Oscillator Calibration on page 284 for an illustration of this circuit.
- Page 285 Reference Manual CMU - Clock Management Unit Up-counter sampled and CALRDY interrupt flag set. Sampled value available in CMU_CALCNT. Up-counter Down-counter Calibration Started Calibration Stopped (counters stopped) Figure 12.14. Single Calibration (CONT=0) Up-counter sampled and CALRDY Up-counter sampled and CALRDY interrupt flag set.
- Page 286 Reference Manual CMU - Clock Management Unit 12.3.3 Configuration for Operating Frequencies The HFXO is capable of frequencies up to 40 MHz, which allows the EFR32 to run at up to this frequency. However the Memory Sys- tem Controller (MSC) and the Low Energy Peripheral Interface need to be configured correctly to allow operation at higher frequencies as explained below.
- Page 287 Reference Manual CMU - Clock Management Unit 12.3.4 Energy Modes The availability of oscillators and system clocks depends on the chosen energy mode. Default the high frequency oscillators (HFRCO, AUXHFRCO, and HFXO) and high frequency clocks (HFSRCLK, HFCLK, HFCORECLK, HFBUSCLK, HFPERCLK, HFRADIOCLK, HFCLKLE) are available downto EM1 Sleep.
- Page 288 Reference Manual CMU - Clock Management Unit 12.3.5 Clock Output on a Pin It is possible to configure the CMU to output clocks on the CMU_CLK0 and CMU_CLK1 pins. This clock selection is done using the CLKOUTSEL0 and CLKOUTSEL1 fields, respectively, in CMU_CTRL. The required output pins must be enabled in the CMU_ROU- TEPEN register and the pin locations can be configured in the CMU_ROUTELOC0 register.
- Page 289 Reference Manual CMU - Clock Management Unit 12.3.10 Protection It is possible to lock the control- and command registers to prevent unintended software writes to critical clock settings. This is control- led by the CMU_LOCK register. silabs.com | Building a more connected world. Rev.
- Page 290 Reference Manual CMU - Clock Management Unit 12.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 CMU_CTRL CMU Control Register 0x010 CMU_HFRCOCTRL HFRCO Control Register 0x018 CMU_AUXHFRCOCTRL AUXHFRCO Control Register 0x020 CMU_LFRCOCTRL LFRCO Control Register...
- Page 291 Reference Manual CMU - Clock Management Unit Offset Name Type Description 0x110 CMU_HFRADIOPRESC High Frequency Radio Peripheral Clock Prescaler Register 0x114 CMU_HFEXPPRESC High Frequency Export Clock Prescaler Register 0x120 CMU_LFAPRESC0 Low Frequency a Prescaler Register 0 (Async Reg) 0x128 CMU_LFBPRESC0 Low Frequency B Prescaler Register 0 (Async Reg) 0x130 CMU_LFEPRESC0...
- Page 292 Reference Manual CMU - Clock Management Unit 12.5 Register Description 12.5.1 CMU_CTRL - CMU Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions HFRADIOCLKEN...
- Page 293 Reference Manual CMU - Clock Management Unit Name Reset Access Description HFXOQ HFXO (qualified) HFSRCCLK HFSRCCLK Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLKOUTSEL0 Clock Output Select 0 Controls the clock output multiplexer. To actually output on the pin, set CLKOUT0PEN in CMU_ROUTE. Value Mode Description...
- Page 294 Reference Manual CMU - Clock Management Unit 12.5.2 CMU_HFRCOCTRL - HFRCO Control Register Write this register to set the frequency band in which the HFRCO is to operate. Always update all fields in this register at once by writ- ing the value for the desired band, which has been obtained from the Device Information page entry for that band. The TUNING, FINE- TUNING, FINETUNINGEN and CLKDIV bitfields can be used to tune a specific band (FREQRANGE) of the oscillator to a non-precon- figured frequency.
- Page 295 Reference Manual CMU - Clock Management Unit even while the system is running on the HFRCO. Only write CMU_HFRCOCTRL when it is ready for an update as indicated by HFRCOBSY=0 in CMU_SYNCBUSY. Offset Bit Position 0x010 Reset Access Name Name Reset Access Description...
- Page 296 Reference Manual CMU - Clock Management Unit 12.5.3 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register Write this register with the production calibrated values from the Device Info pages. The TUNING, FINETUNING, FINETUNINGEN and CLKDIV bitfields can be used to tune a specific band (FREQRANGE) of the oscillator to a non-preconfigured frequency. Only write CMU_AUXHFRCOCTRL when it is ready for an update as indicated by AUXHFRCOBSY=0 in CMU_SYNCBUSY.
- Page 297 Reference Manual CMU - Clock Management Unit 12.5.4 CMU_LFRCOCTRL - LFRCO Control Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:28 GMCCURTUNE Tuning of Gmc Current Set to tune GMC current. This field is updated with the production calibrated value during reset, and the reset value might therefore vary between devices.
- Page 298 Reference Manual CMU - Clock Management Unit 12.5.5 CMU_HFXOCTRL - HFXO Control Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions AUTOSTARTRDY- Automatically Start HFXO on RAC Wake-up and Select It Upon...
- Page 299 Reference Manual CMU - Clock Management Unit Name Reset Access Description 23:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions XTO2GND Clamp HFXTAL_P Pin to Ground When HFXO Oscillator is Off Set to enable grounding of HFXTAL_P pin when HFXO oscillator is off XTI2GND Clamp HFXTAL_N Pin to Ground When HFXO Oscillator is Off...
- Page 300 Reference Manual CMU - Clock Management Unit 12.5.6 CMU_HFXOCTRL1 - HFXO Control 1 Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions XTIBIASEN...
- Page 301 Reference Manual CMU - Clock Management Unit 12.5.7 CMU_HFXOSTARTUPCTRL - HFXO Startup Control Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:28 RESERVED1 Sets the Regulator Output Current Level (shunt Regulator) This REGISH value is applied during the keep warm phase of the HFXO. Ish=120uA+reg_ish X 120uA. 27:21 RESERVED0 0x09...
- Page 302 Reference Manual CMU - Clock Management Unit 12.5.8 CMU_HFXOSTEADYSTATECTRL - HFXO Steady State Control Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:28 REGISHUPPER Set Regulator Output Current Level (shunt Regulator). Ish = 120uA + REGISHUPPER X 120uA Set to steady state value of REGISH + 3.
- Page 303 Reference Manual CMU - Clock Management Unit 12.5.9 CMU_HFXOTIMEOUTCTRL - HFXO Timeout Control Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 19:16...
- Page 304 Reference Manual CMU - Clock Management Unit Name Reset Access Description 1KCYCLES Timeout period of 1024 cycles 2KCYCLES Timeout period of 2048 cycles 4KCYCLES Timeout period of 4096 cycles 8KCYCLES Timeout period of 8192 cycles 16KCYCLES Timeout period of 16384 cycles 32KCYCLES Timeout period of 32768 cycles 11:8...
- Page 305 Reference Manual CMU - Clock Management Unit Name Reset Access Description 16KCYCLES Timeout period of 16384 cycles 32KCYCLES Timeout period of 32768 cycles silabs.com | Building a more connected world. Rev. 1.3 | 305...
- Page 306 Reference Manual CMU - Clock Management Unit 12.5.10 CMU_LFXOCTRL - LFXO Control Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 26:24...
- Page 307 Reference Manual CMU - Clock Management Unit Name Reset Access Description 12:11 GAIN LFXO Startup Gain The optimal value for maximum startup margin depends on the chosen XTAL. Refer to the device data sheet or Simplicity Studio for more information. Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 308 Reference Manual CMU - Clock Management Unit 12.5.11 CMU_ULFRCOCTRL - ULFRCO Control Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 17:16...
- Page 309 Reference Manual CMU - Clock Management Unit 12.5.12 CMU_CALCTRL - Calibration Control Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 27:24...
- Page 310 Reference Manual CMU - Clock Management Unit Name Reset Access Description PRSCH5 PRS Channel 5 selected as input PRSCH6 PRS Channel 6 selected as input PRSCH7 PRS Channel 7 selected as input PRSCH8 PRS Channel 8 selected as input PRSCH9 PRS Channel 9 selected as input PRSCH10 PRS Channel 10 selected as input...
- Page 311 Reference Manual CMU - Clock Management Unit 12.5.13 CMU_CALCNT - Calibration Counter Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 19:0...
- Page 312 Reference Manual CMU - Clock Management Unit 12.5.14 CMU_OSCENCMD - Oscillator Enable/Disable Command Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LFXODIS...
- Page 313 Reference Manual CMU - Clock Management Unit 12.5.15 CMU_CMD - Command Register Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions HFXOSHUNTOPT- HFXO Shunt Current Optimization Start...
- Page 314 Reference Manual CMU - Clock Management Unit 12.5.16 CMU_DBGCLKSEL - Debug Trace Clock Select Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions Debug Trace Clock...
- Page 315 Reference Manual CMU - Clock Management Unit 12.5.18 CMU_LFACLKSEL - Low Frequency A Clock Select Register Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions Clock Select for LFA...
- Page 316 Reference Manual CMU - Clock Management Unit 12.5.20 CMU_LFECLKSEL - Low Frequency E Clock Select Register Offset Bit Position 0x088 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions Clock Select for LFE...
- Page 317 Reference Manual CMU - Clock Management Unit 12.5.21 CMU_STATUS - Status Register Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions HFXOREGILOW HFXO Regulator Shunt Current Too Low...
- Page 318 Reference Manual CMU - Clock Management Unit Name Reset Access Description LFRCORDY LFRCO Ready LFRCO is enabled and start-up time has exceeded. LFRCOENS LFRCO Enable Status LFRCO is enabled (shows disabled status if EM4 repaint is required). AUXHFRCORDY AUXHFRCO Ready AUXHFRCO is enabled and start-up time has exceeded.
- Page 319 Reference Manual CMU - Clock Management Unit 12.5.23 CMU_HFXOTRIMSTATUS - HFXO Trim Status Offset Bit Position 0x09C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 10:7...
- Page 320 Reference Manual CMU - Clock Management Unit 12.5.24 CMU_IF - Interrupt Flag Register Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description CMUERR CMU Error Interrupt Flag Set upon illegal CMU write attempt (e.g. writing CMU_LFRCOCTRL while LFRCOBSY is set). 30:15 Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 321 Reference Manual CMU - Clock Management Unit Name Reset Access Description AUXHFRCORDY AUXHFRCO Ready Interrupt Flag Set when AUXHFRCO is ready (start-up time exceeded). LFXORDY LFXO Ready Interrupt Flag Set when LFXO is ready (start-up time exceeded). LFXORDY can be used as wake-up interrupt. LFRCORDY LFRCO Ready Interrupt Flag Set when LFRCO is ready (start-up time exceeded).
- Page 322 Reference Manual CMU - Clock Management Unit 12.5.25 CMU_IFS - Interrupt Flag Set Register Offset Bit Position 0x0A4 Reset Access Name Name Reset Access Description CMUERR Set CMUERR Interrupt Flag Write 1 to set the CMUERR interrupt flag 30:15 Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 323 Reference Manual CMU - Clock Management Unit Name Reset Access Description LFXORDY Set LFXORDY Interrupt Flag Write 1 to set the LFXORDY interrupt flag LFRCORDY Set LFRCORDY Interrupt Flag Write 1 to set the LFRCORDY interrupt flag HFXORDY Set HFXORDY Interrupt Flag Write 1 to set the HFXORDY interrupt flag HFRCORDY Set HFRCORDY Interrupt Flag...
- Page 324 Reference Manual CMU - Clock Management Unit 12.5.26 CMU_IFC - Interrupt Flag Clear Register Offset Bit Position 0x0A8 Reset Access Name Name Reset Access Description CMUERR (R)W1 Clear CMUERR Interrupt Flag Write 1 to clear the CMUERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
- Page 325 Reference Manual CMU - Clock Management Unit Name Reset Access Description CALOF (R)W1 Clear CALOF Interrupt Flag Write 1 to clear the CALOF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.). CALRDY (R)W1 Clear CALRDY Interrupt Flag...
- Page 326 Reference Manual CMU - Clock Management Unit 12.5.27 CMU_IEN - Interrupt Enable Register Offset Bit Position 0x0AC Reset Access Name Name Reset Access Description CMUERR CMUERR Interrupt Enable Enable/disable the CMUERR interrupt 30:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LFTIMEOUTERR...
- Page 327 Reference Manual CMU - Clock Management Unit Name Reset Access Description LFXORDY LFXORDY Interrupt Enable Enable/disable the LFXORDY interrupt LFRCORDY LFRCORDY Interrupt Enable Enable/disable the LFRCORDY interrupt HFXORDY HFXORDY Interrupt Enable Enable/disable the HFXORDY interrupt HFRCORDY HFRCORDY Interrupt Enable Enable/disable the HFRCORDY interrupt 12.5.28 CMU_HFBUSCLKEN0 - High Frequency Bus Clock Enable Register 0 Offset Bit Position...
- Page 328 Reference Manual CMU - Clock Management Unit 12.5.29 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0 Offset Bit Position 0x0C0 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions IDAC0...
- Page 329 Reference Manual CMU - Clock Management Unit 12.5.30 CMU_LFACLKEN0 - Low Frequency a Clock Enable Register 0 (Async Reg) Offset Bit Position 0x0E0 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LETIMER0...
- Page 330 Reference Manual CMU - Clock Management Unit 12.5.32 CMU_LFECLKEN0 - Low Frequency E Clock Enable Register 0 (Async Reg) Offset Bit Position 0x0F0 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RTCC...
- Page 331 Reference Manual CMU - Clock Management Unit 12.5.33 CMU_HFPRESC - High Frequency Clock Prescaler Register Offset Bit Position 0x100 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 24:24...
- Page 332 Reference Manual CMU - Clock Management Unit 12.5.34 CMU_HFCOREPRESC - High Frequency Core Clock Prescaler Register Offset Bit Position 0x108 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 16:8...
- Page 333 Reference Manual CMU - Clock Management Unit 12.5.36 CMU_HFRADIOPRESC - High Frequency Radio Peripheral Clock Prescaler Register Offset Bit Position 0x110 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 16:8...
- Page 334 Reference Manual CMU - Clock Management Unit 12.5.38 CMU_LFAPRESC0 - Low Frequency a Prescaler Register 0 (Async Reg) Offset Bit Position 0x120 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LETIMER0...
- Page 335 Reference Manual CMU - Clock Management Unit 12.5.39 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg) Offset Bit Position 0x128 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LEUART0...
- Page 336 Reference Manual CMU - Clock Management Unit 12.5.41 CMU_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x140 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LFXOBSY...
- Page 337 Reference Manual CMU - Clock Management Unit Name Reset Access Description CMU_LFRCOCTRL is busy synchronizing new value AUXHFRCOBSY AUXHFRCO Busy Used to check the synchronization status of CMU_AUXHFRCOCTRL. Value Description CMU_AUXHFRCOCTRL is ready for update CMU_AUXHFRCOCTRL is busy synchronizing new value HFRCOBSY HFRCO Busy Used to check the synchronization status of CMU_HFRCOCTRL.
- Page 338 Reference Manual CMU - Clock Management Unit Name Reset Access Description LFBCLKEN0 Low Frequency B Clock Enable 0 Busy Used to check the synchronization status of CMU_LFBCLKEN0. Value Description CMU_LFBCLKEN0 is ready for update CMU_LFBCLKEN0 is busy synchronizing new value Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 339 Reference Manual CMU - Clock Management Unit 12.5.42 CMU_FREEZE - Freeze Register Offset Bit Position 0x144 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions REGFREEZE Register Update Freeze...
- Page 340 Reference Manual CMU - Clock Management Unit 12.5.43 CMU_PCNTCTRL - PCNT Control Register Offset Bit Position 0x150 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PCNT0CLKSEL...
- Page 341 Reference Manual CMU - Clock Management Unit 12.5.44 CMU_ADCCTRL - ADC Control Register Offset Bit Position 0x15C Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ADC0CLKINV...
- Page 342 Reference Manual CMU - Clock Management Unit 12.5.45 CMU_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x170 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLKOUT1PEN...
- Page 343 Reference Manual CMU - Clock Management Unit 12.5.46 CMU_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x174 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
- Page 344 Reference Manual CMU - Clock Management Unit 12.5.47 CMU_LOCK - Configuration Lock Register Offset Bit Position 0x180 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
- Page 345 Reference Manual RTCC - Real Time Counter and Calendar 13. RTCC - Real Time Counter and Calendar Quick Facts What? The Real Time Counter and Calendar (RTCC) is a 32-bit counter ensuring timekeeping in low energy 2 3 4 modes. The RTCC also includes a calendar mode for easy time and date keeping.
- Page 346 Reference Manual RTCC - Real Time Counter and Calendar 13.3 Functional Description The RTCC is a 32-bit up-counter with three Capture/Compare channels. In addition, the RTCC includes a 15-bit pre-counter which can be used as an independent counter or to prescale the main counter. An overview of the RTCC module is shown in Figure 13.1 RTCC Overview on page 346.
- Page 347 Reference Manual RTCC - Real Time Counter and Calendar 13.3.1 Counter The RTCC consists of two counters; the 32-bit main counter, RTCC_CNT (RTCC_TIME and RTCC_DATE in calendar mode), and a 15-bit pre-counter, RTCC_PRECNT. The pre-counter can be used as an independent counter or to generate a specific frequency for the main counter.
- Page 348 Reference Manual RTCC - Real Time Counter and Calendar 13.3.1.1 Normal Mode The main counter can receive a tick based on different tappings from the pre-counter, allowing the ticks to be power of 2 divisions of the LFCLK . For more accurate configuration of the tick frequency, RTCC_CC0_CCV[14:0] can be used as a top value for RTCC RTCC_PRECNT.
- Page 349 Reference Manual RTCC - Real Time Counter and Calendar 13.3.1.2 Calendar Mode The RTCC includes a calendar mode which implements time and date decoding in hardware. Calendar mode is enabled by configuring CNTMODE in RTCC_CTRL to CALENDAR. When in calendar mode, the counter value is available in RTCC_TIME and RTCC_DATE. RTCC_TIME shows seconds, minutes, and hours while RTCC_DATE shows day of month, month, year, and day of week.
- Page 350 Reference Manual RTCC - Real Time Counter and Calendar 13.3.1.3 RTCC Initialization The counters of the RTCC, RTCC_CNT (RTCC_TIME and RTCC_DATE in calendar mode) and RTCC_PRECNT, can at any time be written by software, as long as the registers are not locked using RTCC_LOCKKEY. All RTCC registers use the immediate synchroni- zation scheme, described in 4.3.1 Writing.
- Page 351 Reference Manual RTCC - Real Time Counter and Calendar 13.3.2 Capture/Compare Channels Three capture/compare channels are available in the RTCC. Each channel can be configured as input capture or output compare, by setting the corresponding MODE in the RTCC_CCx_CTRL register. RTCC_CNT RTCC_CC0_CCV RTCC_CC1_CCV...
- Page 352 Reference Manual RTCC - Real Time Counter and Calendar RTCC_CCx_CTRL_COMPBASE = CNT PRECNT MASK Compare match MASK CCx_CCV RTCC_CCx_CTRL_COMPBASE = PRECNT 0 14 PRECNT MASK Compare match MASK CCx_CCV Figure 13.4. RTCC Compare base illustration Table 13.3 RTCC Capture/Compare Subjects on page 352 summarizes which registers being subject to comparison for different con- figurations of RTCC_CTRL_CNTMODE and RTCC_CCx_CTRL_COMPBASE.
- Page 353 Reference Manual RTCC - Real Time Counter and Calendar RTCC_DATE RTCC_TIME [0b000, [DAYOMT, DAYOW] DAYOMU] RTCC_CCx_CTRL_DAYCC [MONTHT,MONTHU] MASK Compare match MASK [MONTHT,MONTHU] [DAYT,DAYU] RTCC_CCx_DATE RTCC_CCx_TIME Figure 13.5. RTCC Compare in calendar mode, COMPBASE = CNT To generate periodically recurring events, it is possible to mask out parts of the compare match values. By configuring COMPMASK in RTCC_CCx_CTRL, parts of the compare values will be masked out, limiting which part of the compare register being subject to com- parison with the counter.
- Page 354 Reference Manual RTCC - Real Time Counter and Calendar 13.3.3.1 Main Counter Tick PRS Output To output the ticks for the main counter on PRS, it is possible to use a Capture/Compare channel and mask all the bits, i.e. RTCC_CCx_CTRL_COMPBASE=CNT and RTCC_CCx_CTRL_COMPMASK=31. PRS output of main counter ticks does not work if the main counter is not prescaled.
- Page 355 Reference Manual RTCC - Real Time Counter and Calendar 13.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 RTCC_CTRL Control Register 0x004 RTCC_PRECNT Pre-Counter Value Register 0x008 RTCC_CNT Counter Value Register 0x00C RTCC_COMBCNT Combined Pre-Counter and Counter Value Register...
- Page 356 Reference Manual RTCC - Real Time Counter and Calendar 13.5 Register Description 13.5.1 RTCC_CTRL - Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name Name Reset...
- Page 357 Reference Manual RTCC - Real Time Counter and Calendar Name Reset Access Description DIV4 = LFECLK RTCC DIV8 = LFECLK RTCC DIV16 = LFECLK RTCC DIV32 = LFECLK RTCC DIV64 = LFECLK RTCC DIV128 = LFECLK /128 RTCC DIV256 = LFECLK /256 RTCC DIV512...
- Page 358 Reference Manual RTCC - Real Time Counter and Calendar 13.5.2 RTCC_PRECNT - Pre-Counter Value Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x004 Reset Access Name Name Reset Access Description...
- Page 359 Reference Manual RTCC - Real Time Counter and Calendar 13.5.4 RTCC_COMBCNT - Combined Pre-Counter and Counter Value Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:15 CNTLSB 0x00000 Counter Value Gives access to the 17 LSBs of the main counter, CNT. Register will be read as zero when RTCC_CTRL_CNTMODE = CALENDAR.
- Page 360 Reference Manual RTCC - Real Time Counter and Calendar 13.5.5 RTCC_TIME - Time of Day Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x010 Reset Access Name Name Reset Access...
- Page 361 Reference Manual RTCC - Real Time Counter and Calendar 13.5.6 RTCC_DATE - Date Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:27...
- Page 362 Reference Manual RTCC - Real Time Counter and Calendar 13.5.7 RTCC_IF - RTCC Interrupt Flags Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions MONTHTICK...
- Page 363 Reference Manual RTCC - Real Time Counter and Calendar 13.5.8 RTCC_IFS - Interrupt Flag Set Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions MONTHTICK...
- Page 364 Reference Manual RTCC - Real Time Counter and Calendar 13.5.9 RTCC_IFC - Interrupt Flag Clear Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions MONTHTICK...
- Page 365 Reference Manual RTCC - Real Time Counter and Calendar Name Reset Access Description (R)W1 Clear OF Interrupt Flag Write 1 to clear the OF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
- Page 366 Reference Manual RTCC - Real Time Counter and Calendar 13.5.11 RTCC_STATUS - Status Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:0 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13.5.12 RTCC_CMD - Command Register (Async Reg)
- Page 367 Reference Manual RTCC - Real Time Counter and Calendar 13.5.13 RTCC_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CMD Register Busy...
- Page 368 Reference Manual RTCC - Real Time Counter and Calendar 13.5.15 RTCC_LOCK - Configuration Lock Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x038 Reset Access Name Name Reset Access Description...
- Page 369 Reference Manual RTCC - Real Time Counter and Calendar 13.5.17 RTCC_CCx_CTRL - CC Channel Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x040 Reset Access Name Name Reset Access...
- Page 370 Reference Manual RTCC - Real Time Counter and Calendar Name Reset Access Description PRSCH6 PRS Channel 6 selected as input PRSCH7 PRS Channel 7 selected as input PRSCH8 PRS Channel 8 selected as input PRSCH9 PRS Channel 9 selected as input PRSCH10 PRS Channel 10 selected as input PRSCH11...
- Page 371 Reference Manual RTCC - Real Time Counter and Calendar 13.5.18 RTCC_CCx_CCV - Capture/Compare Value Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x044 Reset Access Name Name Reset Access Description...
- Page 372 Reference Manual RTCC - Real Time Counter and Calendar 13.5.19 RTCC_CCx_TIME - Capture/Compare Time Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x048 Reset Access Name Name Reset Access Description...
- Page 373 Reference Manual RTCC - Real Time Counter and Calendar 13.5.20 RTCC_CCx_DATE - Capture/Compare Date Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x04C Reset Access Name Name Reset Access Description...
- Page 374 Reference Manual WDOG - Watchdog Timer 14. WDOG - Watchdog Timer Quick Facts What? The Watchdog Timer (WDOG) resets the system in case of a fault condition, and can be enabled in all energy modes as long as the low frequency clock source is available.
- Page 375 Reference Manual WDOG - Watchdog Timer 14.3.1 Clock Source Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOGn_CTRL. The corresponding clocks must be enabled in the CMU. The SWOSCBLOCK bit in WDOGn_CTRL can be written to prevent accidental disabling of the selected clocks.
- Page 376 Reference Manual WDOG - Watchdog Timer 14.3.6 Window Interrupt This interrupt occurs when the watchdog is cleared below a certain threshold. This threshold is given by the formula: 3+PERSEL = ( (2 ) * (WINSEL/8) + 1)/f, WARNING where f is the frequency of the selected clock. This value will be approximately 12.5%, 25%, 37.5%, 50%, 62.5%, 75%, or 87.5% of the timeout value based on the WINSEL field of the WDOGn_CTRL.
- Page 377 Reference Manual WDOG - Watchdog Timer 14.3.7 PRS as Watchdog Clear The first PRS channel (selected by register WDOGn_PCH0_PRSCTRL) can be used to clear the watchdog counter. To enable this feature, CLRSRC must be set to 1. Figure 14.2 PRS Clearing WDOG on page 377 shows how the PRS channel takes over the WDOG clear function.
- Page 378 Reference Manual WDOG - Watchdog Timer 14.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 WDOG_CTRL Control Register 0x004 WDOG_CMD Command Register 0x008 WDOG_SYNCBUSY Synchronization Busy Register 0x00C WDOGn_PCH0_PRSCTRL PRS Control Register 0x010 WDOGn_PCH1_PRSCTRL PRS Control Register...
- Page 379 Reference Manual WDOG - Watchdog Timer 14.5 Register Description 14.5.1 WDOG_CTRL - Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name Name Reset Access Description WDOGRSTDIS...
- Page 380 Reference Manual WDOG - Watchdog Timer Name Reset Access Description 23:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 17:16 WARNSEL Watchdog Timeout Period Select Select watchdog warning timeout period. Value Description Disabled.
- Page 381 Reference Manual WDOG - Watchdog Timer Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SWOSCBLOCK Software Oscillator Disable Block Set to disallow disabling of the selected WDOG oscillator. Writing this bit to 1 will turn on the selected WDOG oscillator if it is not already running.
- Page 382 Reference Manual WDOG - Watchdog Timer Name Reset Access Description Watchdog Timer Enable Set to enabled watchdog timer. 14.5.2 WDOG_CMD - Command Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x004...
- Page 383 Reference Manual WDOG - Watchdog Timer 14.5.3 WDOG_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PCH1_PRSCTRL PCH1_PRSCTRL Register Busy...
- Page 384 Reference Manual WDOG - Watchdog Timer 14.5.4 WDOGn_PCHx_PRSCTRL - PRS Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 385 Reference Manual WDOG - Watchdog Timer 14.5.5 WDOG_IF - Watchdog Interrupt Flags Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PEM1 PRS Channel One Event Missing Interrupt Flag...
- Page 386 Reference Manual WDOG - Watchdog Timer 14.5.6 WDOG_IFS - Interrupt Flag Set Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PEM1...
- Page 387 Reference Manual WDOG - Watchdog Timer 14.5.7 WDOG_IFC - Interrupt Flag Clear Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PEM1...
- Page 388 Reference Manual WDOG - Watchdog Timer 14.5.8 WDOG_IEN - Interrupt Enable Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PEM1 PEM1 Interrupt Enable...
- Page 389 Reference Manual PRS - Peripheral Reflex System 15. PRS - Peripheral Reflex System Quick Facts What? The Peripheral Reflex System (PRS) allows configu- rable, fast, and autonomous communication be- tween peripherals. Why? Events and signals from one peripheral can be used as input signals or triggered by other peripherals.
- Page 390 Reference Manual PRS - Peripheral Reflex System 15.3 Functional Description An overview of the PRS module is shown in Figure 15.1 PRS Overview on page 390. The PRS contains 12 Reflex channels. All chan- nels can select any Reflex signal offered by the producers. The consumers can choose which PRS channel to listen to and perform actions based on the Reflex signals routed through that channel.
- Page 391 Reference Manual PRS - Peripheral Reflex System 15.3.1.2 Edge Detection and Clock Domains Using EDSEL in PRS_CHx_CTRL, edge detection can be applied to a PRS signal. When edge detection is enabled, changes in the PRS input will result in a pulse on the PRS channel. This requires that the ASYNC bit in PRS_CHx_CTRL is cleared. Signals on the PRS input must be at least one HFCLK period wide in order to be detected properly.
- Page 392 Reference Manual PRS - Peripheral Reflex System 15.3.3 Consumers Consumer peripherals (Listed in Table 15.1 Reflex Consumers on page 392) can be set to listen to a PRS channel and perform an action based on the signal received on that channel. While most consumers can handle either only pulse input or only level input, some can handle both pulse and level inputs.
- Page 393 Reference Manual PRS - Peripheral Reflex System 15.3.4 Event on PRS The PRS can be used to send events to the MCU. This is very useful in combination with the Wait For Event (WFE) instruction. A single PRS channel can be selected for this using SEVONPRSSEL in PRS_CTRL, and the feature is enabled by setting SEVONPRS in the same register.
- Page 394 Reference Manual PRS - Peripheral Reflex System 15.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PRS_SWPULSE Software Pulse Register 0x004 PRS_SWLEVEL Software Level Register 0x008 PRS_ROUTEPEN I/O Routing Pin Enable Register 0x010 PRS_ROUTELOC0 I/O Routing Location Register...
- Page 395 Reference Manual PRS - Peripheral Reflex System 15.5 Register Description 15.5.1 PRS_SWPULSE - Software Pulse Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CH11PULSE...
- Page 396 Reference Manual PRS - Peripheral Reflex System 15.5.2 PRS_SWLEVEL - Software Level Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CH11LEVEL...
- Page 397 Reference Manual PRS - Peripheral Reflex System 15.5.3 PRS_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CH11PEN...
- Page 398 Reference Manual PRS - Peripheral Reflex System 15.5.4 PRS_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24...
- Page 399 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description LOC3 Location 3 LOC4 Location 4 LOC5 Location 5 LOC6 Location 6 LOC7 Location 7 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
- Page 400 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description silabs.com | Building a more connected world. Rev. 1.3 | 400...
- Page 401 Reference Manual PRS - Peripheral Reflex System 15.5.5 PRS_ROUTELOC1 - I/O Routing Location Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24...
- Page 402 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description LOC7 Location 7 LOC8 Location 8 LOC9 Location 9 LOC10 Location 10 LOC11 Location 11 LOC12 Location 12 LOC13 Location 13 LOC14 Location 14 LOC15 Location 15 LOC16 Location 16 LOC17 Location 17 15:14...
- Page 403 Reference Manual PRS - Peripheral Reflex System 15.5.6 PRS_ROUTELOC2 - I/O Routing Location Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24...
- Page 404 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description LOC1 Location 1 LOC2 Location 2 LOC3 Location 3 LOC4 Location 4 LOC5 Location 5 LOC6 Location 6 LOC7 Location 7 LOC8 Location 8 LOC9 Location 9 LOC10 Location 10 LOC11 Location 11 LOC12...
- Page 405 Reference Manual PRS - Peripheral Reflex System 15.5.7 PRS_CTRL - Control Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SEVONPRSSEL SEVONPRS PRS Channel Select...
- Page 406 Reference Manual PRS - Peripheral Reflex System 15.5.8 PRS_DMAREQ0 - DMA Request 0 Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PRSSEL...
- Page 407 Reference Manual PRS - Peripheral Reflex System 15.5.9 PRS_DMAREQ1 - DMA Request 1 Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PRSSEL...
- Page 408 Reference Manual PRS - Peripheral Reflex System 15.5.10 PRS_PEEK - PRS Channel Values Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CH11VAL...
- Page 409 Reference Manual PRS - Peripheral Reflex System 15.5.11 PRS_CHx_CTRL - Channel Control Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ASYNC Asynchronous Reflex...
- Page 410 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description 14:8 SOURCESEL 0x00 Source Select Select input source to PRS channel. Value Mode Description 0b0000000 NONE No source selected 0b0000001 PRSL Peripheral Reflex System 0b0000010 PRSH Peripheral Reflex System 0b0000110 ACMP0 Analog Comparator 0...
- Page 411 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description 0b111 PRSCH7 PRS channel 7 PRSCH7 (Asynchronous) SOURCESEL = 0b0000010 (PRSH) 0b000 PRSCH8 PRS channel 8 PRSCH8 (Asynchronous) 0b001 PRSCH9 PRS channel 9 PRSCH9 (Asynchronous) 0b010 PRSCH10 PRS channel 10 PRSCH10 (Asynchronous) 0b011 PRSCH11 PRS channel 11 PRSCH11 (Asynchronous)
- Page 412 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description 0b100 TIMER1CC2 Timer 1 Compare/Capture 2 TIMER1CC2 0b101 TIMER1CC3 Timer 1 Compare/Capture 3 TIMER1CC3 SOURCESEL = 0b0101001 (RTCC) 0b001 RTCCCCV0 RTCC Compare 0 RTCCCCV0 (Asynchronous) 0b010 RTCCCCV1 RTCC Compare 1 RTCCCCV1 (Asynchronous) 0b011 RTCCCCV2 RTCC Compare 2 RTCCCCV2 (Asynchronous)
- Page 413 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description 0b000 CM4TXEV CM4TXEV silabs.com | Building a more connected world. Rev. 1.3 | 413...
- Page 414 Reference Manual PCNT - Pulse Counter 16. PCNT - Pulse Counter Quick Facts What? The Pulse Counter (PCNT) decodes incoming pul- ses. The module has a quadrature mode which may be used to decode the speed and direction of a me- chanical shaft.
- Page 415 Reference Manual PCNT - Pulse Counter 16.3 Functional Description An overview of the PCNT module is shown in Figure 16.1 PCNT Overview on page 415. CMU (conceptual) LFACLK Clock Triggered compare PCNTnCLK switch and clear control TCCMODE != DISABLED PCNT S0PRS Input OVR_SINGLE Edge...
- Page 416 Reference Manual PCNT - Pulse Counter 16.3.1.3 Quadrature Decoder Modes Two different types of quadrature decoding is supported in the pulse counter: the externally clocked (Asynchronous) quadrature decod- ing and the oversampling (Synchronous) quadrature decoding. The externally clocked mode supports 1X quadrature decoding whereas the oversampling mode supports 1X, 2X and 4X quadrature decoding.
- Page 417 Reference Manual PCNT - Pulse Counter 16.3.1.4 Externally Clocked Quadrature Decoder Mode This mode is enabled by writing EXTCLKQUAD to the MODE field in PCNTn_CTRL and disabled by writing DISABLE to the same field. The external pin clock source is configured by setting PCNT0CLKSEL in the CMU_PCNTCTRL register (12.
- Page 418 Reference Manual PCNT - Pulse Counter Inputs Control/Status S1IN posedge S1IN negedge Count Enable CNTDIR status bit Note: PCNTn_S1IN is sampled on both edges of PCNTn_S0IN. silabs.com | Building a more connected world. Rev. 1.3 | 418...
- Page 419 Reference Manual PCNT - Pulse Counter 16.3.1.5 Oversampling Quadrature Decoder Mode There are three Oversampling Quadrature Decoder Modes supported: 1X , 2X and 4X. These modes are enabled by writing OVS- QUAD1X, OVSQUAD2X and OVSQUAD4X, respectively, to the MODE field in PCNTn_CTRL and disabled by writing DISABLE to the same field.
- Page 420 Reference Manual PCNT - Pulse Counter Relationship between inputs and its state STATE S1IN S0IN ‘b00 ‘b00 ‘b00 ‘b10 ‘b10 ‘b10 ‘b01 ‘b01 ‘b01 ‘b11 ‘b11 ‘b11 OVSQUAD2X mode OVSQUAD4X mode OVSQUAD1X mode Transitions between States All state transitions updates the Transitions between States and between counter...
- Page 421 Reference Manual PCNT - Pulse Counter Period > 125 us S0IN S1IN Figure 16.5. PCNT Oversampling Quadrature Decoder 2X Mode Period > 125 us S0IN S1IN Figure 16.6. PCNT Oversampling Quadrature Decoder 4X Mode The above modes, by default are prone to flutter effects in the inputs PCNTn_S0IN and PCNTn_S1IN. When this occurs, the counter changes directions rapidly causing DIRCNG interrupts and unnecessarily waking the core.
- Page 422 Reference Manual PCNT - Pulse Counter 16.3.2 Hysteresis By default the pulse counter wraps to 0 when passing the configured top value, and wraps to the top value when counting down from 0. On these events, a system will likely want to wake up to store and track the overflow count. This is fine if the pulse counter is tracking a monotonic value or a value that does not change directions frequently.
- Page 423 Reference Manual PCNT - Pulse Counter 16.3.3 Auxiliary Counter To be able to keep explicit track of counting in one direction in addition to the regular counter which counts both up and down, the auxiliary counter can be used. The pulse counter can, for instance, be configured to keep track of the absolute rotation of the wheel, while at the same time the auxiliary counter can keep track of how much the wheel has reversed.
- Page 424 Reference Manual PCNT - Pulse Counter 16.3.4 Triggered Compare and Clear The pulse counter features triggered compare and clear. When enabled, a configurable trigger will induce a comparison between the main counter, PCNTn_CNT, and the top value, PCNTn_TOP. After the comparison, the counter is cleared. The trigger for a compare and clear event is configured in the TCCMODE bit-field in PCNTn_CTRL.
- Page 425 Reference Manual PCNT - Pulse Counter 16.3.5 Register Access The counter-clock domain may be clocked externally. To update the counter-clock domain registers from software in this mode, 2-3 clock pulses on the external clock are needed to synchronize accesses to the externally clocked domain. Clock source switching is controlled from the registers in the CMU (12.
- Page 426 Reference Manual PCNT - Pulse Counter 16.3.9 PRS and PCNTn_S0IN,PCNTn_S1IN Inputs It is possible to receive input from PRS on both PCNTn_S0IN (or PCNTn_S1IN) by setting S0PRSEN (or S1PRSEN) in PCNTn_IN- PUT. The PRS channel used can be selected using S0PRSSEL (or S1PRSSEL) in PCNTn_INPUT. In the Oversampling quadrature decoder modes, the input frequency should be less than 8KHz to ensure correct functionality.
- Page 427 Reference Manual PCNT - Pulse Counter 16.3.10.2 Direction Change Interrupt The PCNTn_PCNT module sets the DIRCNG interrupt flag (PCNTn_IF register) for EXTCLKQUAD and OVSQUAD1X-4X modes when the direction of the quadrature code changes. The behavior of this interrupt in the EXTCLKQUAD mode is illustrated by Figure 16.13 PCNT Direction Change Interrupt (DIRCNG) Generation on page 427.
- Page 428 Reference Manual PCNT - Pulse Counter 16.3.11 Cascading Pulse Counters When two or more Pulse Counters are available, it is possible to cascade them. For example two 16-bit Pulse Counters can be casca- ded to form a 32-bit pulse counter. This can be done with the help of the CNT UF/OF PRS and CNT DIR PRS ouputs. The figure Figure 16.14 PCNT Cascading to two 16-bit PCNT to form a 32-bit PCNT on page 428 illustrates this structure.
- Page 429 Reference Manual PCNT - Pulse Counter 16.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PCNTn_CTRL Control Register 0x004 PCNTn_CMD Command Register 0x008 PCNTn_STATUS Status Register 0x00C PCNTn_CNT Counter Value Register 0x010 PCNTn_TOP Top Value Register...
- Page 430 Reference Manual PCNT - Pulse Counter 16.5 Register Description 16.5.1 PCNTn_CTRL - Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name Name Reset Access Description TOPBHFSEL...
- Page 431 Reference Manual PCNT - Pulse Counter Name Reset Access Description PRSGATEEN PRS Gate Enable When set, the clock input to the pulse counter will be gated when the selected PRS input is the inverse of TCCPRSPOL. 23:22 TCCCOMP Triggered Compare and Clear Compare Mode Selects the mode for comparison upon a compare and clear event.
- Page 432 Reference Manual PCNT - Pulse Counter Name Reset Access Description CNTDIR Non-Quadrature Mode Counter Direction Control The direction of the counter must be set in the OVSSINGLE and EXTCLKSINGLE modes. This bit is ignored in EX- TCLKQUAD mode as the direction is automatically detected. Value Mode Description...
- Page 433 Reference Manual PCNT - Pulse Counter Name Reset Access Description CNTRSTEN Enable CNT Reset The counter, CNT, is asynchronously held in reset when this bit is set. The reset is synchronously released two PCNT clock edges after this bit is cleared. If an external clock is used, the reset should be performed by setting and clearing the bit without pending for SYNCBUSY bit.
- Page 434 Reference Manual PCNT - Pulse Counter 16.5.2 PCNTn_CMD - Command Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 435 Reference Manual PCNT - Pulse Counter 16.5.4 PCNTn_CNT - Counter Value Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0 0x0000...
- Page 436 Reference Manual PCNT - Pulse Counter 16.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:16 Reserved...
- Page 437 Reference Manual PCNT - Pulse Counter 16.5.8 PCNTn_IFS - Interrupt Flag Set Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OQSTERR...
- Page 438 Reference Manual PCNT - Pulse Counter 16.5.9 PCNTn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OQSTERR...
- Page 439 Reference Manual PCNT - Pulse Counter 16.5.10 PCNTn_IEN - Interrupt Enable Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OQSTERR OQSTERR Interrupt Enable...
- Page 440 Reference Manual PCNT - Pulse Counter 16.5.11 PCNTn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
- Page 441 Reference Manual PCNT - Pulse Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions S0INLOC...
- Page 442 Reference Manual PCNT - Pulse Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 16.5.12 PCNTn_FREEZE - Freeze Register Offset Bit Position 0x040...
- Page 443 Reference Manual PCNT - Pulse Counter 16.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OVSCFG OVSCFG Register Busy...
- Page 444 Reference Manual PCNT - Pulse Counter 16.5.15 PCNTn_INPUT - PCNT Input Register Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions S1PRSEN S1IN PRS Enable...
- Page 445 Reference Manual PCNT - Pulse Counter Name Reset Access Description PRSCH0 PRS Channel 0 selected. PRSCH1 PRS Channel 1 selected. PRSCH2 PRS Channel 2 selected. PRSCH3 PRS Channel 3 selected. PRSCH4 PRS Channel 4 selected. PRSCH5 PRS Channel 5 selected. PRSCH6 PRS Channel 6 selected.
- Page 446 Reference Manual I2C - Inter-Integrated Circuit Interface 17. I2C - Inter-Integrated Circuit Interface Quick Facts What? The I C interface allows communication on I buses with the lowest energy consumption possible. Why? C is a popular serial bus that enables communica- tion with a number of external devices using only Gecko Device C master/slave...
- Page 447 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3 Functional Description An overview of the I2C module is shown in Figure 17.1 I2C Overview on page 447. Peripheral Bus C Control and Transmit Buffer Receive Buffer Status (2-level FIFO) (2-level FIFO) I2Cn_SDA Symbol Transmit...
- Page 448 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.1 I2C-Bus Overview The I C-bus uses two wires for communication; a serial data line (SDA) and a serial clock line (SCL) as shown in Figure 17.2 I2C-Bus Example on page 448. As a true multi-master bus it includes collision detection and arbitration to resolve situations where multiple masters transmit data at the same time without data loss.
- Page 449 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.1.1 START and STOP Conditions START and STOP conditions are used to initiate and stop transactions on the I C-bus. All transactions on the bus begin with a START condition (S) and end with a STOP condition (P). As shown in Figure 17.4 I2C START and STOP Conditions on page 449, a START condition is generated by pulling the SDA line low while SCL is high, and a STOP condition is generated by pulling the SDA line high...
- Page 450 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.1.2 Bus Transfer When a master wants to initiate a transfer on the bus, it waits until the bus is idle and transmits a START condition on the bus. The master then transmits the address of the slave it wishes to interact with and a single R/W bit telling whether it wishes to read from the slave (R/W bit set to 1) or write to the slave (R/W bit set to 0).
- Page 451 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.1.3 Addresses C supports both 7-bit and 10-bit addresses. When using 7-bit addresses, the first byte transmitted after the START-condition contains the address of the slave that the master wants to contact. In the 7-bit address space, several addresses are reserved. These addresses are summarized in Table 17.1 I2C Reserved I C Addresses on page...
- Page 452 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.1.5 Arbitration, Clock Synchronization, Clock Stretching Arbitration and clock synchronization are features aimed at allowing multi-master buses. Arbitration occurs when two devices try to drive the bus at the same time. If one device drives it low, while the other drives it high, the one attempting to drive it high will not be able to do so due to the open-drain bus configuration.
- Page 453 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.5 Arbitration Arbitration is enabled by default, but can be disabled by setting the ARBDIS bit in I2Cn_CTRL. When arbitration is enabled, the value on SDA is sensed every time the I C module attempts to change its value. If the sensed value is different than the value the I C module tried to output, it is interpreted as a simultaneous transmission by another device, and that the I C module has lost arbitration.
- Page 454 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.6.2 Receive Buffer and Shift Register The I C receiver uses a 2-level FIFO receive buffer and a receive shift register as shown in Figure 17.14 I2C Receive Buffer Operation on page 454. When a byte has been fully received by the receive shift register, it is loaded into the receive buffer if there is room for it, making the shift register empty to receive another byte.
- Page 455 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.7 Master Operation A bus transaction is initiated by transmitting a START condition (S) on the bus. This is done by setting the START bit in I2Cn_CMD. The command schedules a START condition, and makes the I C module generate a start condition whenever the bus becomes free.
- Page 456 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.7.1 Master State Machine The master state machine is shown in Figure 17.15 I2C Master State Machine on page 456. A master operation starts in the far left of the state machine, and follows the solid lines through the state machine, ending the operation or continuing with a new operation when arriving at the right side of the state machine.
- Page 457 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.7.2 Interactions Whenever the I C module is waiting for interaction from software, it holds the bus clock SCL low, freezing all bus activities, and the BUSHOLD interrupt flag in I2Cn_IF is set. The action(s) required by software depends on the current state the of the I C module.
- Page 458 Reference Manual I2C - Inter-Integrated Circuit Interface Pending commands can be cleared by setting the CLEARPC command bit in I2Cn_CMD. 17.3.7.3 Automatic ACK Interaction When receiving addresses and data, an ACK command in I2Cn_CMD is normally required after each received byte. When AUTOACK is set in I2Cn_CTRL, an ACK is always pending, and the ACK-pending bit PACK in I2Cn_STATUS is thus always set, even after an ACK has been consumed.
- Page 459 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.7.5 Master Transmitter To transmit data to a slave, the master must operate as a master transmitter. Table 17.3 I2C Master Transmitter on page 459 shows the states the I C module goes through while acting as a master transmitter. Every state where an interaction is required has the possi- ble interactions listed, along with the result of the interactions.
- Page 460 Reference Manual I2C - Inter-Integrated Circuit Interface I2Cn_STATE Description I2Cn_IF Required in- Response teraction 0x97 ADDR+W transmitted, ACK interrupt flag TXDATA DATA will be sent ACK received (BUSHOLD interrupt STOP STOP will be sent. Bus will be released flag) START Repeated start condition will be sent STOP + STOP will be sent and the bus released.
- Page 461 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.7.6 Master Receiver To receive data from a slave, the master must operate as a master receiver, see Table 17.4 I2C Master Receiver on page 461. This is done by transmitting ADDR+R as the address byte instead of ADDR+W, which is transmitted to become a master transmitter. The ad- dress byte loaded into the data register thus has to contain the 7-bit slave address in the 7 most significant bits of the byte, and have the least significant bit set.
- Page 462 Reference Manual I2C - Inter-Integrated Circuit Interface I2Cn_STATE Description I2Cn_IF Required in- Response teraction 0xB3 Data received RXDATA interrupt ACK + RXDA- ACK will be transmitted, reception continues flag(BUSHOLD inter- rupt flag) NACK + NACK will be transmitted, reception continues CONT + RXDATA ACK/NACK +...
- Page 463 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.8 Bus States The I2Cn_STATE register can be used to determine which state the I C module and the I C bus are in at a given time. The register consists of the STATE bit-field, which shows which state the I C module is at in any ongoing transmission, and a set of single-bits, which reveal the transmission mode, whether the bus is busy or idle, and whether the bus is held by this I C module waiting for a soft-...
- Page 464 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.9.1 Slave State Machine The slave state machine is shown in Figure 17.16 I2C Slave State Machine on page 464. The dotted lines show where I C-specific interrupt flags are set. The full-drawn circles show places where interaction may be required by software to let the transmission pro- ceed.
- Page 465 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.9.3 Slave Transmitter When SLAVE in I2Cn_CTRL is set, the RSTART interrupt flag in I2Cn_IF will be set when repeated START conditions are detected. After a START or repeated START condition, the bus master will transmit an address along with an R/W bit. If there is no room in the receive shift register for the address, the bus will be held by the slave until room is available in the shift register.
- Page 466 Reference Manual I2C - Inter-Integrated Circuit Interface I2Cn_STATE Description I2Cn_IF Required in- Response teraction Stop received SSTOP interrupt flag None The slave goes idle START START will be sent when bus becomes idle Arbitration lost ARBLOST interrupt flag None The slave goes idle START START will be sent when the bus becomes idle silabs.com | Building a more connected world.
- Page 467 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.9.4 Slave Receiver A slave receiver operation is started in the same way as a slave transmitter operation, with the exception that the address transmitted by the master has the R/W bit cleared (W), indicating that the master wishes to write to the slave. The slave then goes into slave receiv- er mode.
- Page 468 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.10.1 DMA DMA can be used to automatically load data into the transmit buffer and load data out from the receive buffer. When using DMA, soft- ware is thus relieved of moving data to and from memory after each transferred byte. 17.3.10.2 Automatic ACK When AUTOACK in I2Cn_CTRL is set, an ACK is sent automatically whenever an ACK interaction is possible and no higher priority interactions are pending.
- Page 469 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.12.3 I2C-Bus Errors An I C-bus error occurs when a START or STOP condition is misplaced, which happens when the value on SDA changes while SCL is high during bit-transmission on the I C-bus.
- Page 470 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.12.7 Clock Low Error The I C module can continue transmission in parallel with another device for the entire transaction, as long as the two communications are identical. A case may arise when (before an arbitration has been decided upon) the I C module decides to send out a repeated START or a STOP condition while the other device is still sending data.
- Page 471 Reference Manual I2C - Inter-Integrated Circuit Interface 17.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 I2Cn_CTRL Control Register 0x004 I2Cn_CMD Command Register 0x008 I2Cn_STATE State Register 0x00C I2Cn_STATUS Status Register 0x010 I2Cn_CLKDIV Clock Division Register...
- Page 472 Reference Manual I2C - Inter-Integrated Circuit Interface 17.5 Register Description 17.5.1 I2Cn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 18:16...
- Page 473 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description 13:12 BITO Bus Idle Timeout Use to generate a timeout when SCL has been high for a given amount time between a START and STOP condition. When in a bus transaction, i.e. the BUSY flag is set, a timer is started whenever SCL goes high. When the timer reaches the value defined by BITO, it sets the BITO interrupt flag.
- Page 474 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description When a general call address is received, a software response is re- quired. ARBDIS Arbitration Disable A master or slave will not release the bus upon losing arbitration. Value Description When a device loses arbitration, the ARB interrupt flag is set and the bus is released.
- Page 475 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description Value Description The I C module is disabled. And its internal state is cleared The I C module is enabled. 17.5.2 I2Cn_CMD - Command Register Offset Bit Position 0x004 Reset Access Name...
- Page 476 Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.3 I2Cn_STATE - State Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions STATE Transmission State...
- Page 477 Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.4 I2Cn_STATUS - Status Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXFULL RX FIFO Full...
- Page 478 Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.5 I2Cn_CLKDIV - Clock Division Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 0x000...
- Page 479 Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.7 I2Cn_SADDRMASK - Slave Address Mask Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions MASK...
- Page 480 Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.9 I2Cn_RXDOUBLE - Receive Buffer Double Data Register (Actionable Reads) Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:8...
- Page 481 Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.11 I2Cn_RXDOUBLEP - Receive Buffer Double Data Peek Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:8...
- Page 482 Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.13 I2Cn_TXDOUBLE - Transmit Buffer Double Data Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:8...
- Page 483 Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.14 I2Cn_IF - Interrupt Flag Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLERR...
- Page 484 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description RXDATAV Receive Data Valid Interrupt Flag Set when data is available in the receive buffer. Cleared automatically when the receive buffer is read. TXBL Transmit Buffer Level Interrupt Flag Set when the transmit buffer becomes empty.
- Page 485 Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.15 I2Cn_IFS - Interrupt Flag Set Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLERR...
- Page 486 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description Set TXC Interrupt Flag Write 1 to set the TXC interrupt flag ADDR Set ADDR Interrupt Flag Write 1 to set the ADDR interrupt flag RSTART Set RSTART Interrupt Flag Write 1 to set the RSTART interrupt flag START Set START Interrupt Flag...
- Page 487 Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.16 I2Cn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLERR...
- Page 488 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description MSTOP (R)W1 Clear MSTOP Interrupt Flag Write 1 to clear the MSTOP interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.). NACK (R)W1 Clear NACK Interrupt Flag...
- Page 489 Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.17 I2Cn_IEN - Interrupt Enable Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLERR...
- Page 490 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description RXDATAV RXDATAV Interrupt Enable Enable/disable the RXDATAV interrupt TXBL TXBL Interrupt Enable Enable/disable the TXBL interrupt TXC Interrupt Enable Enable/disable the TXC interrupt ADDR ADDR Interrupt Enable Enable/disable the ADDR interrupt RSTART RSTART Interrupt Enable Enable/disable the RSTART interrupt...
- Page 491 Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.19 I2Cn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
- Page 492 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SDALOC...
- Page 493 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
- Page 494 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18. USART - Universal Synchronous Asynchronous Receiver/Transmitter Quick Facts What? The USART handles high-speed UART, SPI-bus, SmartCards, and IrDA communication. Why? Serial communication is frequently used in embed- ded systems and the USART allows efficient com- munication with a wide range of external devices.
- Page 495 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.2 Features • Asynchronous and synchronous (SPI) communication • Full duplex and half duplex • Separate TX/RX enable • Separate receive / transmit multiple entry buffers, with additional separate shift registers • Programmable baud rate, generated as an fractional division from the peripheral clock (HFPERCLK USARTn •...
- Page 496 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3 Functional Description An overview of the USART module is shown in Figure 18.1 USART Overview on page 496. This section describes all possible USART features. Refer to the device data sheet to see what features a specific USART instance supports.
- Page 497 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.1 Modes of Operation The USART operates in either asynchronous or synchronous mode. In synchronous mode, a separate clock signal is transmitted with the data. This clock signal is generated by the bus master, and both the master and slave sample and transmit data according to this clock.
- Page 498 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.1 Frame Format The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a frame, and is used for synchronization.
- Page 499 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter The order in which the data bits are transmitted and received is defined by MSBF in USARTn_CTRL. When MSBF is cleared, data in a frame is sent and received with the least significant bit first. When it is set, the most significant bit comes first. The frame format used by the transmitter can be inverted by setting TXINV in USARTn_CTRL, and the format expected by the receiver can be inverted by setting RXINV in USARTn_CTRL.
- Page 500 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.3 Clock Generation The USART clock defines the transmission and reception data rate. When operating in asynchronous mode, the baud rate (bit-rate) is given by Figure 18.3 USART Baud Rate on page 500.
- Page 501 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter USARTn_OVS =00 USARTn_OVS =01 Desired baud USARTn_CLKDIV/256 Actual baud rate USARTn_CLKDIV/256 Actual baud rate rate [baud/s] Error % Error % (to 32nd position) [baud/s] (to 32nd position) [baud/s] 38400 38461.54 0.160 12.03125 38369.3 -0.080 57600...
- Page 502 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.6 Transmit Buffer Operation The transmit-buffer is a multiple entry FIFO buffer. A frame can be loaded into the buffer by writing to USARTn_TXDATA, USARTn_TXDATAX, USARTn_TXDOUBLE or USARTn_TXDOUBLEX. Using USARTn_TXDATA allows 8 bits to be written to the buf- fer, while using USARTn_TXDOUBLE will write 2 frames of 8 bits to the buffer.
- Page 503 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.7 Frame Transmission Control The transmission control bits, which can be written using USARTn_TXDATAX and USARTn_TXDOUBLEX, affect the transmission of the written frame. The following options are available: • Generate break: By setting TXBREAK, the output will be held low during the stop-bit period to generate a framing error. A receiver that supports break detection detects this state, allowing it to be used e.g.
- Page 504 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.9 Receive Buffer Operation When data becomes available in the receive buffer, the RXDATAV flag in USARTn_STATUS, and the RXDATAV interrupt flag in USARTn_IF are set, and when the buffer becomes full, RXFULL in USARTn_STATUS and the RXFULL interrupt flag in USARTn_IF are set.
- Page 505 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.10 Blocking Incoming Data When using hardware frame recognition, as detailed in 18.3.2.20 Multi-Processor Mode 18.3.2.21 Collision Detection, it is necessa- ry to be able to let the receiver sample incoming frames without passing the frames to software by loading them into the receive buffer. This is accomplished by blocking incoming data.
- Page 506 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.11 Clock Recovery and Filtering The receiver samples the incoming signal at a rate 16, 8, 6 or 4 times higher than the given baud rate, depending on the oversampling mode given by OVS in USARTn_CTRL. Lower oversampling rates make higher baud rates possible, but give less room for errors. When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a start-bit, and the baud rate generator is synchronized with the incoming frame.
- Page 507 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter n’th bit 1 stop bit Idle or start bit 13 14 15 16 1 9 10 0/1 Figure 18.8. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More When working with stop bit lengths of half a baud period, the above sampling scheme no longer suffices.
- Page 508 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.14 Local Loopback The USART receiver samples U(S)n_RX by default, and the transmitter drives U(S)n_TX by default. This is not the only option howev- er. When LOOPBK in USARTn_CTRL is set, the receiver is connected to the U(S)n_TX pin as shown in Figure 18.9 USART Local Loopback on page 508.
- Page 509 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.17 Single Data-link With External Driver Some communication schemes, such as RS-485 rely on an external driver. Here, the driver has an extra input which enables it, and instead of tristating the transmitter when receiving data, the external driver must be disabled. This can be done manually by assigning a GPIO to turn the driver on or off, or it can be handled automatically by the USART.
- Page 510 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.19 Large Frames As each frame in the transmit and receive buffers holds a maximum of 9 bits, both the elements in the buffers are combined when working with USART-frames of 10 or more data bits. To transmit such a frame, at least two elements must be available in the transmit buffer.
- Page 511 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter When receiving a large frame, BYTESWAP in USARTn_CTRL determines the order the way the large frame is split into the two buffer elements. If BYTESWAP is cleared, the least significant 8 bits of the received frame are loaded into the first element of the receive buffer, and the remaining bits are loaded into the second element, as shown in Figure 18.13 USART Reception of Large Frames on page...
- Page 512 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.21 Collision Detection The USART supports a basic form of collision detection. When the receiver is connected to the output of the transmitter, either by using the LOOPBK bit in USARTn_CTRL or through an external connection, this feature can be used to detect whether data transmitted on the bus by the USART did get corrupted by a simultaneous transmission by another device on the bus.
- Page 513 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.22 SmartCard Mode In SmartCard mode, the USART supports the ISO 7816 I/O line T0 mode. With exception of the stop-bits (guard time), the 7816 data frame is equal to the regular asynchronous frame. In this mode, the receiver pulls the line low for one baud, half a baud into the guard time to indicate a parity error.
- Page 514 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 1/2 stop bit NAK or stop Stop 13 14 15 16 1 9 10 11 14 15 16 17 18 X Figure 18.16. USART SmartCard Stop Bit Sampling For communication with a SmartCard, a clock signal needs to be generated for the card. This clock output can be generated using one of the timers.
- Page 515 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.3.2 Clock Generation The bit-rate in synchronous mode is given by Figure 18.17 USART Synchronous Mode Bit Rate on page 515. As in the case of asyn- chronous operation, the clock division factor have a 15-bit integral part and a 5-bit fractional part. br = f /(2 x (1 + USARTn_CLKDIV/256)) HFPERCLK...
- Page 516 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter RXDATAV flag is updated on the last sample clock edge of a transfer, while the RX overflow interrupt flag, RXOF, is set on the first sample clock edge if the receive buffer overflows. When a transfer has been performed, interrupt flags TXBL and TXC are updated on the first setup clock edge of the succeeding frame, or when CS is deasserted.
- Page 517 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.3.7 Synchronous Half Duplex Communication Half duplex communication in synchronous mode is very similar to half duplex communication in asynchronous mode as detailed in 18.3.2.15 Asynchronous Half Duplex Communication. The main difference is that in this mode, the master must generate the bus clock even when it is not transmitting data, i.e.
- Page 518 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.3.10 Major Modes The USART supports a set of different I2S formats as shown in Table 18.9 USART I2S Modes on page 518, but it is not limited to these modes. MONO, JUSTIFY and DELAY in USARTn_I2SCTRL can be mixed and matched to create an appropriate format. MONO enables mono mode, i.e.
- Page 519 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter USn_CLK USn_CS (word select) USn_TX/ USn_RX Left channel Right channel Left channel Figure 18.22. USART Left-Justified I2S Waveform A right-justified stream is shown in Figure 18.23 USART Right-Justified I2S Waveform on page 519.
- Page 520 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.3.11 Using I2S Mode When using the USART in I2S mode, DATABITS in USARTn_FRAME must be set to 8 or 16 data-bits. 8 databits can be used in all modes, and 16 can be used in the modes where the number of bytes in the I2S word is even. In addition to this, MSBF in USARTn_CTRL should be set, and CLKPOL and CLKPHA in USARTn_CTRL should be cleared.
- Page 521 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.8 PRS CLK Input The USART can be configured to receive clock directly from a PRS channel by setting CLKPRS in USARTn_INPUT. The PRS channel used is selected using CLKPRSSEL in USARTn_INPUT. This is useful in synchronous slave mode and can together with RX PRS input be used to input data from PRS.
- Page 522 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.10 Timer In addition to the TX sequence timer, there is a versatile 8 bit timer that can generate up to three event pulses. These pulses can be used to create timing for a variety of uses such as RX timeout, break detection, response timeout, and RX enable delay. Transmission delay, CS setup, inter-character spacing, and CS hold use the TX sequence counter.
- Page 523 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter TIMECMP2 TIMECMP1 TIMECMP0 TCMPn TXST RXACT TCMPVALn RXACTN TSTOP GP_CNT[7:0] clear DISABLE TCMP TXEOF Compare TCMPn enable RXACT RXEOF TSTART START_An RESTARTEN START_Bn START_A2 START_B2 START_A1 start START_B1 event START_A0 8 bit bit time GP_CNT[7:0] START_B0...
- Page 524 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Application TSTARTn TSTOPn TCMPVALn Other Break Detect TSTART1 = RXACT TSTOP1 = TCMPVAL1 TCMP1 in USARTn_IEN RXACTN = 0x0C TX delayed start of transmission and TSTART0 = DISA- TSTOP0 = TCMP0, TCMPVAL0 TXDELAY = TCMP0, CSSETUP = CS setup BLE, TSTART1 =...
- Page 525 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.10.2 RX Timeout A receiver timeout function can be implemented by using the RX end of frame to start comparator 1 and look for the RX start bit RXACT to disable the comparator. See Table 18.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 523 for details on setting up this example.
- Page 526 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.10.4 TX Start Delay Some applications may require a delay before the start of transmission. This example in Figure 18.29 USART TXSEQ Timing on page shows the TXSEQ timer used to delay the start of transmission by 4 baud times before the start of CS, and by 2 baud times with CS asserted.
- Page 527 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.10.8 Combined TX and RX Example This example describes how to alternate between TX and RX frames. This has a 28 baud-time space after RX and a 16 baud-time space after TX. The TSTART1 in USARTn_TIMECMP1 is set to RXEOF which uses the the receiver end of frame to start the timer. The TSTOP1 is set to TCMP1 to generate an event after 28 baud times.
- Page 528 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.12 IrDA Modulator/ Demodulator The IrDA modulator implements the physical layer of the IrDA specification, which is necessary for communication over IrDA. The mod- ulator takes the signal output from the USART module, and modulates it before it leaves the USART. In the same way, the input signal is demodulated before it enters the actual USART module.
- Page 529 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 USARTn_CTRL Control Register 0x004 USARTn_FRAME USART Frame Format Register 0x008 USARTn_TRIGCTRL USART Trigger Control Register 0x00C USARTn_CMD Command Register...
- Page 530 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5 Register Description 18.5.1 USARTn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description SMSDELAY Synchronous Master Sample Delay Delay Synchronous Master sample point to the next setup edge to improve timing and allow communication at higher speeds MVDIS Majority Vote Disable...
- Page 531 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Framing and parity errors disable the receiver ERRSDMA Halt DMA on Error When set, DMA requests will be cleared on framing and parity errors (asynchronous mode only). Value Description Framing and parity errors have no effect on DMA requests from the USART...
- Page 532 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Output from the transmitter is inverted before it is passed to U(S)n_TX RXINV Receiver Input Invert Setting this bit will invert the input to the USART receiver. Value Description Input is passed directly to the receiver Input is inverted before it is passed to the receiver...
- Page 533 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description IDLEHIGH The bus clock used in synchronous mode has a high base value Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions Oversampling...
- Page 534 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description The USART operates in synchronous mode silabs.com | Building a more connected world. Rev. 1.3 | 534...
- Page 535 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.2 USARTn_FRAME - USART Frame Format Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:12...
- Page 536 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Each frame contains 6 data bits SEVEN Each frame contains 7 data bits EIGHT Each frame contains 8 data bits NINE Each frame contains 9 data bits Each frame contains 10 data bits ELEVEN Each frame contains 11 data bits TWELVE...
- Page 537 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.3 USARTn_TRIGCTRL - USART Trigger Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 19:16...
- Page 538 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description TXARX2EN Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL When set, an RX end of frame will trigger the transmitter after TCMP2VAL bit times to force a minimum response delay TXARX1EN Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL When set, an RX end of frame will trigger the transmitter after TCMP1VAL bit times to force a minimum response delay...
- Page 539 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.4 USARTn_CMD - Command Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLEARRX...
- Page 540 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.5 USARTn_STATUS - USART Status Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 17:16...
- Page 541 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description TX Complete Set when a transmission has completed and no more data is available in the transmit buffer and shift register. Cleared when data is written to the transmit buffer. TXTRI Transmitter Tristated Set when the transmitter is tristated, and cleared when transmitter output is enabled.
- Page 542 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register (Actionable Reads) Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions FERR...
- Page 543 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register (Actionable Reads) Offset Bit Position 0x020 Reset Access Name Name Reset Access Description FERR1 Data Framing Error 1 Set if data in buffer has a framing error. Can be the result of a break condition. PERR1 Data Parity Error 1 Set if data in buffer has a parity error (asynchronous mode only).
- Page 544 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register (Actionable Reads) Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:8...
- Page 545 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description FERRP1 Data Framing Error 1 Peek Set if data in buffer has a framing error. Can be the result of a break condition. PERRP1 Data Parity Error 1 Peek Set if data in buffer has a parity error (asynchronous mode only).
- Page 546 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXENAT...
- Page 547 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.14 USARTn_TXDATA - TX Buffer Data Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TXDATA...
- Page 548 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description RXENAT1 Enable RX After Transmission Set to enable reception after transmission. TXDISAT1 Clear TXEN After Transmission Set to disable transmitter and release data bus directly after transmission.
- Page 549 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:8...
- Page 550 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.17 USARTn_IF - Interrupt Flag Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMP2...
- Page 551 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXFULL RX Buffer Full Interrupt Flag Set when the receive buffer becomes full. RXDATAV RX Data Valid Interrupt Flag Set when data becomes available in the receive buffer. TXBL TX Buffer Level Interrupt Flag Set when buffer becomes empty if buffer level is set to 0x0, or when the number of empty TX buffer elements equals speci-...
- Page 552 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.18 USARTn_IFS - Interrupt Flag Set Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMP2...
- Page 553 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions Set TXC Interrupt Flag Write 1 to set the TXC interrupt flag silabs.com | Building a more connected world.
- Page 554 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.19 USARTn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMP2...
- Page 555 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description TXOF (R)W1 Clear TXOF Interrupt Flag Write 1 to clear the TXOF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.). RXUF (R)W1 Clear RXUF Interrupt Flag...
- Page 556 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.20 USARTn_IEN - Interrupt Enable Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMP2...
- Page 557 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXFULL RXFULL Interrupt Enable Enable/disable the RXFULL interrupt RXDATAV RXDATAV Interrupt Enable Enable/disable the RXDATAV interrupt TXBL TXBL Interrupt Enable Enable/disable the TXBL interrupt TXC Interrupt Enable Enable/disable the TXC interrupt silabs.com | Building a more connected world.
- Page 558 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.21 USARTn_IRCTRL - IrDA Control Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 11:8...
- Page 559 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description IRPW IrDA TX Pulse Width Configure the pulse width generated by the IrDA modulator as a fraction of the configured USART bit period. Value Mode Description IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1...
- Page 560 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.22 USARTn_INPUT - USART Input Register Offset Bit Position 0x058 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLKPRS...
- Page 561 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description PRSCH0 PRS Channel 0 selected PRSCH1 PRS Channel 1 selected PRSCH2 PRS Channel 2 selected PRSCH3 PRS Channel 3 selected PRSCH4 PRS Channel 4 selected PRSCH5 PRS Channel 5 selected PRSCH6 PRS Channel 6 selected PRSCH7...
- Page 562 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.23 USARTn_I2SCTRL - I2S Control Register Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 10:8...
- Page 563 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Enable I2S Mode Set the U(S)ART in I2S mode. silabs.com | Building a more connected world. Rev. 1.3 | 563...
- Page 564 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.24 USARTn_TIMING - Timing Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 30:28 CSHOLD...
- Page 565 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 22:20...
- Page 566 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.25 USARTn_CTRLX - Control Register Extended Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RTSINV...
- Page 567 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.26 USARTn_TIMECMP0 - Used to Generate Interrupts and Various Delays Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RESTARTEN...
- Page 568 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 15:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMPVAL 0x00 Timer Comparator 0 When the timer equals TCMPVAL, this signals a TCMP0 event and sets the TCMP0 flag. This event can also be used to enable various USART functionality.
- Page 569 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.27 USARTn_TIMECMP1 - Used to Generate Interrupts and Various Delays Offset Bit Position 0x06C Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RESTARTEN...
- Page 570 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 15:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMPVAL 0x00 Timer Comparator 1 When the timer equals TCMPVAL, this signals a TCMP1 event and sets the TCMP1 flag. This event can also be used to enable various USART functionality.
- Page 571 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.28 USARTn_TIMECMP2 - Used to Generate Interrupts and Various Delays Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RESTARTEN...
- Page 572 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 15:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMPVAL 0x00 Timer Comparator 2 When the timer equals TCMPVAL, this signals a TCMP2 event and sets the TCMP2 flag. This event can also be used to enable various USART functionality.
- Page 573 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.29 USARTn_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x074 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RTSPEN...
- Page 574 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXPEN RX Pin Enable When set, the RX/MISO pin of the USART is enabled. Value Description The U(S)n_RX (MISO) pin is disabled The U(S)n_RX (MISO) pin is enabled silabs.com | Building a more connected world.
- Page 575 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.30 USARTn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x078 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24...
- Page 576 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 23:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16...
- Page 577 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
- Page 578 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXLOC...
- Page 579 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
- Page 580 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.31 USARTn_ROUTELOC1 - I/O Routing Location Register Offset Bit Position 0x07C Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
- Page 581 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 582 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
- Page 583 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19. LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Quick Facts What? The LEUART provides full UART communication us- ing a low frequency 32.768 kHz clock, and has spe- cial features for communication without CPU inter- vention.
- Page 584 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.2 Features • Low energy asynchronous serial communications • Full/half duplex communication • Separate TX / RX enable • Separate double buffered transmit buffer and receive buffer • Programmable baud rate, generated as a fractional division of the LFBCLK •...
- Page 585 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3 Functional Description An overview of the LEUART module is shown in Figure 19.1 LEUART Overview on page 585. Peripheral Bus UART Control TX Buffer RX Buffer and status !RXBLOCK Start frame (STARTFRAME) Start frame interrupt Signal frame interrupt...
- Page 586 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.1 Frame Format The frame format used by the LEUART consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a frame, and is used for synchronization.
- Page 587 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.3 Clock Generation The LEUART clock defines the transmission and reception data rate. The clock generator employs a fractional clock divider to allow baud rates that are not attainable by integral division of the 32.768 kHz clock that drives the LEUART. The clock divider used in the LEUART is a 14-bit value, with a 9-bit integral part and a 5-bit fractional part.
- Page 588 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.4.1 Transmit Buffer Operation A frame can be loaded into the transmit buffer by writing to LEUARTn_TXDATA or LEUARTn_TXDATAX. Using LEUARTn_TXDATA allows 8 bits to be written to the buffer. If 9 bit frames are used, the 9th bit will in that case be set to the value of BIT8DV in LEUARTn_CTRL.
- Page 589 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.5 Data Reception Data reception is enabled by setting RXEN in LEUARTn_CMD. When the receiver is enabled, it actively samples the input looking for a transition from high to low indicating the start bit of a new frame. When a start bit is found, reception of the new frame begins if the receive shift register is empty and ready for new data.
- Page 590 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.5.2 Blocking Incoming Data When using hardware frame recognition, as detailed in 19.3.5.6 Programmable Start Frame, 19.3.5.7 Programmable Signal Frame, and 19.3.5.8 Multi-Processor Mode, it is necessary to be able to let the receiver sample incoming frames without passing the frames to software by loading them into the receive buffer.
- Page 591 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.5.5 Framing Error and Break Detection A framing error is the result of a received frame where the stop bit was sampled to a value of 0. This can be the result of noise and baud rate errors, but can also be the result of a break generated by the transmitter on purpose.
- Page 592 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.6 Loopback The LEUART receiver samples LEUn_RX by default, and the transmitter drives LEUn_TX by default. This is not the only configuration however. When LOOPBK in LEUARTn_CTRL is set, the receiver is connected to the LEUn_TX pin as shown in Figure 19.9 LEUART Local Loopback on page 592.
- Page 593 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.7.2 Single Data-link With External Driver Some communication schemes, such as RS-485 rely on an external driver. Here, the driver has an extra input which enables it, and instead of Tristating the transmitter when receiving data, the external driver must be disabled. The USART has hardware support for automatically turning the driver on and off.
- Page 594 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.10 DMA Support The LEUART has full DMA support in energy modes EM0 Active – EM2 DeepSleep. The DMA controller can write to the transmit buffer using the registers LEUARTn_TXDATA and LEUARTn_TXDATAX, and it can read from receive buffer using the registers LEUARTn_RXDATA and LEUARTn_RXDATAX.
- Page 595 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.11.1 Interrupts The interrupts generated by the LEUART are combined into one interrupt vector. If LEUART interrupts are enabled, an interrupt will be made if one or more of the interrupt flags in LEUARTn_IF and their corresponding bits in LEUART_IEN are set. 19.3.12 Register Access Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations must be taken when accessing registers.
- Page 596 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5 Register Description 19.5.1 LEUARTn_CTRL - Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name Name Reset...
- Page 597 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Name Reset Access Description MPAB Multi-Processor Address-Bit Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks the frame as a multi-processor address frame. Multi-Processor Mode Set to enable multi-processor mode.
- Page 598 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Name Reset Access Description One stop-bit is transmitted with every frame Two stop-bits are transmitted with every frame PARITY Parity-Bit Mode Determines whether parity bits are enabled, and whether even or odd parity should be used. Value Mode Description...
- Page 599 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.2 LEUARTn_CMD - Command Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:8...
- Page 600 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.3 LEUARTn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TXIDLE...
- Page 601 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x00C Reset Access Name Name Reset Access Description...
- Page 602 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x014 Reset Access Name Name Reset Access Description...
- Page 603 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads) Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXDATA...
- Page 604 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x024 Reset Access Name Name Reset...
- Page 605 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x028 Reset Access Name Name Reset Access...
- Page 606 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.12 LEUARTn_IF - Interrupt Flag Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SIGF...
- Page 607 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.13 LEUARTn_IFS - Interrupt Flag Set Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SIGF...
- Page 608 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.14 LEUARTn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SIGF...
- Page 609 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.15 LEUARTn_IEN - Interrupt Enable Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SIGF...
- Page 610 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x03C Reset Access Name Name Reset Access Description...
- Page 611 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.17 LEUARTn_FREEZE - Freeze Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions REGFREEZE...
- Page 612 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PULSECTRL...
- Page 613 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.19 LEUARTn_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TXPEN...
- Page 614 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.20 LEUARTn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x058 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
- Page 615 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Name Reset Access Description LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXLOC...
- Page 616 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Name Reset Access Description LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
- Page 617 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.21 LEUARTn_INPUT - LEUART Input Register Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXPRS...
- Page 618 Reference Manual TIMER - Timer/Counter 20. TIMER - Timer/Counter Quick Facts What? The TIMER (Timer/Counter) keeps track of timing and counts events, generates output waveforms, and triggers timed actions in other peripherals. Why? Most applications have activities that need to be USART timed accurately with as little CPU intervention and energy consumption as possible.
- Page 619 Reference Manual TIMER - Timer/Counter 20.2 Features • 16-bit auto reload up/down counter • Dedicated 16-bit reload register which serves as counter maximum • 3 or 4 Compare/Capture channels • Individually configurable as either input capture or output compare/PWM • Multiple Counter modes •...
- Page 620 Reference Manual TIMER - Timer/Counter • Dead-Time Insertion Unit • Complementary PWM outputs with programmable dead-time • Dead-time is specified independently for rising and falling edge • 10-bit prescaler • 6-bit time value • Outputs have configurable polarity • Outputs can be set inactive individually by software. •...
- Page 621 Reference Manual TIMER - Timer/Counter 20.3.1 Counter Modes The timer consists of a counter that can be configured to the following modes: 1. Up-count: Counter counts up until it reaches the value in TIMERn_TOP, where it is reset to 0 before counting up again. 2.
- Page 622 Reference Manual TIMER - Timer/Counter 20.3.1.2 Operation Figure 20.2 TIMER Hardware Timer/Counter Control on page 622 shows the hardware Timer/Counter control. Software can start or stop the counter by setting the START or STOP bits in TIMERn_CMD. The counter value (CNT in TIMERn_CNT) can always be written by software to any 16-bit value.
- Page 623 Reference Manual TIMER - Timer/Counter 20.3.1.4 Peripheral Clock (HFPERCLK) The peripheral clock (HFPERCLK) can be used as a source with a configurable prescale factor of 2^PRESC, where PRESC is an inte- ger between 0 and 10, which is set in PRESC in TIMERn_CTRL. However, if 2x Count Mode is enabled and the Compare/Capture channels are put in PWM mode, the CC output is updated on both clock edges so prescaling the peripheral clock will produce an incor- rect result.
- Page 624 Reference Manual TIMER - Timer/Counter 20.3.1.8 Top Value Buffer The TIMERn_TOP register can be altered either by writing it directly or by writing to the TIMER_TOPB (buffer) register. When writing to the buffer register the TIMERn_TOPB register will be written to TIMERn_TOP on the next update event. Buffering ensures that the TOP value is not set below the actual count value.
- Page 625 Reference Manual TIMER - Timer/Counter 20.3.1.9 Quadrature Decoder Quadrature Decoding mode is used to track motion and determine both rotation direction and position. The Quadrature Decoder uses two input channels that are 90 degrees out of phase (see Figure 20.6 TIMER Quadrature Encoded Inputs on page 625).
- Page 626 Reference Manual TIMER - Timer/Counter 20.3.1.10 X2 Decoding Mode In X2 Decoding mode, the counter increments or decrements on every edge of Channel A, see Table 20.1 TIMER Counter Response in X2 Decoding Mode on page 626 Figure 20.8 TIMER X2 Decoding Mode on page 626.
- Page 627 Reference Manual TIMER - Timer/Counter 20.3.1.12 TIMER Rotational Position To calculate a position Figure 20.10 TIMER Rotational Position Equation on page 627 can be used. pos° = (CNT/X x N) x 360° Figure 20.10. TIMER Rotational Position Equation where X = Encoding type and N = Number of pulses per revolution. 20.3.2 Compare/Capture Channels The timer contains 3 Compare/Capture channels, which can be configured in the following modes: 1.
- Page 628 Reference Manual TIMER - Timer/Counter 20.3.2.3 Input Capture In Input Capture Mode, the counter value (TIMERn_CNT) can be captured in the Compare/Capture Register (TIMERn_CCx_CCV) (see Figure 20.12 TIMER Input Capture on page 628). The CCPOL bits in TIMERn_STATUS indicate the polarity of the edge that trig- gered the capture in TIMERn_CCx_CCV.
- Page 629 Reference Manual TIMER - Timer/Counter 20.3.2.4 Period/Pulse-Width Capture Period and/or pulse-width capture can only be possible with Channel 0 (CC0), because this is the only channel that can start and stop the timer. This can be done by setting the RISEA field in TIMERn_CTRL to Clear&Start, and select the wanted input from either exter- nal pin or PRS, see Figure 20.13 TIMER Period and/or Pulse width Capture on page 629.
- Page 630 Reference Manual TIMER - Timer/Counter 20.3.2.5 Compare Each Compare/Capture channel contains a comparator which outputs a compare match if the contents of TIMERn_CCx_CCV matches the counter value, see Figure 20.14 TIMER Block Diagram Showing Comparison Functionality on page 630. In compare mode, each compare channel can be configured to either set, clear or toggle the output on an event (compare match, overflow or underflow).
- Page 631 Reference Manual TIMER - Timer/Counter 20.3.2.6 Compare Mode Registers When running in Output Compare or PWM mode, the value in TIMERn_CCx_CCV will be compared against the count value. In Com- pare mode the output can be configured to toggle, clear or set on compare match, overflow, and underflow through the CMOA, COFOA and CUFOA fields in TIMERn_CCx_CTRL.
- Page 632 Reference Manual TIMER - Timer/Counter 20.3.2.7 Frequency Generation (FRG) Frequency generation (see Figure 20.17 TIMER Up-count Frequency Generation on page 632) can be achieved in compare mode by: • Setting the counter in up-count mode • Enabling buffering of the TOP value. •...
- Page 633 Reference Manual TIMER - Timer/Counter 20.3.2.9 Up-count (Single-slope) PWM If the counter is set to up-count and the Compare/Capture channel is put in PWM mode, single slope PWM output will be generated (see Figure 20.20 TIMER Up-count PWM Generation on page 633).
- Page 634 Reference Manual TIMER - Timer/Counter 20.3.2.10 2x Count Mode (Up-count) When the timer is set in 2x mode, the TIMER will count up by two. This will in effect make any odd Top value be rounded down to the closest even number. Similarly, any odd CC value will generate a match on the closest lower even value as shown in Figure 20.25 TIMER CC out in 2x mode on page 634 Clock...
- Page 635 Reference Manual TIMER - Timer/Counter 20.3.2.11 Up/Down-count (Dual-slope) PWM If the counter is set to up-down count and the Compare/Capture channel is put in PWM mode, dual slope PWM output will be generated Figure 20.29 TIMER Up/Down-count PWM Generation on page 635.The resolution (in bits) is given by Figure 20.30 TIMER Up/ Down-count PWM Resolution Equation on page...
- Page 636 Reference Manual TIMER - Timer/Counter 20.3.2.12 2x Count Mode (Up/Down-count) When the timer is set in 2x mode, the TIMER will count up/down by two. This will in effect make any odd Top value be rounded down to the closest even number. Similarly, any odd CC value will generate a match on the closest lower even value as shown in Figure 20.34 TIMER CC out in 2x mode on page 636 Clock...
- Page 637 Reference Manual TIMER - Timer/Counter 20.3.3 Dead-Time Insertion Unit Some of the timers include a Dead-Time Insertion module suitable for motor control applications. Refer to the device data sheet to check if a timer has this feature. The example settings in this section are for TIMER0, but identical settings can be used for other timers with DTI as well.
- Page 638 Reference Manual TIMER - Timer/Counter DTFALLT DTRISET Select Original PWM (TIM0_CCx_pre) HFPERCLK Clock control Counter TIMERn Primary output (TIM0_CCx) Complementary Output (TIM0_CDTIx) Figure 20.41. TIMER Overview of Dead-Time Insertion Block for a Single PWM channel The DTI unit is enabled by setting DTEN in TIMER0_DTCTRL. In addition to providing the complementary outputs, the DTI unit then also overrides the compare match outputs from the timer.
- Page 639 Reference Manual TIMER - Timer/Counter Table 20.3. DTI Output When Timer Halted DTAR DTFATS State frozen safe running running 20.3.3.1 Output Polarity The value of the primary and complementary outputs in a pair will never be set active at the same time by the DTI unit. The polarity of the outputs can be changed if this is required by the application.
- Page 640 Reference Manual TIMER - Timer/Counter 20.3.3.2 PRS Channel as a Source A PRS channel can be used as input to the DTI module instead of the PWM output from the timer for DTI channel 0. Setting DTPRSEN in TIMER0_DTCTRL will override the source of the first DTI channel, driving TIM0_CC0 and TIM0_CDTI0, with the value on the PRS channel.
- Page 641 Reference Manual TIMER - Timer/Counter 20.3.4 Debug Mode When the CPU is halted in debug mode, the timer can be configured to either continue to run or to be frozen. This is configured in DEBUGRUN in TIMERn_CTRL. 20.3.5 Interrupts, DMA and PRS Output The timer has 3 different types of output events: •...
- Page 642 Reference Manual TIMER - Timer/Counter 20.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 TIMERn_CTRL Control Register 0x004 TIMERn_CMD Command Register 0x008 TIMERn_STATUS Status Register 0x00C TIMERn_IF Interrupt Flag Register 0x010 TIMERn_IFS Interrupt Flag Set Register...
- Page 643 Reference Manual TIMER - Timer/Counter 20.5 Register Description 20.5.1 TIMERn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RSSCOIST...
- Page 644 Reference Manual TIMER - Timer/Counter Name Reset Access Description Compare/Capture Channel 1 Input TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions X2CNT...
- Page 645 Reference Manual TIMER - Timer/Counter Name Reset Access Description OSMEN One-shot Mode Enable Enable/disable one shot mode. SYNC Timer Start/Stop/Reload Synchronization When this bit is set, the Timer is started/stopped/reloaded by start/stop/reload commands in the other timers Value Description Timer is not started/stopped/reloaded by other timers Timer is started/stopped/reloaded by other timers Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 646 Reference Manual TIMER - Timer/Counter 20.5.3 TIMERn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CCPOL3 CC3 Polarity In Input Capture mode, this bit indicates the polarity of the edge that triggered capture in TIMERn_CC3_CCV.
- Page 647 Reference Manual TIMER - Timer/Counter Name Reset Access Description 23:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICV3 CC3 Input Capture Valid This bit indicates that TIMERn_CC3_CCV contains a valid capture value. These bits are only used in input capture mode and are cleared when CCMODE is written to 0b00 (Off).
- Page 648 Reference Manual TIMER - Timer/Counter Name Reset Access Description CCVBV2 CC2 CCVB Valid This field indicates that the TIMERn_CC2_CCVB registers contain data which have not been written to TIMERn_CC2_CCV. These bits are only used in output compare/PWM mode and are cleared when CCMODE is written to 0b00 (Off).
- Page 649 Reference Manual TIMER - Timer/Counter Name Reset Access Description RUNNING Running Indicates if timer is running or not. 20.5.4 TIMERn_IF - Interrupt Flag Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICBOF3...
- Page 650 Reference Manual TIMER - Timer/Counter 20.5.5 TIMERn_IFS - Interrupt Flag Set Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICBOF3 Set ICBOF3 Interrupt Flag...
- Page 651 Reference Manual TIMER - Timer/Counter 20.5.6 TIMERn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICBOF3 (R)W1...
- Page 652 Reference Manual TIMER - Timer/Counter Name Reset Access Description (R)W1 Clear UF Interrupt Flag Write 1 to clear the UF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.). (R)W1 Clear OF Interrupt Flag Write 1 to clear the OF interrupt flag.
- Page 653 Reference Manual TIMER - Timer/Counter 20.5.7 TIMERn_IEN - Interrupt Enable Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICBOF3 ICBOF3 Interrupt Enable...
- Page 654 Reference Manual TIMER - Timer/Counter 20.5.8 TIMERn_TOP - Counter Top Value Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0 0xFFFF...
- Page 655 Reference Manual TIMER - Timer/Counter 20.5.10 TIMERn_CNT - Counter Value Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0 0x0000...
- Page 656 Reference Manual TIMER - Timer/Counter 20.5.11 TIMERn_LOCK - TIMER Configuration Lock Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0 TIMERLOCKKEY...
- Page 657 Reference Manual TIMER - Timer/Counter 20.5.12 TIMERn_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CDTI2PEN...
- Page 658 Reference Manual TIMER - Timer/Counter 20.5.13 TIMERn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24 CC3LOC...
- Page 659 Reference Manual TIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 23:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16...
- Page 660 Reference Manual TIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
- Page 661 Reference Manual TIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CC0LOC...
- Page 662 Reference Manual TIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
- Page 663 Reference Manual TIMER - Timer/Counter 20.5.14 TIMERn_ROUTELOC2 - I/O Routing Location Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16 CDTI2LOC...
- Page 664 Reference Manual TIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
- Page 665 Reference Manual TIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CDTI0LOC...
- Page 666 Reference Manual TIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
- Page 667 Reference Manual TIMER - Timer/Counter 20.5.15 TIMERn_CCx_CTRL - CC Channel Control Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions FILT Digital Filter...
- Page 668 Reference Manual TIMER - Timer/Counter Name Reset Access Description 25:24 ICEDGE Input Capture Edge Select These bits control which edges the edge detector triggers on. The output is used for input capture and external clock input. Value Mode Description RISING Rising edges detected FALLING Falling edges detected...
- Page 669 Reference Manual TIMER - Timer/Counter Name Reset Access Description NONE No action on counter overflow TOGGLE Toggle output on counter overflow CLEAR Clear output on counter overflow Set output on counter overflow CMOA Compare Match Output Action Select output action on compare match. Value Mode Description...
- Page 670 Reference Manual TIMER - Timer/Counter 20.5.16 TIMERn_CCx_CCV - CC Channel Value Register (Actionable Reads) Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
- Page 671 Reference Manual TIMER - Timer/Counter 20.5.18 TIMERn_CCx_CCVB - CC Channel Buffer Register Offset Bit Position 0x06C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0 CCVB...
- Page 672 Reference Manual TIMER - Timer/Counter 20.5.19 TIMERn_DTCTRL - DTI Control Register Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DTPRSEN DTI PRS Source Enable...
- Page 673 Reference Manual TIMER - Timer/Counter Name Reset Access Description DTCINV DTI Complementary Output Invert Set to invert complementary outputs. DTIPOL DTI Inactive Polarity Set inactive polarity for outputs. DTDAS DTI Automatic Start-up Functionality Configure DTI restart on debugger exit. Value Mode Description NORESTART...
- Page 674 Reference Manual TIMER - Timer/Counter 20.5.20 TIMERn_DTTIME - DTI Time Control Register Offset Bit Position 0x0A4 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16 DTFALLT...
- Page 675 Reference Manual TIMER - Timer/Counter Name Reset Access Description silabs.com | Building a more connected world. Rev. 1.3 | 675...
- Page 676 Reference Manual TIMER - Timer/Counter 20.5.21 TIMERn_DTFC - DTI Fault Configuration Register Offset Bit Position 0x0A8 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DTLOCKUPFEN DTI Lockup Fault Enable...
- Page 677 Reference Manual TIMER - Timer/Counter Name Reset Access Description PRSCH3 PRS Channel 3 selected as fault source 1 PRSCH4 PRS Channel 4 selected as fault source 1 PRSCH5 PRS Channel 5 selected as fault source 1 PRSCH6 PRS Channel 6 selected as fault source 1 PRSCH7 PRS Channel 7 selected as fault source 1 PRSCH8...
- Page 678 Reference Manual TIMER - Timer/Counter 20.5.22 TIMERn_DTOGEN - DTI Output Generation Enable Register Offset Bit Position 0x0AC Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DTOGCDTI2EN...
- Page 679 Reference Manual TIMER - Timer/Counter 20.5.23 TIMERn_DTFAULT - DTI Fault Register Offset Bit Position 0x0B0 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DTLOCKUPF DTI Lockup Fault...
- Page 680 Reference Manual TIMER - Timer/Counter 20.5.24 TIMERn_DTFAULTC - DTI Fault Clear Register Offset Bit Position 0x0B4 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TLOCKUPFC DTI Lockup Fault Clear...
- Page 681 Reference Manual TIMER - Timer/Counter 20.5.25 TIMERn_DTLOCK - DTI Configuration Lock Register Offset Bit Position 0x0B8 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0 LOCKKEY...
- Page 682 Reference Manual LETIMER - Low Energy Timer 21. LETIMER - Low Energy Timer Quick Facts What? The LETIMER is a down-counter that can keep track of time and output configurable waveforms. Running on a 32768 Hz clock, the LETIMER is available in EM0 Active, EM1 Sleep, EM2 DeepSleep, and EM3 Stop.
- Page 683 Reference Manual LETIMER - Low Energy Timer 21.3 Functional Description An overview of the LETIMER module is shown in Figure 21.1 LETIMER Overview on page 683. The LETIMER is a 16-bit down-coun- ter with two compare registers, LETIMERn_COMP0 and LETIMERn_COMP1. The LETIMERn_COMP0 register can optionally act as a top value for the counter.
- Page 684 Reference Manual LETIMER - Low Energy Timer 21.3.3 Top Value If COMP0TOP in LETIMERn_CTRL is set, the value of LETIMERn_COMP0 acts as the top value of the timer, and LETIMERn_COMP0 is loaded into LETIMERn_CNT on timer underflow. If COMP0TOP is cleared to 0, the timer wraps around to 0xFFFF. The underflow interrupt flag UF in LETIMERn_IF is set when the timer reaches zero.
- Page 685 Reference Manual LETIMER - Low Energy Timer 21.3.3.3 Free-Running Mode In free-running mode, the LETIMER acts as a regular timer and the repeat counter is disabled. When started, the timer runs until it is stopped using the STOP command bit in LETIMERn_CMD. A state machine for this mode is shown in Figure 21.2 LETIMER State Machine for Free-running Mode on page 685 Wait for positive clock edge...
- Page 686 Reference Manual LETIMER - Low Energy Timer 21.3.3.4 One-shot Mode The one-shot repeat mode is the most basic repeat mode. In this mode, the repeat register LETIMERn_REP0 is decremented every time the timer underflows, and the timer stops when LETIMERn_REP0 goes from 1 to 0. In this mode, the timer counts down LETI- MERn_REP0 times, i.e.
- Page 687 Reference Manual LETIMER - Low Energy Timer 21.3.3.5 Buffered Mode The Buffered repeat mode allows buffered timer operation. When started, the timer runs LETIMERn_REP0 number of times. If LETI- MERn_REP1 has been written since the last time it was used and it is nonzero, LETIMERn_REP1 is then loaded into LETI- MERn_REP0, and counting continues the new number of times.
- Page 688 Reference Manual LETIMER - Low Energy Timer 21.3.3.6 Double Mode The Double repeat mode works much like the one-shot repeat mode. The difference is that, where the one-shot mode counts as long as LETIMERn_REP0 is larger than 0, the double mode counts as long as either LETIMERn_REP0 or LETIMERn_REP1 is larger than 0.
- Page 689 Reference Manual LETIMER - Low Energy Timer 21.3.3.8 PRS Input Triggers The LETIMER can be configured to start, stop, and/or clear based on PRS inputs. The diagram showing the functions of the PRS input triggers is shown in Figure 21.7 LETIMER PRS Input Triggers on page 689.
- Page 690 Reference Manual LETIMER - Low Energy Timer 21.3.4 Underflow Output Action For each of the repeat registers, an underflow output action can be set. The configured output action is performed every time the coun- ter underflows while the respective repeat register is nonzero. In PWM mode, the output is similarly only changed on COMP1 match if the repeat register is nonzero.
- Page 691 Reference Manual LETIMER - Low Energy Timer Initial configuration COMP0 Int. flags set UFIF UFIF UFIF UFIF UFIF UFIF LFACLK LETIMERn LETn_O0 UFOA0 = 00 LETn_O0 UFOA0 = 01 LETn_O0 UFOA0 = 10 Figure 21.8. LETIMER Simple Waveforms Output For the example in Figure 21.9 LETIMER Repeated Counting on page 691, the One-shot repeat mode has been selected, and LETI- MERn_REP0 has been written to 3.
- Page 692 Reference Manual LETIMER - Low Energy Timer UFOA0 = 10 UFOA1 = 10 REP0 = 2 REP0 = 2 REP1 = 7 REP0 = 3 REP1 = 3 START START START LETn_O0 LETn_O1 Figure 21.10. LETIMER Dual Output 21.3.5 PRS Output The LETIMER outputs can be routed out onto the PRS system.
- Page 693 Reference Manual LETIMER - Low Energy Timer 21.3.6.1 Triggered Output Generation If both LETIMERn_CNT and LETIMERn_REP0 are 0 in buffered mode, and COMP0TOP and BUFTOP in LETIMERn_CTRL are set, the values of LETIMERn_COMP1 and LETIMERn_REP1 are loaded into LETIMERn_CNT and LETIMERn_REP0 respectively when the timer is started.
- Page 694 Reference Manual LETIMER - Low Energy Timer 21.3.6.2 Continuous Output Generation In some scenarios, it might be desired to make LETIMER generate a continuous waveform. Very simple constant waveforms can be generated without the repeat counter as shown in Figure 21.8 LETIMER Simple Waveforms Output on page 691, but to generate changing waveforms, using the repeat counter and buffer registers can prove advantageous.
- Page 695 Reference Manual LETIMER - Low Energy Timer Note: Multiple LETIMER cycles are required to write a value to the LETIMER registers. The example in Figure 21.12 LETIMER Contin- uous Operation on page 694 assumes that writes are done in advance so they arrive in the LETIMER as described in the figure. Figure 21.13 LETIMER LETIMERn_CNT Not Initialized to 0 on page 695 shows an example where the LETIMER is started while LETIMERn_CNT is nonzero.
- Page 696 Reference Manual LETIMER - Low Energy Timer 21.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LETIMERn_CTRL Control Register 0x004 LETIMERn_CMD Command Register 0x008 LETIMERn_STATUS Status Register 0x00C LETIMERn_CNT Counter Value Register 0x010 LETIMERn_COMP0 Compare Value Register 0...
- Page 697 Reference Manual LETIMER - Low Energy Timer 21.5 Register Description 21.5.1 LETIMERn_CTRL - Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name Name Reset Access Description...
- Page 698 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description UFOA1 Underflow Output Action 1 Defines the action on LETn_O1 on a LETIMER underflow. Value Mode Description NONE LETn_O1 is held at its idle value as defined by OPOL1 TOGGLE LETn_O1 is toggled on CNT underflow PULSE...
- Page 699 Reference Manual LETIMER - Low Energy Timer 21.5.2 LETIMERn_CMD - Command Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 700 Reference Manual LETIMER - Low Energy Timer 21.5.4 LETIMERn_CNT - Counter Value Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
- Page 701 Reference Manual LETIMER - Low Energy Timer 21.5.6 LETIMERn_COMP1 - Compare Value Register 1 (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:16...
- Page 702 Reference Manual LETIMER - Low Energy Timer 21.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:8...
- Page 703 Reference Manual LETIMER - Low Energy Timer 21.5.10 LETIMERn_IFS - Interrupt Flag Set Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions REP1...
- Page 704 Reference Manual LETIMER - Low Energy Timer 21.5.11 LETIMERn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions REP1...
- Page 705 Reference Manual LETIMER - Low Energy Timer 21.5.12 LETIMERn_IEN - Interrupt Enable Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions REP1...
- Page 706 Reference Manual LETIMER - Low Energy Timer 21.5.14 LETIMERn_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OUT1PEN...
- Page 707 Reference Manual LETIMER - Low Energy Timer 21.5.15 LETIMERn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
- Page 708 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OUT0LOC...
- Page 709 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
- Page 710 Reference Manual LETIMER - Low Energy Timer 21.5.16 LETIMERn_PRSSEL - PRS Input Select Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 27:26...
- Page 711 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description FALLING Falling edge of selected PRS input can start the LETIMER BOTH Both the rising or falling edge of the selected PRS input can start the LETIMER 17:16 Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 712 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PRSSTARTSEL PRS Start Select Determines which PRS input can start the LETIMER. Value Mode Description...
- Page 713 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22. CRYOTIMER - Ultra Low Energy Timer/Counter Quick Facts What? The CRYOTIMER is a timer capable of providing wakeup events/interrupts after deterministic intervals in all energy modes, including EM4. Why? CRYOTIMER The CRYOTIMER enables the chip to remain in the lowest energy modes for long durations, while keep- ing track of time and being able to wake up at regu- lar intervals, all with an absolute minimum current...
- Page 714 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.3.1 Block Diagram An overview of the CRYOTIMER is shown in Figure 22.1 CRYOTIMER Block Overview on page 714. LFXO CRYOCLK LFRCO Prescaler Counter ULFRCO Edge Detector Interrupt/ Wakeup Event OSCSEL PRESC PERIODSEL Figure 22.1.
- Page 715 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.3.2 Operation The desired low frequency oscillator for the CRYOTIMER operation can be selected by using OSCSEL in CRYOTIMER_CTRL. The selection must be made before enabling the CRYOTIMER, and it must be ensured that the selected oscillator is ready. This can be checked by observing LFXORDY or LFRCORDY (depending upon the oscillator selection) in CMU_STATUS.
- Page 716 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 CRYOTIMER_CTRL Control Register 0x004 CRYOTIMER_PERIODSEL Interrupt Duration 0x008 CRYOTIMER_CNT Counter Value 0x00C CRYOTIMER_EM4WUEN Wake Up Enable 0x010 CRYOTIMER_IF...
- Page 717 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.5 Register Description 22.5.1 CRYOTIMER_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PRESC...
- Page 718 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.5.2 CRYOTIMER_PERIODSEL - Interrupt Duration Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PERIODSEL...
- Page 719 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter Name Reset Access Description Wakeup event after 8M Pre-scaled clock cycles. Wakeup event after 16M Pre-scaled clock cycles. Wakeup event after 32M Pre-scaled clock cycles. Wakeup event after 64M Pre-scaled clock cycles. Wakeup event after 128M Pre-scaled clock cycles.
- Page 720 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.5.5 CRYOTIMER_IF - Interrupt Flag Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PERIOD...
- Page 721 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.5.7 CRYOTIMER_IFC - Interrupt Flag Clear Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PERIOD...
- Page 722 Reference Manual ACMP - Analog Comparator 23. ACMP - Analog Comparator Quick Facts What? The Analog Comparator (ACMP) compares two ana- log signals and returns a digital value telling which is greater. Why? Applications often do not need to know the exact value of an analog signal, only if it has passed a cer- tain threshold.
- Page 723 Reference Manual ACMP - Analog Comparator 23.3 Functional Description An overview of the ACMP is shown in Figure 23.1 ACMP Overview on page 723 POSSEL Warmup Interrupt VADIV Warm-up ACMPACT Counter VBDIV Dedicated APORT0 APORT1 CSRESSEL APORT2 APORT APORT3 CSRESEN APORT4 ACMPOUT INACTVAL...
- Page 724 Reference Manual ACMP - Analog Comparator 23.3.2 Warm-up Time The analog comparator is enabled by setting the EN bit in ACMPn_CTRL. The comparator requires some time to stabilize after it is enabled. This time period is called the warm-up time. The warm-up period is self-timed and will complete within 5µs after EN is set. During warm-up and when the comparator is disabled, the output level of the comparator is set to the value of the INACTVAL bit in ACMPn_CTRL.
- Page 725 Reference Manual ACMP - Analog Comparator 23.3.4 Hysteresis When the hysteresis level is set to a non-zero value, the digital output will not toggle until the positive input voltage is at a voltage equal to the hysteresis level above or below the negative input voltage (see Figure 23.3 Hysteresis on page 725 ).
- Page 726 Reference Manual ACMP - Analog Comparator 23.3.5 Input Pin Considerations For external ACMP inputs routed through the APORT, the maximum supported analog input voltage will be limited to the MIN(V , IOVDD) (where V is selected by the PWRSEL bitfield in ACMPn_CTRL). Note that pins configured as ACMP ACMPVDD ACMPVDD inputs should disable OVT (by setting the corresponding GPIO_Px_OVTDIS bit) to reduce any potential distortion introduced by the...
- Page 727 Reference Manual ACMP - Analog Comparator 23.3.7 Capacitive Sense Mode The analog comparator includes specialized hardware for capacitive sensing of passive push buttons. Such buttons are traces on the PCB laid out in a way that creates a parasitic capacitor between the button and the ground node. Because a human finger will have a small intrinsic capacitance to ground, the capacitance of the button will increase when the button is touched.
- Page 728 Reference Manual ACMP - Analog Comparator Voltage VADIV1 VADIV Divider VADIV0 voltage ACMPn_HYSTERESIS0.VADIV ACMPn_HSYTERESIS1.VADIV time ACMPOUT Figure 23.5. Capacitive Sensing Setup silabs.com | Building a more connected world. Rev. 1.3 | 728...
- Page 729 Reference Manual ACMP - Analog Comparator 23.3.8 Interrupts and PRS Output The analog comparator includes an edge triggered interrupt flag (EDGE in ACMPn_IF). If either IRISE and/or IFALL in ACMPn_CTRL is set, the EDGE interrupt flag will be set on rising and/or falling edge of the comparator output respectively. An interrupt request will be sent if the EDGE interrupt flag in ACMPn_IF is set and enabled through the EDGE bit in ACMPn_IEN.
- Page 730 Reference Manual ACMP - Analog Comparator 23.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ACMPn_CTRL Control Register 0x004 ACMPn_INPUTSEL Input Selection Register 0x008 ACMPn_STATUS Status Register 0x00C ACMPn_IF Interrupt Flag Register 0x010 ACMPn_IFS Interrupt Flag Set Register...
- Page 731 Reference Manual ACMP - Analog Comparator 23.5 Register Description 23.5.1 ACMPn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description FULLBIAS Full Bias Current Set this bit to 1 for full bias current. See the data sheet for details. Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 732 Reference Manual ACMP - Analog Comparator Name Reset Access Description LTVDDDIV2 Setting when the input will always be less than ACMPVDD/2. 17:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ACCURACY ACMP Accuracy Mode Select between low and high accuracy mode of the comparator.
- Page 733 Reference Manual ACMP - Analog Comparator Name Reset Access Description APORTXMASTER- APORT Bus X Master Disable Determines if the ACMP will request the APORT X bus selected by POSSEL or NEGSEL. This bit allows multiple APORT connected devices to monitor the same APORT bus simultaneously by allowing the ACMP to not master the selected bus. When 1, the determination is expected to be from another peripheral, and the ACMP only passively looks at the bus.
- Page 734 Reference Manual ACMP - Analog Comparator 23.5.2 ACMPn_INPUTSEL - Input Selection Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 30:28 CSRESSEL...
- Page 735 Reference Manual ACMP - Analog Comparator Name Reset Access Description VBSEL VB Selection Select the input for the VB Divider Value Mode Description 1V25 1.25V 2.50V 21:16 VASEL 0x00 VA Selection Select the input for the VA Divider Mode Value Description ACMPVDD APORT2YCH0...
- Page 736 Reference Manual ACMP - Analog Comparator Name Reset Access Description APORT1XCH0 0x20 APORT1X Channel 0 APORT1YCH1 0x21 APORT1Y Channel 1 APORT1XCH2 0x22 APORT1X Channel 2 APORT1YCH3 0x23 APORT1Y Channel 3 APORT1XCH4 0x24 APORT1X Channel 4 APORT1YCH5 0x25 APORT1Y Channel 5 .
- Page 737 Reference Manual ACMP - Analog Comparator Name Reset Access Description VBDIV 0xfc Divided VB Voltage VADIV 0xfd Divided VA Voltage 0xfe ACMPVDD as selected via PWRSEL 0xff POSSEL 0x00 Positive Input Select Select positive input. APORT0XCH0 0x00 Dedicated APORT0X Channel 0 APORT0XCH1 0x01 Dedicated APORT0X Channel 1...
- Page 738 Reference Manual ACMP - Analog Comparator Name Reset Access Description APORT3XCH2 0x62 APORT3X Channel 2 APORT3YCH3 0x63 APORT3Y Channel 3 APORT3XCH4 0x64 APORT3X Channel 4 APORT3YCH5 0x65 APORT3Y Channel 5 ..APORT3XCH30 0x7e APORT3X Channel 30 APORT3YCH31...
- Page 739 Reference Manual ACMP - Analog Comparator 23.5.3 ACMPn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTCONFLICT APORT Conflict Output...
- Page 740 Reference Manual ACMP - Analog Comparator 23.5.5 ACMPn_IFS - Interrupt Flag Set Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTCONFLICT...
- Page 741 Reference Manual ACMP - Analog Comparator 23.5.6 ACMPn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTCONFLICT...
- Page 742 Reference Manual ACMP - Analog Comparator 23.5.7 ACMPn_IEN - Interrupt Enable Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTCONFLICT APORTCONFLICT Interrupt Enable...
- Page 743 Reference Manual ACMP - Analog Comparator 23.5.8 ACMPn_APORTREQ - APORT Request Status Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YREQ...
- Page 744 Reference Manual ACMP - Analog Comparator 23.5.9 ACMPn_APORTCONFLICT - APORT Conflict Status Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YCONFLICT 0...
- Page 745 Reference Manual ACMP - Analog Comparator Name Reset Access Description APORT0XCONFLICT 0 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral Reports if the bus connected to APORT0X is is also being requested by another peripheral silabs.com | Building a more connected world.
- Page 746 Reference Manual ACMP - Analog Comparator 23.5.10 ACMPn_HYSTERESIS0 - Hysteresis 0 Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24 DIVVB...
- Page 747 Reference Manual ACMP - Analog Comparator 23.5.11 ACMPn_HYSTERESIS1 - Hysteresis 1 Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24 DIVVB...
- Page 748 Reference Manual ACMP - Analog Comparator 23.5.12 ACMPn_ROUTEPEN - I/O Routing Pine Enable Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OUTPEN...
- Page 749 Reference Manual ACMP - Analog Comparator 23.5.13 ACMPn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OUTLOC...
- Page 750 Reference Manual ACMP - Analog Comparator Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
- Page 751 Reference Manual ADC - Analog to Digital Converter 24. ADC - Analog to Digital Converter Quick Facts What? The ADC is used to convert analog signals into a digital representation and features low-power, auton- omous operation. Why? In many applications there is a need to measure an- alog signals and record them in a digital representa- tion, without exhausting the energy source.
- Page 752 Reference Manual ADC - Analog to Digital Converter 24.2 Features • Programmable resolution (6/8/12-bit) • 13 conversion clock cycles for a 12-bit conversion • Maximum 1 Msps @ 12-bit • Maximum 1.6 Msps @ 6-bit • Configurable acquisition time • Externally controllable conversion start time using PRS in TIMED mode •...
- Page 753 Reference Manual ADC - Analog to Digital Converter • Support for offset and gain calibration • Interrupt generation and/or DMA request when • Programmable number of converted data available in the single FIFO (also generates DMA request) • Programmable number of converted data available in the scan FIFO (also generates DMA request) •...
- Page 754 Reference Manual ADC - Analog to Digital Converter 24.3.1 Clock Selection The ADC logic is partitioned into two clock domains: HFPERCLK and ADC_CLK. The HFPERCLK domain contains the register inter- face logic, APORT request logic and portions of FIFO read logic. The HFPERCLK is the default clock for the ADC peripheral. The rest of the ADC is clocked by the ADC_CLK domain.
- Page 755 Reference Manual ADC - Analog to Digital Converter 24.3.3 ADC Modes The ADC contains two programmable modes: single channel mode and scan mode. Both modes have separate configuration registers and a four-deep FIFO for conversion results. Both modes may be set up to run only once per trigger or to automatically repeat after each operation.
- Page 756 Reference Manual ADC - Analog to Digital Converter 24.3.4 Warm-up Time After power-on, the ADC requires some time for internal bias currents and references to settle prior to starting a conversion. This time period is called the warm-up time. Warm-up timing is performed by hardware. Software must program the number of ADC_CLK cycles required to count at least 1 µs in the TIMEBASE field of the ADCn_CTRL register.
- Page 757 Reference Manual ADC - Analog to Digital Converter ADC standby/ slowacc ADC warm-up ADC conversion WARMUPMODE Conversion trigger Conversion trigger ADC warmed up waiting for trigger Power NORMAL 5 µs Time 1 µs Power KEEPINSTANDBY/ KEEPINSLOWACC 5 µs 5 µs Time 1 µs Power...
- Page 758 Reference Manual ADC - Analog to Digital Converter 24.3.7 Input Selection The ADC samples and converts the analog voltage differential at its positive and negative voltage inputs. The input multiplexers of the ADC can connect these inputs to one of several internal nodes (e.g., temperature sensor) or to external signals via analog ports (APORT0, APORT1, APORT2, APORT3 or APORT4).
- Page 759 Reference Manual ADC - Analog to Digital Converter Multiple peripherals may request the same shared system bus (BUSAX, BUSAY, BUSBX, etc.). When this happens, a conflict status is generated and that bus is kept floating. If this happens with the ADC, the PROGERR field in ADCn_STATUS is set to BUSCONF, and an interrupt may be generated (if enabled).
- Page 760 Reference Manual ADC - Analog to Digital Converter 24.3.7.2 Configuring ADC Inputs in Scan Mode In scan mode, the ADC can sample and convert up to 32 external channels on each conversion trigger. Internal channels are not avail- able in scan mode. The ADC's scanner logic automatically changes the input mux settings between conversions, eliminating the need for firmware intervention.
- Page 761 Reference Manual ADC - Analog to Digital Converter SCANINPUTSEL APORT1CH16TO23 APORT1CH16TO23 APORT4CH8TO15 APORT1CH16TO23 APORT-Channel (Positive) APORT-Channel (Negative) I/O Differential SCANMASK SCANINPUTID Figure 24.7. ADC Differential Scan Mode Example In certain applications it may be desirable to perform differential conversions on several channels against a common voltage. The ADCn_SCANNEGSEL register allows eight of the SCANINPUTIDs to re-map the negative terminal of a differential conversion to a common channel.
- Page 762 Reference Manual ADC - Analog to Digital Converter 24.3.7.3 APORT Conflicts The ADC shares common analog buses connected to its APORTs (1-4) with other analog peripherals (see device-specific data sheet). As the ADC performs single or scan conversions, it requests the shared buses and sends selections for the control switches to connect the desired I/O pins.
- Page 763 Reference Manual ADC - Analog to Digital Converter 24.3.8.1 Basic Full-Scale Voltage Configuration Basic configuration of the VFS (full scale voltage) for the converter is done by programming the REF bitfield in ADCn_SINGLECTRL (for single channel mode) or ADCn_SCANCTRL (for scan mode) to any of the pre-defined options. The list of available pre-defined VFS options is: •...
- Page 764 Reference Manual ADC - Analog to Digital Converter 24.3.8.2 Advanced Full-Scale Voltage Configuration For most applications, the pre-defined VFS options described in 24.3.8.1 Basic Full-Scale Voltage Configuration are suitable. Advanced VFS configurations are also possible by programming the REF bitfield in ADCn_SINGLECTRL or ADCn_SCANCTRL to the CONF op- tion.
- Page 765 Reference Manual ADC - Analog to Digital Converter The maximum and minimum input voltage which the ADC can recognize at any external pin is limited to the minimum of the V IOVDD supply voltages (where V is VDDX_ANA, as described in 24.3.5 Power Supply).
- Page 766 Reference Manual ADC - Analog to Digital Converter 24.3.10 Feature Set The following sections explain different ADC features. 24.3.10.1 Conversion Tailgating Scan conversions have priority over single channel conversions. This means that if scan and single triggers are received simultaneous- ly, or even if the scan is received later when ADC is being warmed up for performing a single conversion, the scan conversion will have priority and will be done before the single conversion.
- Page 767 Reference Manual ADC - Analog to Digital Converter 24.3.10.3 Conversion Trigger The conversion modes can be activated by writing a 1 to the SINGLESTART or SCANSTART bit in the ADCn_CMD register. The con- versions can be stopped by writing a 1 to the SINGLESTOP or SCANSTOP bit in the ADCn_CMD register. A START command will have priority over a STOP command.
- Page 768 Reference Manual ADC - Analog to Digital Converter running, then the CMU automatically turns it on when the ADC sends a clock request. In such a case, it takes (7 ADC_CLK cycles + the oscillator startup time) for the ADC_CLK to start. The oscillator startup time can be found in the device data sheet. When triggering repeat mode using PRS and then stopping the triggered mode using STOP command, ensure that the PRS pulse used to generate the repeat mode has gone low by the time the STOP command is issued.
- Page 769 Reference Manual ADC - Analog to Digital Converter 24.3.10.6 Oversampling To achieve higher accuracy, hardware oversampling can be enabled individually for each mode (Set RES in ADCn_SINGLECTRL/ ADCn_SCANCTRL to 0x3). The oversampling rate (OVSRSEL in ADCn_CTRL) can be set to any integer power of 2 from 2 to 4096 and the configuration is shared between the scan and single channel mode (OVSRSEL field in ADCn_CTRL).
- Page 770 Reference Manual ADC - Analog to Digital Converter 24.3.10.8 Channel Connection The inputs are connected to the analog ADC at the beginning of the acquisition phase and are disconnected at the end of the acquisi- tion phase. The time when the APORT switches are closed (for the next input to be converted) can be controlled by the CHCONMODE bitfield in the ADCn_CTRL register.
- Page 771 Reference Manual ADC - Analog to Digital Converter 24.3.11 Interrupts, PRS Output The single and scan modes have separate SINGLE and SCAN interrupt flags indicating whether corresponding FIFO contains DVL # of valid conversion data. Corresponding interrupt enable bit has to be set in ADCn_IEN in order to generate interrupts. For these inter- rupts, there is no software clear mechanism by writing to ADCn_IFC.
- Page 772 Reference Manual ADC - Analog to Digital Converter 24.3.13.2 Gain Calibration Offset calibration must be performed prior to gain calibration. The Gain Calibration is done in the following manner: 1. Select an external ADC channel for single channel conversion (a differential channel can also be used). 2.
- Page 773 Reference Manual ADC - Analog to Digital Converter 24.3.15 ASYNC ADC_CLK Usage Restrictions and Benefits When the ADC_CLK is chosen to come from ASYNCCLK, (ADCCLKMODE is set to ASYNC), the ADC_CLK and the ADC peripheral clock are considered asynchronous and this adds some restrictions: •...
- Page 774 Reference Manual ADC - Analog to Digital Converter 24.3.17 ADC Programming Model The ADC configuration registers are considered static and can only be updated when (1) ADC is in SYNC mode and (2) ADC is idle. ADC is considered busy when it is doing conversions (either the SINGLEACT or SCANACT status flag is high) or when it is warmed up (one of the following status flags is high: WARM, SINGLEREFWARM, SCANREFWARM).
- Page 775 Reference Manual ADC - Analog to Digital Converter 24.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ADCn_CTRL Control Register 0x008 ADCn_CMD Command Register 0x00C ADCn_STATUS Status Register 0x010 ADCn_SINGLECTRL Single Channel Control Register 0x014 ADCn_SINGLECTRLX...
- Page 776 Reference Manual ADC - Analog to Digital Converter 24.5 Register Description 24.5.1 ADCn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CHCONMODE...
- Page 777 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 22:16 TIMEBASE 0x1F 1us Time Base Sets the time base used for the ADC warm up sequence based on ADC_CLK. The TIMEBASE field should be set equal to produce timing of 1us or greater.
- Page 778 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description SCANDMAWU SCANFIFO DMA Wakeup Selects whether to wakeup the DMA controller when in EM2 and DVL is reached in SCANFIFO Value Description While in EM2, the DMA controller will not get requests about DVL reached in SCANFIFO DMA is available in EM2 for processing SCANFIFO DVL request SINGLEDMAWU...
- Page 779 Reference Manual ADC - Analog to Digital Converter 24.5.2 ADCn_CMD - Command Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SCANSTOP...
- Page 780 Reference Manual ADC - Analog to Digital Converter 24.5.3 ADCn_STATUS - Status Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SCANDV...
- Page 781 Reference Manual ADC - Analog to Digital Converter 24.5.4 ADCn_SINGLECTRL - Single Channel Control Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description CMPEN Compare Logic Enable for Single Channel Enable/disable Compare Logic Value Description Disable Compare Logic. Enable Compare Logic.
- Page 782 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 23:16 NEGSEL 0xFF Single Channel Negative Input Selection Selects the negative input to the ADC for Single Channel Differential mode (in case of singled ended mode, the negative input is grounded).
- Page 783 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description ..APORT0XCH15 Select APORT0XCH15 APORT0YCH0 Select APORT0YCH0 APORT0YCH1 Select APORT0YCH1 APORT0YCH15 Select APORT0YCH15 APORT1XCH0 Select APORT1XCH0 APORT1YCH1 Select APORT1YCH1 ..APORT1YCH31 Select APORT1YCH31 APORT2YCH0 Select APORT2YCH0 APORT2XCH1 Select APORT2XCH1 ..
- Page 784 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description SUBLSB SUBLSB measurement enabled. OPA3 OPA3 output. Not Applicable if no OPA is available. Single Channel Reference Selection Select reference to ADC single channel mode. Value Mode Description 1V25 VFS = 1.25V with internal VBGR reference VFS = 2.5V with internal VBGR reference...
- Page 785 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description ADC will perform one conversion per trigger in single channel mode. ADC will repeat conversions in single channel mode continuously until SINGLESTOP is written. silabs.com | Building a more connected world. Rev.
- Page 786 Reference Manual ADC - Analog to Digital Converter 24.5.5 ADCn_SINGLECTRLX - Single Channel Control Register Continued Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CONVSTARTDE-...
- Page 787 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description PRSCH6 PRS ch 6 triggers single channel PRSCH7 PRS ch 7 triggers single channel PRSCH8 PRS ch 8 triggers single channel PRSCH9 PRS ch 9 triggers single channel PRSCH10 PRS ch 10 triggers single channel PRSCH11...
- Page 788 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description VREFSEL Single Channel Reference Selection Select reference VREF to ADC single channel mode. Value Mode Description VBGR Internal 0.83V Bandgap reference VDDXWATT Scaled AVDD: AVDD*(the VREF attenuation factor) VREFPWATT Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenua- tion factor)
- Page 789 Reference Manual ADC - Analog to Digital Converter 24.5.6 ADCn_SCANCTRL - Scan Control Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description CMPEN Compare Logic Enable for Scan Enable/disable Compare Logic Value Description Disable Compare Logic. Enable Compare Logic. Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 790 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 23:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions Scan Sequence Reference Selection Select reference to ADC scan sequence. Value Mode Description...
- Page 791 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description Scan conversion mode repeats continuously until SCANSTOP is writ- ten. silabs.com | Building a more connected world. Rev. 1.3 | 791...
- Page 792 Reference Manual ADC - Analog to Digital Converter 24.5.7 ADCn_SCANCTRLX - Scan Control Register Continued Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CONVSTARTDE-...
- Page 793 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description PRSCH7 PRS ch 7 triggers scan sequence PRSCH8 PRS ch 8 triggers scan sequence PRSCH9 PRS ch 9 triggers scan sequence PRSCH10 PRS ch 10 triggers scan sequence PRSCH11 PRS ch 11 triggers scan sequence PRSMODE...
- Page 794 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description Value Mode Description VBGR Internal 0.83V Bandgap reference VDDXWATT Scaled AVDD: AVDD*(the VREF attenuation factor) VREFPWATT Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenua- tion factor) VREFP Raw single ended external Vref: ADCn_EXTP VREFPNWATT Scaled differential external Vref from : (ADCn_EXTP- ADCn_EXTN)*(the VREF attenuation factor)
- Page 795 Reference Manual ADC - Analog to Digital Converter 24.5.8 ADCn_SCANMASK - Scan Sequence Input Mask Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:0 SCANINPUTEN 0x00000000 Scan Sequence Input Mask Set one or more bits in this mask to select which inputs are included in scan sequence in either single ended or differential mode.
- Page 796 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description INPUT1INPUT2 xxxxxxxxxxxxxxxxxxxxx (Positive input: ADCn_INPUT1 Negative input: ADCn_INPUT2) inclu- xxxxxxxxx1x ded in mask INPUT2INPUT2NEG- xxxxxxxxxxxxxxxxxxxxx (Positive input: ADCn_INPUT2 Negative input: chosen by IN- xxxxxxxx1xx PUT2NEGSEL) included in mask INPUT3INPUT4 xxxxxxxxxxxxxxxxxxxxx (Positive input: ADCn_INPUT3 Negative input: ADCn_INPUT4) inclu-...
- Page 797 Reference Manual ADC - Analog to Digital Converter 24.5.9 ADCn_SCANINPUTSEL - Input Selection Register for Scan Mode Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 28:24...
- Page 798 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description APORT1CH8TO15 Select APORT1's CH8-CH15 as ADCn_INPUT16-ADCn_INPUT23 APORT1CH16TO23 Select APORT1's CH16-CH23 as ADCn_INPUT16-ADCn_INPUT23 APORT1CH24TO31 Select APORT1's CH24-CH31 as ADCn_INPUT16-ADCn_INPUT23 APORT2CH0TO7 Select APORT2's CH0-CH7 as ADCn_INPUT16-ADCn_INPUT23 ..APORT3CH0TO7 Select APORT3's CH0-CH7 as ADCn_INPUT16-ADCn_INPUT23 ..
- Page 799 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description APORT1CH24TO31 Select APORT1's CH24-CH31 as ADCn_INPUT0-ADCn_INPUT7 APORT2CH0TO7 Select APORT2's CH0-CH7 as ADCn_INPUT0-ADCn_INPUT7 ..APORT3CH0TO7 Select APORT3's CH0-CH7 as ADCn_INPUT0-ADCn_INPUT7 ..APORT4CH0TO7 Select APORT4's CH0-CH7 as ADCn_INPUT0-ADCn_INPUT7 ..silabs.com | Building a more connected world. Rev.
- Page 800 Reference Manual ADC - Analog to Digital Converter 24.5.10 ADCn_SCANNEGSEL - Negative Input Select Register for Scan Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:14...
- Page 801 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description INPUT9NEGSEL Negative Input Select Register for ADCn_INPUT9 in Differential Scan Mode Selects negative channel Value Mode Description INPUT8 Selects ADCn_INPUT8 as negative channel input INPUT10 Selects ADCn_INPUT10 as negative channel input INPUT12 Selects ADCn_INPUT12 as negative channel input INPUT14...
- Page 802 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description INPUT1 Selects ADCn_INPUT1 as negative channel input INPUT3 Selects ADCn_INPUT3 as negative channel input INPUT5 Selects ADCn_INPUT5 as negative channel input INPUT7 Selects ADCn_INPUT7 as negative channel input 24.5.11 ADCn_CMPTHR - Compare Threshold Register Offset Bit Position...
- Page 803 Reference Manual ADC - Analog to Digital Converter 24.5.12 ADCn_BIASPROG - Bias Programming Register for Various Analog Blocks Used in ADC Operation Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions GPBIASACC...
- Page 804 Reference Manual ADC - Analog to Digital Converter 24.5.13 ADCn_CAL - Calibration Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description CALEN Calibration Mode is Enabled When enabled, the adc performs conversion and sends raw data to the ADC fifos. This can also be used to debug the adc data conversion 30:24 SCANGAIN...
- Page 805 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description SINGLEOFFSET Single Mode Offset Calibration Value for Differential or Positive Single-ended Mode This register contains the offset calibration value used with single conversions for differential or positive single-ended mode. This field is set to the production offset calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device.
- Page 806 Reference Manual ADC - Analog to Digital Converter 24.5.14 ADCn_IF - Interrupt Flag Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PROGERR...
- Page 807 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description SINGLE Single Conversion Complete Interrupt Flag Indicates (DVL+1) number of single channel results are available in the Single FIFO. 24.5.15 ADCn_IFS - Interrupt Flag Set Register Offset Bit Position 0x03C Reset Access...
- Page 808 Reference Manual ADC - Analog to Digital Converter 24.5.16 ADCn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PROGERR...
- Page 809 Reference Manual ADC - Analog to Digital Converter 24.5.17 ADCn_IEN - Interrupt Enable Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PROGERR...
- Page 810 Reference Manual ADC - Analog to Digital Converter 24.5.18 ADCn_SINGLEDATA - Single Conversion Result Data (Actionable Reads) Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:0 DATA 0x00000000 Single Conversion Result Data This register holds the results from the last single channel mode conversion. Reading this field pops one entry from the SINGLE FIFO.
- Page 811 Reference Manual ADC - Analog to Digital Converter 24.5.20 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:0 DATAP 0x00000000 Single Conversion Result Data Peek The register holds the results from the last single channel mode conversion. Reading this field will not pop an entry from the SINGLE FIFO.
- Page 812 Reference Manual ADC - Analog to Digital Converter 24.5.22 ADCn_SCANDATAX - Scan Sequence Result Data + Data Source Register (Actionable Reads) Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 20:16...
- Page 813 Reference Manual ADC - Analog to Digital Converter 24.5.24 ADCn_APORTREQ - APORT Request Status Register Offset Bit Position 0x07C Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YREQ...
- Page 814 Reference Manual ADC - Analog to Digital Converter 24.5.25 ADCn_APORTCONFLICT - APORT Conflict Status Register Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YCONFLICT 0...
- Page 815 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description APORT0XCONFLICT 0 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral Reports if the bus connected to APORT0X is is also being requested by another peripheral 24.5.26 ADCn_SINGLEFIFOCOUNT - Single FIFO Count Register Offset Bit Position...
- Page 816 Reference Manual ADC - Analog to Digital Converter 24.5.28 ADCn_SINGLEFIFOCLEAR - Single FIFO Clear Register Offset Bit Position 0x08C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SINGLEFIFOCLEAR...
- Page 817 Reference Manual IDAC - Current Digital to Analog Converter 25. IDAC - Current Digital to Analog Converter Quick Facts What? The IDAC can sink or source a configurable con- stant current. Why? The IDAC can be used to bias external circuits or (in conjunction with the ADC) measure capacitance by IDAC injecting a controlled current into a component.
- Page 818 Reference Manual IDAC - Current Digital to Analog Converter 25.3 Functional Description An overview of the IDAC module is shown in Figure 25.1 IDAC Overview on page 818. The IDAC is designed to source or sink a programmable current which can be controlled by setting the range and the step in the RANGESEL and STEPSEL bitfields in IDAC_CURRPROG register.
- Page 819 Reference Manual IDAC - Current Digital to Analog Converter 25.3.4 APORT Configuration The IDAC APORT outputs can be routed to pins through the APORT system. Note that the IDAC has only two local APORT interfaces APORT1X and APORT1Y, which are connected to the APORT BUSCX and BUSCY, respectively. The pins are selected by requesting an APORT channel in APORTOUTSEL in IDAC_CTRL.
- Page 820 Reference Manual IDAC - Current Digital to Analog Converter 25.3.9 PRS Triggered Charge Injection The amount of charge sourced or sunk by the IDAC can be controlled by the PRS (e.g., using a timer as producer) via the output switch. Figure 25.2 IDAC Charge Injection Example on page 820 shows a case where the IDAC is configured to periodically supply charge using the PRS.
- Page 821 Reference Manual IDAC - Current Digital to Analog Converter 25.5 Register Description 25.5.1 IDAC_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 23:20...
- Page 822 Reference Manual IDAC - Current Digital to Analog Converter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTMASTERDIS APORT Bus Master Disable Determines if the IDAC will request the APORT bus selected by APORTOUTSEL. This bit allows multiple APORT connec- ted devices to monitor the same APORT bus simultaneously by allowing the IDAC to not master the selected bus.
- Page 823 Reference Manual IDAC - Current Digital to Analog Converter 25.5.2 IDAC_CURPROG - Current Programming Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 23:16...
- Page 824 Reference Manual IDAC - Current Digital to Analog Converter 25.5.3 IDAC_DUTYCONFIG - Duty Cycle Configuration Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM2DUTYCYCLE-...
- Page 825 Reference Manual IDAC - Current Digital to Analog Converter 25.5.5 IDAC_IF - Interrupt Flag Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTCONFLICT...
- Page 826 Reference Manual IDAC - Current Digital to Analog Converter 25.5.7 IDAC_IFC - Interrupt Flag Clear Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTCONFLICT...
- Page 827 Reference Manual IDAC - Current Digital to Analog Converter 25.5.9 IDAC_APORTREQ - APORT Request Status Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT1YREQ...
- Page 828 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 26. GPCRC - General Purpose Cyclic Redundancy Check Quick Facts What? The GPCRC is an error-detecting module commonly used in digital networks and storage systems to de- tect accidental changes to data. Why? The GPCRC module can detect errors in data, giv- ing a higher system reliability and robustness.
- Page 829 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 26.3 Functional Description An overview of the GPCRC module is shown in Figure 26.1 GPCRC Overview on page 829. GPCRC Module DATAREV bit reversal DATA byte reversal DATABYTEREV INPUTDATA byte byte-level reorder Hardware CRC reversal...
- Page 830 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 26.3.1 Polynomial Specification POLYSEL in GPCRC_CTRL selects between 32-bit and 16-bit polynomial functions. When a 32-bit polynomial is selected, the fixed IEEE 802.3 polynomial(0x04C11DB7) is used. When a 16-bit polynomial is selected, any valid polynomial can be defined by the user in GPCRC_POLY.
- Page 831 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 26.3.5 Byte-Level Bit Reversal and Byte Reordering The byte-level bit reversal and byte reordering operations occur before the data is used in the CRC calculation. Byte reordering can occur on words or half words. The hardware ignores the BYTEREVERSE field with any byte writes or operations with byte mode ena- bled (BYTEMODE = 1), but the bit reversal settings (BITREVERSE) are still applied to the byte.
- Page 832 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Byte 3 Byte 2 Byte 1 Byte 0 Input data is big endian, MSB- first BYTEREVERSE = 1 8'h00 8'h00 Byte 0 Byte 1 BITREVERSE = 1 8'h00 8'h00 Byte 0 Byte 1 Data is now 16-bit little endian, LSB-first for CRC...
- Page 833 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Input Width(bits) BYTEREVERSE Setting BITREVERSE Setting Input to CRC Calculation Note: 1. X indicates a "don't care". 2. Bn is the byte field within the word. 3. 'Bn is the bit-reversed byte field within the word. 26.4 Register Map The offset register address is relative to the registers base address.
- Page 834 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 26.5 Register Description 26.5.1 GPCRC_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions AUTOINIT...
- Page 835 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CRC Functionality Enable Enables CRC functionality. Value Mode Description DISABLE Disable CRC function.
- Page 836 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 26.5.4 GPCRC_POLY - CRC Polynomial Value Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
- Page 837 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 26.5.6 GPCRC_INPUTDATAHWORD - Input 16-bit Data Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
- Page 838 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 26.5.8 GPCRC_DATA - CRC Data Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:0 DATA 0x00000000 CRC Data Register CRC Data Register, read only. The CRC data register may still be indirectly written from software, by writing the INIT regis- ter and then issue an INITIALIZE command.
- Page 839 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 26.5.10 GPCRC_DATABYTEREV - CRC Data Byte Reverse Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:0 DATABYTEREV 0x00000000 Data Byte Reverse Value Byte reversed version of CRC Data register. When a 32-bit CRC polynomial is selected, the bytes are swizzled to {B0, B1, B2, B3}.
- Page 840 Reference Manual CRYPTO - Crypto Accelerator 27. CRYPTO - Crypto Accelerator Quick Facts What? A fast and energy efficient autonomous hardware accelerator for AES encryption and decryption with 128- or 256-bit keys, ECC over prime and binary Galois finite fields, SHA-1, SHA-224 and SHA-256. Why? How are you? &G#%5...
- Page 841 Reference Manual CRYPTO - Crypto Accelerator 27.2 Features • Efficient AES core • Encryption/decryption using 128-bit key (54 clock cycles) or 256-bit key (75 clock cycles) • Key buffer • Supports autonomous cipher block modes (e.g. ECB, CTR, CBC, PCBC, CFB, CBC-MAC, GMAC, CCM, CCM* and GCM) across multiple blocks •...
- Page 842 Reference Manual CRYPTO - Crypto Accelerator 27.4 Functional Description A block diagram of the CRYPTO module is shown in Figure 27.1 CRYPTO Overview on page 842. AHB bus Sequencer Control DATA TRANSFER DDATA0[255:0] DDATA0[255:0] QDATA0[511:0] KEY[255:0] DDATA1[255:0] DATA1[127:0] DATA0[127:0] DDATA2[255:0] QDATA1[511:0] DATA3[127:0] DATA2[127:0]...
- Page 843 Reference Manual CRYPTO - Crypto Accelerator 27.4.1 Data and Key Registers The CRYPTO module contains five 256-bit registers. Accelerators are implemented through instructions operating on these registers, either by copying data between registers and external components like the BUFC or through DMA, or by executing instructions on the registers.
- Page 844 Reference Manual CRYPTO - Crypto Accelerator Shift on write and read DATA0 (128 bit) CRYPTO_DATA0 CRYPTO_DATA0XOR Write data Read data CRYPTO_DATA0BYTE CRYPTO_DATA0XORBYTE DATA1 (128 bit) CRYPTO_DATA1 Write data Read data CRYPTO_DATA1BYTE DATA2 (128 bit) CRYPTO_DATA2 Write data Read data DATA3 (128 bit) CRYPTO_DATA3 Write data Read data...
- Page 845 Reference Manual CRYPTO - Crypto Accelerator 27.4.1.2 DDATA0 and DDATA1 Quick Observation DDATA0LSBS in CRYPTO_DSTATUS shows the 4 least significant bits in DDATA0. DDATA0MSBS in CRYPTO_DSTATUS shows the 4 most significant bits of DDATA0, while DDATA1MSB in CRYPTO_DSTATUS shows the msb of DDATA1. These observation bitfields are useful for determining the sign of the value in the data registers without having to read out the full register data register values The 4 bits observed by DDATA0MSBS will change depending on RESULTWIDTH in CRYPTO_WAC.
- Page 846 Reference Manual CRYPTO - Crypto Accelerator 27.4.2.1 Sequences For executing a set of instructions, it is more efficient to load them into the CRYPTO module and run them as a sequence. This is done by writing the instructions into CRYPTO_SEQ0-CRYPTO_SEQ4, and marking the end of the instruction sequence with either an END or an EXEC instruction.
- Page 847 Reference Manual CRYPTO - Crypto Accelerator 27.4.2.2 Available Instructions The available ALU instructions are listed in Table 27.1 ALU Instructions on page 847, data transfer instructions are listed in Table 27.3 Transfer Instructions on page 848, conditional instructions are listed in Table 27.4 Conditional Instructions on page 849 special instructions are listed in Table 27.5 Special Instructions on page...
- Page 848 Reference Manual CRYPTO - Crypto Accelerator Instruction Description Constraints/Notes SHRB DDATA0 = V0 >> 1 | V0[0] << resultwidth-1 SHR1 DDATA0 = V0 >> 1 | 1 << resultwidth-1 SHRA DDATA0 = V0 >> 1 | V0[resultwidth-1] << result- width-1 DDATA0 = 0 DDATA0 = V0 ^ V1 If V0 != DDATA0, then V1 != DDATA0...
- Page 849 Reference Manual CRYPTO - Crypto Accelerator Instruction Operation Constraints/Notes SELDATAxDDATAy Use DATAx as V0, DDATAy as V1 x = 0,1,2; y = 0,1,2,3,4 SELDDATAxDATAy Use DDATAx as V0, DATAy as V1 x = 0,1,2,3,4; y = 0,1 SELDATAxDATAy Use DATAx as V0, DATAy as V1 x = 0,1,2;...
- Page 850 Reference Manual CRYPTO - Crypto Accelerator 27.4.2.6 Carry The carry output from most instructions can be observed through the CARRY bit in CRYPTO_DSTATUS. Shift-instructions set CARRY to the value that is shifted out of the register, addition and multiplication set it on register overflow, and subtraction sets it on borrow, e.g.
- Page 851 Reference Manual CRYPTO - Crypto Accelerator 27.4.4 AES The AES core operates on data in the 128-bit register DATA0 using the either a 128-bit or 256-bit key from the KEY register. The key width is specified by AES256 in CRYPTO_CTRL. AES operations are implemented as the AESENC and AESDEC instructions, for AES encryption and AES decryption respectively.
- Page 852 Reference Manual CRYPTO - Crypto Accelerator DATA KEY/KEYBUF [7:0] [15:8] [23:16] [31:24] Figure 27.5. CRYPTO Data and Key Orientation as Defined in the Advanced Encryption Standard silabs.com | Building a more connected world. Rev. 1.3 | 852...
- Page 853 Reference Manual CRYPTO - Crypto Accelerator 27.4.5 SHA The CRYPTO SHA instruction implements SHA-1 with a 160-bit digest or SHA-2 with a 224-bit digest (SHA-224) or 256-bit digest (SHA-256). Depending on SHAMODE in CRYPTO_CTRL, SHA-1, SHA-224 or SHA-256 will be run on the data in QDATA1, and the result will be put on DDATA0.
- Page 854 Reference Manual CRYPTO - Crypto Accelerator 27.4.7 GCM and GMAC CRYPTO implements support for Galois/Counter Mode (GCM), and also Galois Message Authentication Code (GMAC), by providing AES instructions and allowing multiplication on the field GF(2^128) defined by the polynomial x^128 + x^7 + x^2 + x + 1. Note: BBSWAP128 needs to be applied to both operands and the result of the MMUL instruction when using it for GCM and GMAC Efficient sequencer programs can be set up to perform GCM authentication and encryption/decryption on data from either BUFC, DMA, or CPU.
- Page 855 Reference Manual CRYPTO - Crypto Accelerator 27.4.8.1 DMA Initial Bytes Skip The DMA must be configured to use 32-bit transfer size. This normally would imply that the source data must be aligned to a 4 byte address boundary. However, it is possible to skip the initial bytes (1 to 3) when using DMA to write to DATA0 or DATA1 through a CRYPTO instruction operation.
- Page 856 Reference Manual CRYPTO - Crypto Accelerator 27.4.9 BUFC Data Transfer To allow automatic encryption/decryption or other operations on radio data, CRYPTO has instructions for moving data from and to BUFC, the Buffer Controller. Both DATA0 and DATA1 can be loaded with data from the buffer selected by READBUFSEL (CRYP- TO_CTRL register) as shown in Figure 27.6 CRYPTO BUFC Data Transfer on page 856.
- Page 857 Reference Manual CRYPTO - Crypto Accelerator 27.4.10 Debugging There are multiple ways of debugging CRYPTO sequences. The most straight-forward way is to write individual instructions to INSTR in CRYPTO_CMD. An instruction can be written, and data can be read out and examined before running another instruction. Running individual instructions to debug a program falls short when working with repeated sequences.
- Page 858 Reference Manual CRYPTO - Crypto Accelerator 27.4.11.1 CBC Encryption In CBC encryption, the cipher input is the PlainText XOR'ed with the previous cipher output (an initialization vector IV is used during the first block). This mode is easily implemented using the CRYPTO instruction sequence BUFTODATA0XOR, AESENC then DATA0TO- BUF.
- Page 859 Reference Manual CRYPTO - Crypto Accelerator 27.4.11.2 CBC Decryption In CBC decryption, CipherText (C ) is used as input to the Cipher Core. The output from the Cipher Core is XOR'ed with the CipherText from the previous block C to form the PlainText P (an initialization vector IV is used as C during the first block).
- Page 860 Reference Manual CRYPTO - Crypto Accelerator 27.5 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 CRYPTO_CTRL Control Register 0x004 CRYPTO_WAC Wide Arithmetic Configuration 0x008 CRYPTO_CMD Command Register 0x010 CRYPTO_STATUS Status Register 0x014 CRYPTO_DSTATUS Data Status Register...
- Page 861 Reference Manual CRYPTO - Crypto Accelerator Offset Name Type Description 0x110 CRYPTO_DDATA4 RWH(nB)(a) DDATA4 Register Access 0x130 CRYPTO_DDATA0BIG RWH(nB)(a) DDATA0 Register Big Endian Access 0x140 CRYPTO_DDATA0BYTE RWH(nB)(a) DDATA0 Register Byte Access 0x144 CRYPTO_DDATA1BYTE RWH(nB)(a) DDATA1 Register Byte Access 0x148 CRYPTO_DDATA0BYTE32 RWH(nB) DDATA0 Register Byte 32 Access 0x180...
- Page 862 Reference Manual CRYPTO - Crypto Accelerator 27.6 Register Description 27.6.1 CRYPTO_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description COMBDMA0WEREQ 0 Combined Data0 Write DMA Request When cleared, the DATA0WR and DATA0XORWR operate independently. When set, DATA0XORWR requests are also given through DATA0WR Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 863 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description LENLIMITBYTE Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing.
- Page 864 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SHA Mode Select SHA-1 or SHA-2 mode. Value Mode Description SHA1 SHA-1 mode SHA2 SHA-2 mode (SHA-224 or SHA-256) KEYBUFDIS...
- Page 865 Reference Manual CRYPTO - Crypto Accelerator 27.6.2 CRYPTO_WAC - Wide Arithmetic Configuration Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 11:10 RESULTWIDTH...
- Page 866 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description BIN128 Generic modulus. p = 2^128 ECCBIN233P Modulus for B-233 and K-233 ECC curves. p(t) = t^233 + t^74 + 1 ECCBIN163P Modulus for B-163 and K-163 ECC curves. p(t) = t^163 + t^7 + t^6 + t^3 + 1 GCMBIN128 Modulus for GCM.
- Page 867 Reference Manual CRYPTO - Crypto Accelerator 27.6.3 CRYPTO_CMD - Command Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SEQSTEP Sequence Step...
- Page 868 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description Multiply MULC See detailed instruction listing MMUL Modular multiplication MULO See detailed instruction listing Shift left SHLC Shift left with carry (Rotate left) SHLB See detailed instruction listing SHL1 See detailed instruction listing Shift right SHRC Shift right with carry (Rotate right)
- Page 869 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description DATA2TODATA0XOR- DATA0[len-1:0] = DATA0[len-1:0] ^ DATA2[len-1:0] DATA2TODATA1 DATA1 = DATA2 DATA2TODATA3 DATA3 = DATA2 DATA3TODATA0 DATA0 = DATA3 DATA3TODATA0XOR DATA0 = DATA0 ^ DATA3 DATA3TODATA0XOR- DATA0[len-1:0] = DATA0[len-1:0] ^ DATA3[len-1:0] DATA3TODATA1 DATA1 = DATA3 DATA3TODATA2...
- Page 870 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description DDATA2TODDATA3 DDATA3 = DDATA2 DDATA2TODDATA4 DDATA4 = DDATA2 DDATA2LTODATA2 DATA2 = DDATA2[127:0] DDATA3TODDATA0 DDATA0 = DDATA3 DDATA3TODDATA1 DDATA1 = DDATA3 DDATA3TODDATA2 DDATA2 = DDATA3 DDATA3TODDATA4 DDATA4 = DDATA3 DDATA3LTODATA0 DATA0 = DDATA3[127:0] DDATA3HTODATA1 DATA1 = DDATA3[255:128] DDATA4TODDATA0...
- Page 871 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description SELDATA1DDATA1 Use DATA1 as V0, DDATA1 as V1 SELDATA2DDATA1 Use DATA2 as V0, DDATA2 as V1 SELDDATA0DDATA2 Use DDATA0 as V0, DDATA2 as V1 SELDDATA1DDATA2 Use DDATA1 as V0, DDATA2 as V1 SELDDATA2DDATA2 Use DDATA2 as V0, DDATA2 as V1 SELDDATA3DDATA2...
- Page 872 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description SELDDATA3DATA1 Use DDATA3 as V0, DATA1 as V1 SELDDATA4DATA1 Use DDATA4 as V0, DATA1 as V1 SELDATA0DATA1 Use DATA0 as V0, DATA1 as V1 SELDATA1DATA1 Use DATA1 as V0, DATA1 as V1 SELDATA2DATA1 Use DATA2 as V0, DATA1 as V1 EXECIFA...
- Page 873 Reference Manual CRYPTO - Crypto Accelerator 27.6.5 CRYPTO_DSTATUS - Data Status Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CARRY Carry From Arithmetic Operation...
- Page 874 Reference Manual CRYPTO - Crypto Accelerator 27.6.6 CRYPTO_CSTATUS - Control Status Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 24:20 SEQIP...
- Page 875 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description Selected ALU Operand 0 Selectable operand for arithmetic operations Value Mode Description DDATA0 DDATA1 DDATA2 DDATA3 DDATA4 DATA0 DATA1 DATA2 27.6.7 CRYPTO_KEY - KEY Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x020...
- Page 876 Reference Manual CRYPTO - Crypto Accelerator 27.6.8 CRYPTO_KEYBUF - KEY Buffer Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:0 KEYBUF 0xXXXXXXX Key Buffer Access Access to KEYBUF. 4x32bits (8x32bits if AES256 in CRYPTO_CTRL is set) read/write accesses are required to fully read/ write KEYBUF silabs.com | Building a more connected world.
- Page 877 Reference Manual CRYPTO - Crypto Accelerator 27.6.9 CRYPTO_SEQCTRL - Sequence Control Offset Bit Position 0x030 Reset Access Name Name Reset Access Description HALT Halt Sequence Allows stepping through CRYPTO instructions in the sequence for debugging. Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DMA1PRESA...
- Page 878 Reference Manual CRYPTO - Crypto Accelerator 27.6.10 CRYPTO_SEQCTRLB - Sequence Control B Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DMA1PRESB DMA1 Preserve B...
- Page 879 Reference Manual CRYPTO - Crypto Accelerator 27.6.11 CRYPTO_IF - AES Interrupt Flags Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions BUFUF Buffer Underflow...
- Page 880 Reference Manual CRYPTO - Crypto Accelerator 27.6.12 CRYPTO_IFS - Interrupt Flag Set Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions BUFUF...
- Page 881 Reference Manual CRYPTO - Crypto Accelerator 27.6.13 CRYPTO_IFC - Interrupt Flag Clear Register Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions BUFUF...
- Page 882 Reference Manual CRYPTO - Crypto Accelerator 27.6.14 CRYPTO_IEN - Interrupt Enable Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions BUFUF BUFUF Interrupt Enable...
- Page 883 Reference Manual CRYPTO - Crypto Accelerator 27.6.16 CRYPTO_SEQ1 - Sequence Register 1 Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:24 INSTR7 0x00 Sequence Instruction 7 Sequence instruction. See INSTR in CRYPTO_CMD for a possible values. 23:16 INSTR6 0x00 Sequence Instruction 6...
- Page 884 Reference Manual CRYPTO - Crypto Accelerator 27.6.18 CRYPTO_SEQ3 - Sequence Register 3 Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:24 INSTR15 0x00 Sequence Instruction 15 Sequence instruction. See INSTR in CRYPTO_CMD for a possible values. 23:16 INSTR14 0x00 Sequence Instruction 14...
- Page 885 Reference Manual CRYPTO - Crypto Accelerator 27.6.20 CRYPTO_DATA0 - DATA0 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:0 DATA0 0xXXXXXXX Data 0 Access Access to DATA0. 4x32bits read/write accesses are required to fully read/write DATA0 27.6.21 CRYPTO_DATA1 - DATA1 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position...
- Page 886 Reference Manual CRYPTO - Crypto Accelerator 27.6.22 CRYPTO_DATA2 - DATA2 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x088 Reset Access Name Name Reset Access Description 31:0 DATA2 0xXXXXXXX Data 2 Access Access to DATA2. 4x32bits read/write accesses are required to fully read/write DATA2. 27.6.23 CRYPTO_DATA3 - DATA3 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position...
- Page 887 Reference Manual CRYPTO - Crypto Accelerator 27.6.24 CRYPTO_DATA0XOR - DATA0XOR Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description 31:0 DATA0XOR 0xXXXXXXX XOR Data 0 Access Any value written to this register will be XOR'ed with the value of DATA0. The result is stored in DATA0. Reads return DA- TA0 directly.
- Page 888 Reference Manual CRYPTO - Crypto Accelerator 27.6.26 CRYPTO_DATA1BYTE - DATA1 Register Byte Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x0B4 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DATA1BYTE...
- Page 889 Reference Manual CRYPTO - Crypto Accelerator 27.6.28 CRYPTO_DATA0BYTE12 - DATA0 Register Byte 12 Access (No Bit Access) Offset Bit Position 0x0C0 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DATA0BYTE12...
- Page 890 Reference Manual CRYPTO - Crypto Accelerator 27.6.30 CRYPTO_DATA0BYTE14 - DATA0 Register Byte 14 Access (No Bit Access) Offset Bit Position 0x0C8 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DATA0BYTE14...
- Page 891 Reference Manual CRYPTO - Crypto Accelerator 27.6.32 CRYPTO_DDATA0 - DDATA0 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x100 Reset Access Name Name Reset Access Description 31:0 DDATA0 0xXXXXXXX Double Data 0 Access Access to DDATA0. 8x32bits read/write accesses are required to fully read/write DDATA0. 27.6.33 CRYPTO_DDATA1 - DDATA1 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position...
- Page 892 Reference Manual CRYPTO - Crypto Accelerator 27.6.34 CRYPTO_DDATA2 - DDATA2 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x108 Reset Access Name Name Reset Access Description 31:0 DDATA2 0xXXXXXXX Double Data 0 Access Access to DDATA2, which consists of {DATA1, DATA0}. 8x32bits read/write accesses are required to fully read/write DDA- TA2.
- Page 893 Reference Manual CRYPTO - Crypto Accelerator 27.6.36 CRYPTO_DDATA4 - DDATA4 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x110 Reset Access Name Name Reset Access Description 31:0 DDATA4 0xXXXXXXX Double Data 0 Access Access to DDATA4, which is equal to the full width of KEYBUF regardless of AES256 in CRYPTO_CTRL. 8x32bits read/ write accesses are required to fully read/write DDATA4.
- Page 894 Reference Manual CRYPTO - Crypto Accelerator 27.6.38 CRYPTO_DDATA0BYTE - DDATA0 Register Byte Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x140 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DDATA0BYTE...
- Page 895 Reference Manual CRYPTO - Crypto Accelerator 27.6.40 CRYPTO_DDATA0BYTE32 - DDATA0 Register Byte 32 Access (No Bit Access) Offset Bit Position 0x148 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DDATA0BYTE32...
- Page 896 Reference Manual CRYPTO - Crypto Accelerator 27.6.42 CRYPTO_QDATA1 - QDATA1 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x184 Reset Access Name Name Reset Access Description 31:0 QDATA1 0xXXXXXXX Quad Data 1 Access Access to QDATA1, which is equal to {DATA3, DATA2, DATA1, DATA0} and {DDATA3, DDATA2}. 16x32bits read/write accesses are required to fully read/write QDATA1.
- Page 897 Reference Manual CRYPTO - Crypto Accelerator 27.6.44 CRYPTO_QDATA0BYTE - QDATA0 Register Byte Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x1C0 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions QDATA0BYTE...
- Page 898 Reference Manual GPIO - General Purpose Input/Output 28. GPIO - General Purpose Input/Output Quick Facts What? The General Purpose Input/Output (GPIO) is used for pin configuration, direct pin manipulation and sensing, as well as routing for peripheral pin connec- tions. Why? Easy to use and highly configurable input/output pins are important to fit many communication proto-...
- Page 899 Reference Manual GPIO - General Purpose Input/Output 28.2 Features • Individual configuration for each pin • Tristate (reset state) • Push-pull • Open-drain • Pull-up resistor • Pull-down resistor • Drive strength • 1 mA • 10 mA • Slewrate •...
- Page 900 Reference Manual GPIO - General Purpose Input/Output 28.3 Functional Description An overview of the GPIO module is shown in Figure 28.1 Pin Configuration on page 900. The GPIO pins are grouped into 16-pin ports. Each individual GPIO pin is called Pxn where x indicates the port (A, B, C ...) and n indicates the pin number (0,1,..,15). Fewer than 16 bits may be available on some ports, depending on the total number of I/O pins on the package.
- Page 901 Reference Manual GPIO - General Purpose Input/Output 28.3.1 Pin Configuration In addition to setting the pins as either outputs or inputs, the GPIO_Px_MODEL and GPIO_Px_MODEH registers can be used for more advanced configurations. GPIO_Px_MODEL contains 8 bit fields named MODEn (n=0,1,..7) which control pins 0-7, while GPIO_Px_MODEH contains 8 bit fields named MODEn (n=8,9,..15) which control pins 8-15.
- Page 902 Reference Manual GPIO - General Purpose Input/Output Set DINDIS to disable the input of a gpio port. The pull-up, pull-down and glitch filter function can optionally be applied to the input, see Figure 28.2 Tristated Output With Optional Pull-up or Pull-down on page 902.
- Page 903 Reference Manual GPIO - General Purpose Input/Output 28.3.1.1 Over Voltage Tolerance Over voltage capability is available for most pins. If available, it allows the pin to be used at the minimum of IOVDD + 2V and 5.5V (for 5V tolerant pads). The data sheet specifies which pins can be used as 5V tolerant pins. Default over voltage is enabled for each pin supporting that feature.
- Page 904 Reference Manual GPIO - General Purpose Input/Output 28.3.2 EM4 Wake-up It is possible to trigger a wake-up from EM4 using any of the selectable EM4WU GPIO pins. The wake-up request can be triggered through the pins by enabling the corresponding bit in the GPIO_EM4WUEN register. When EM4 wake-up is enabled for the pin, the input filter is enabled during EM4.
- Page 905 Reference Manual GPIO - General Purpose Input/Output 28.3.4 Alternate Functions Alternate functions are connections to pins from peripherals, i.e. Timers, USARTs, etc.. These peripherals contain route registers, where the pin connections are enabled. In addition, the route registers contain a location bit field that configures which pin an output of that peripheral will be connected to if enabled.
- Page 906 Reference Manual GPIO - General Purpose Input/Output 28.3.5.1 Edge Interrupt Generation The GPIO can generate an interrupt from any edge of the input of any GPIO pin on the device. The edge interrupts have asynchronous sense capability, enabling wake-up from energy modes as low as EM3 Stop, see Figure 28.6 Pin N Interrupt Generation on page 906.
- Page 907 Reference Manual GPIO - General Purpose Input/Output 28.3.5.2 Level Interrupt Generation GPIO can generate a level interrupt using the input of any GPIO EM4 wake-up pins on the device. The interrupts have asynchronous sense capability, enabling wake-up from energy modes as low as EM4. In order to enable the level interrupt, set the EM4WU field in the GPIO_IEN register and the EM4WUn field in the GPIO_EXTILEVEL register.
- Page 908 Reference Manual GPIO - General Purpose Input/Output 28.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 GPIO_PA_CTRL Port Control Register 0x004 GPIO_PA_MODEL Port Pin Mode Low Register 0x008 GPIO_PA_MODEH Port Pin Mode High Register 0x00C GPIO_PA_DOUT Port Data Out Register...
- Page 909 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x42C GPIO_EM4WUEN EM4 Wake Up Enable Register 0x440 GPIO_ROUTEPEN I/O Routing Pin Enable Register 0x444 GPIO_ROUTELOC0 I/O Routing Location Register 0x450 GPIO_INSENSE Input Sense Register 0x454 GPIO_LOCK Configuration Lock Register silabs.com | Building a more connected world.
- Page 910 Reference Manual GPIO - General Purpose Input/Output 28.5 Register Description 28.5.1 GPIO_Px_CTRL - Port Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DINDISALT...
- Page 911 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description DRIVESTRENGTH Drive Strength for Port Drive strength setting for port pins not using alternate modes. Value Mode Description STRONG 10 mA drive current WEAK 1 mA drive current silabs.com | Building a more connected world. Rev.
- Page 912 Reference Manual GPIO - General Purpose Input/Output 28.5.2 GPIO_Px_MODEL - Port Pin Mode Low Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:28 MODE7 Pin 7 Mode Configure mode for pin 7. Value Mode Description DISABLED Input disabled.
- Page 913 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description PUSHPULL Push-pull output PUSHPULLALT Push-pull using alternate control WIREDOR Wired-or output WIREDORPULLDOWN Wired-or output with pull-down WIREDAND Open-drain output WIREDANDFILTER Open-drain output with filter WIREDANDPULLUP Open-drain output with pullup WIREDANDPULLUP- Open-drain output with filter and pullup FILTER...
- Page 914 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 19:16 MODE4 Pin 4 Mode Configure mode for pin 4. Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled. Filter if DOUT is set INPUTPULL Input enabled.
- Page 915 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDALT Open-drain output using alternate control WIREDANDALTFILTER Open-drain output using alternate control with filter WIREDANDALTPULL- Open-drain output using alternate control with pullup WIREDANDALTPUL- Open-drain output using alternate control with filter and pullup LUPFILTER 11:8 MODE2...
- Page 916 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDORPULLDOWN Wired-or output with pull-down WIREDAND Open-drain output WIREDANDFILTER Open-drain output with filter WIREDANDPULLUP Open-drain output with pullup WIREDANDPULLUP- Open-drain output with filter and pullup FILTER WIREDANDALT Open-drain output using alternate control WIREDANDALTFILTER Open-drain output using alternate control with filter WIREDANDALTPULL- Open-drain output using alternate control with pullup...
- Page 917 Reference Manual GPIO - General Purpose Input/Output 28.5.3 GPIO_Px_MODEH - Port Pin Mode High Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:28 MODE15 Pin 15 Mode Configure mode for pin 15. Value Mode Description DISABLED Input disabled.
- Page 918 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description PUSHPULL Push-pull output PUSHPULLALT Push-pull using alternate control WIREDOR Wired-or output WIREDORPULLDOWN Wired-or output with pull-down WIREDAND Open-drain output WIREDANDFILTER Open-drain output with filter WIREDANDPULLUP Open-drain output with pullup WIREDANDPULLUP- Open-drain output with filter and pullup FILTER...
- Page 919 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 19:16 MODE12 Pin 12 Mode Configure mode for pin 12. Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled. Filter if DOUT is set INPUTPULL Input enabled.
- Page 920 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDALT Open-drain output using alternate control WIREDANDALTFILTER Open-drain output using alternate control with filter WIREDANDALTPULL- Open-drain output using alternate control with pullup WIREDANDALTPUL- Open-drain output using alternate control with filter and pullup LUPFILTER 11:8 MODE10...
- Page 921 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDORPULLDOWN Wired-or output with pull-down WIREDAND Open-drain output WIREDANDFILTER Open-drain output with filter WIREDANDPULLUP Open-drain output with pullup WIREDANDPULLUP- Open-drain output with filter and pullup FILTER WIREDANDALT Open-drain output using alternate control WIREDANDALTFILTER Open-drain output using alternate control with filter WIREDANDALTPULL- Open-drain output using alternate control with pullup...
- Page 922 Reference Manual GPIO - General Purpose Input/Output 28.5.4 GPIO_Px_DOUT - Port Data Out Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
- Page 923 Reference Manual GPIO - General Purpose Input/Output 28.5.6 GPIO_Px_DIN - Port Data in Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
- Page 924 Reference Manual GPIO - General Purpose Input/Output 28.5.8 GPIO_Px_OVTDIS - Over Voltage Disable for All Modes Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
- Page 925 Reference Manual GPIO - General Purpose Input/Output 28.5.9 GPIO_EXTIPSELL - External Interrupt Port Select Low Register Offset Bit Position 0x400 Reset Access Name Name Reset Access Description 31:28 EXTIPSEL7 External Interrupt 7 Port Select Select input port for external interrupt 7. Value Mode Description...
- Page 926 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Value Mode Description PORTA Port A group selected for external interrupt 4 PORTB Port B group selected for external interrupt 4 PORTC Port C group selected for external interrupt 4 PORTD Port D group selected for external interrupt 4 PORTF...
- Page 927 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description PORTC Port C group selected for external interrupt 0 PORTD Port D group selected for external interrupt 0 PORTF Port F group selected for external interrupt 0 silabs.com | Building a more connected world. Rev.
- Page 928 Reference Manual GPIO - General Purpose Input/Output 28.5.10 GPIO_EXTIPSELH - External Interrupt Port Select High Register Offset Bit Position 0x404 Reset Access Name Name Reset Access Description 31:28 EXTIPSEL15 External Interrupt 15 Port Select Select input port for external interrupt 15. Value Mode Description...
- Page 929 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Value Mode Description PORTA Port A group selected for external interrupt 12 PORTB Port B group selected for external interrupt 12 PORTC Port C group selected for external interrupt 12 PORTD Port D group selected for external interrupt 12 PORTF...
- Page 930 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description PORTC Port C group selected for external interrupt 8 PORTD Port D group selected for external interrupt 8 PORTF Port F group selected for external interrupt 8 silabs.com | Building a more connected world. Rev.
- Page 931 Reference Manual GPIO - General Purpose Input/Output 28.5.11 GPIO_EXTIPINSELL - External Interrupt Pin Select Low Register Offset Bit Position 0x408 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:28...
- Page 932 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 19:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 17:16 EXTIPINSEL4 External Interrupt 4 Pin Select Select the pin for external interrupt 4. Value Mode Description...
- Page 933 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EXTIPINSEL0 External Interrupt 0 Pin Select Select the pin for external interrupt 0. Value Mode Description...
- Page 934 Reference Manual GPIO - General Purpose Input/Output 28.5.12 GPIO_EXTIPINSELH - External Interrupt Pin Select High Register Offset Bit Position 0x40C Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:28...
- Page 935 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 19:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 17:16 EXTIPINSEL12 External Interrupt 12 Pin Select Select the pin for external interrupt 12. Value Mode Description...
- Page 936 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EXTIPINSEL8 External Interrupt 8 Pin Select Select the pin for external interrupt 8. Value Mode Description...
- Page 937 Reference Manual GPIO - General Purpose Input/Output 28.5.14 GPIO_EXTIFALL - External Interrupt Falling Edge Trigger Register Offset Bit Position 0x414 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
- Page 938 Reference Manual GPIO - General Purpose Input/Output 28.5.15 GPIO_EXTILEVEL - External Interrupt Level Register Offset Bit Position 0x418 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM4WU12...
- Page 939 Reference Manual GPIO - General Purpose Input/Output 28.5.16 GPIO_IF - Interrupt Flag Register Offset Bit Position 0x41C Reset Access Name Name Reset Access Description 31:16 EM4WU 0x0000 EM4 Wake Up Pin Interrupt Flag EM4 wake up Pin Interrupt flag. Value Description Interrupt flag cleared Interrupt flag set...
- Page 940 Reference Manual GPIO - General Purpose Input/Output 28.5.18 GPIO_IFC - Interrupt Flag Clear Register Offset Bit Position 0x424 Reset Access Name Name Reset Access Description 31:16 EM4WU 0x0000 (R)W1 Clear EM4WU Interrupt Flag Write 1 to clear the EM4WU interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
- Page 941 Reference Manual GPIO - General Purpose Input/Output 28.5.20 GPIO_EM4WUEN - EM4 Wake Up Enable Register Offset Bit Position 0x42C Reset Access Name Name Reset Access Description 31:16 EM4WUEN 0x0000 EM4 Wake Up Enable Write 1 to enable EM4 wake up request, write 0 to disable EM4 wake up request. Value Description Disable EM4 wake up on pin...
- Page 942 Reference Manual GPIO - General Purpose Input/Output 28.5.21 GPIO_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x440 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SWVPEN...
- Page 943 Reference Manual GPIO - General Purpose Input/Output 28.5.22 GPIO_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x444 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SWVLOC...
- Page 944 Reference Manual GPIO - General Purpose Input/Output 28.5.24 GPIO_LOCK - Configuration Lock Register Offset Bit Position 0x454 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
- Page 945 Reference Manual APORT - Analog Port 29. APORT - Analog Port Quick Facts What? The Analog Port (APORT) is a set of analog buses which are used to connect I/O pins to analog periph- eral signals. Why? The APORT gives on-chip analog resources access to a large number of I/O pins, and provides the sys- .
- Page 946 Reference Manual APORT - Analog Port 29.3 Functional Description Analog node (ANODE) 0 Analog node (ANODE) 1 Analog bus (ABUS) Analog node (ANODE) 2 Analog node (ANODE) 3 Switch control Figure 29.1. Analog Bus (ABUS) An analog bus (ABUS) consists of analog switches connected to a common wire as shown in Figure 29.1 Analog Bus (ABUS) on page 946.
- Page 947 Reference Manual APORT - Analog Port 29.3.2 APORT ABUS Naming Producer 0 (e.g. VDAC, IDAC) Producer 1 (e.g. VDAC, IDAC) Producer 2 (e.g. VDAC, IDAC) Pin 0 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Consumer 0 (e.g.
- Page 948 Reference Manual APORT - Analog Port followed by a letter). It is possible that different instances of an APORT client connect to different ABUSes. For example, ACMP0 APORT1X might connect to the ABUS BUSAX while ACMP1 APORT1X might connect to ABUS BUSCX. Refer to the APORT Client Map in the device data sheet to map the generalized APORT client bus name to an actual device ABUS.
- Page 949 Reference Manual APORT - Analog Port • Set IDAC_CTRL_APORTOUTSEL = APORT1XCH30. This selects the IDAC APORT output 1X and pin PB14. • Set IDAC_CTRL_APORTOUTEN = 1 and IDAC_CTRL_APORTOUTENPRS = 0. This enables the IDAC to ungate it's output to BUSCX. Another example, when ADC is configured to operate in single channel mode for differential inputs (see 24.3.3.1 Single Channel Mode for how to configure ADC in single channel mode), the positive ADC APORT input 2X and the negative ADC APORT input 2Y can be...
- Page 950 Reference Manual APORT - Analog Port 29.3.3 Managing ABUSes The ABUSes of an APORT are shared resources. The user needs to be mindful of this in assigning I/O for different clients throughout the chip, as it is possible to have conflicts for a given ABUS. Each ABUS has an arbiter responsible for limiting the control over the ABUS to one and only one client.
- Page 951 Reference Manual APORT - Analog Port APORT_CONTROL APORT_REQ = APORT_REQ = APORT_REQ = 0001_0000 0011_0000 0000_1111 ACMP0 ACMP1 ADC0 Figure 29.5. APORT Example 2: Bus Conflict Figure 29.5 APORT Example 2: Bus Conflict on page 951 is a similar example to Figure 29.4 APORT Example 1 on page 950, but now both ACMP0 and ACMP1 are requesting ABUS[4].
- Page 952 Reference Manual FPUEH - Floating Point Unit Exception Handler 30. FPUEH - Floating Point Unit Exception Handler Quick Facts What? FPU exception handler allows user defined handling of FPU exceptions. Why? Proper handling of exceptions is crucial in many ap- plications.
- Page 953 Reference Manual FPUEH - Floating Point Unit Exception Handler 30.3 Register Description 30.3.1 FPUEH_IF - Interrupt Flag Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions FPIXC...
- Page 954 Reference Manual FPUEH - Floating Point Unit Exception Handler 30.3.2 FPUEH_IFS - Interrupt Flag Set Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions FPIXC...
- Page 955 Reference Manual FPUEH - Floating Point Unit Exception Handler 30.3.3 FPUEH_IFC - Interrupt Flag Clear Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions FPIXC...
- Page 956 Reference Manual FPUEH - Floating Point Unit Exception Handler 30.3.4 FPUEH_IEN - Interrupt Enable Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions FPIXC...
- Page 957 Reference Manual Revision History 31. Revision History Revision 1.3 July, 2022 • Changed incorrect SysTick resolution from 32 to 24 bits in 2.16 Timers. • References to selecting a third clock output removed from 12.3.5 Clock Output on a Pin 12.3.6 Clock Output on PRS because the CMU_CTRL register does not contain the CLKOUT2 bit field.
- Page 958 Reference Manual Revision History Revision 1.0 December, 2017 • Formatting and color scheme updated to latest corporate stylesheet. • Table 3.1: Added ACMP1 module to IRQ13. • Section 4.7: DI entry descriptions updated with additional serial flash part in EXTINFO and additional product families in PART. •...
- Page 959 Reference Manual Abbreviations Appendix 1. Abbreviations This section lists abbreviations used in this document. Table 1.1. Abbreviations Abbreviation Description Analog to Digital Converter Advanced Encryption Standard Automatic Frequency Control Automatic Gain Control AMBA Advanced High-performance Bus. AMBA is short for "Advanced Microcontroller Bus Architec- ture".
- Page 960 Reference Manual Abbreviations Abbreviation Description Detection of Signal Arrival DSSS Direct Sequence Spread Spectrum Electronic Code Book (AES mode of operation) EFR32 Wireless Gecko Energy Mode Energy Management Unit Forward Error Correction Finite Impulse Response Frame Controller Frequency Shift Keying GFSK Gaussian Frequency Shift Keying GMSK...
- Page 961 Reference Manual Abbreviations Abbreviation Description Pulse Width Modulation Radio Controller Random Access Memory Radio Frequency Reset Management Unit Radio State Machine RSSI Received Signal Strength Indicator Real Time Counter Receive Radio Sequencer Serial Peripheral Interface Sample Rate Converter STIMER Sequencer Timer Software SYNTH Synthesizer...
- Page 962 Note: This content may contain offensive terminology that is now obsolete. Silicon Labs is replacing these terms with inclusive language wherever possible. For more information, visit www.silabs.com/about-us/inclusive-lexicon-project Trademark Information Silicon Laboratories Inc. , Silicon Laboratories , Silicon Labs , SiLabs...
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