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Philips Semiconductors
CS_N
DMACK_N
A0
WR_N
DATA[7:0]
RD_N
DATA[7:0]
Fig 18. Parallel interface timing (I/O and DMA).
Table 18:
AC characteristics (DMA)
Symbol Parameter
Single-cycle DMA timings
t
DMACK_N HIGH to DMREQ HIGH time
AHRH
t
RD_N/WR_N HIGH to DMACK_N HIGH time
SHAH
t
DMREQ HIGH to RD_N/WR HIGH time
RHSH
t
EOT_N LOW pulse width
EL
Burst DMA timings
t
RD_N/WR_N LOW to DMREQ LOW time
SLRL
t
RD_N (only) HIGH to next data valid
RHNDV
EOT timings
t
EOT_N LOW to DMREQ LOW time
ELRL
9397 750 09238
Product data
t
CLRL
t
CLWL
t
AVRL
t
AVWL
COMMAND = 1, DATA = 0
t
WL
t
WDSU
VALID DATA
t
RL
t
RLDD
VALID DATA
Conditions
simultaneous DMACK_N,
RD_N/WR_N and EOT_N
LOW time
Rev. 08 — 20 December 2001
USB interface device with parallel bus
t
RHCH
t
WHCH
t
WHAX
t
WC
t
(WC - WD)
t
(WC - RD)
t
WDH
t
RC
t
RHNDV
t
RHDZ
t
RLDD
PDIUSBD12
VALID DATA
004aaa058
Min
Max
Unit
−
330
ns
−
130
ns
−
120
ns
10
-
ns
-
40
ns
−
420
ns
−
40
ns
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
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