Nuvoton NuMicro NUC442 Series Technical Reference Manual page 1289

NuMicro NUC442/NUC472 Series Technical Reference Manual
Control-Endpoint Control Register (USBD_CEPCTL)
Register Offset
USBD_CEPCTL USBD_BA+0x02C R/W Control-Endpoint Control Register
31 30
23 22
15 14
7 6
Reserved
Bits Description
[31:4] Reserved
[3] FLUSH
[2] ZEROLEN
STALLEN
[1]
May 23, 2014
R/W Description
29 28 27
Reserved
21 20 19
Reserved
13 12 11
Reserved
5 4 3
FLUSH
Reserved.
CEP-FLUSH Bit
0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be
cleared.
1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be
cleared. This bit is self-cleaning.
Zero Packet Length
This bit is valid for Auto Validation mode only.
0 = No zero length packet to the host during Data stage to an IN token.
1 = USB device controller can send a zero length packet to the host during Data stage
to an IN token. This bit gets cleared once the zero length data packet is sent. So, the
local CPU need not write again to clear this bit.
Stall Enable Bit
When this stall bit is set, the control endpoint sends a stall handshake in response to
any in or out token thereafter. This is typically used for response to invalid/unsupported
requests. When this bit is being set the NAK clear bit has to be cleared at the same time
since the NAK clear bit has highest priority than STALL. It is automatically cleared on
receipt of a next setup-token. So, the local CPU need not write again to clear this bit.
0 = No sends a stall handshake in response to any in or out token thereafter.
1 = The control endpoint sends a stall handshake in response to any in or out token
thereafter.
Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
Page 1289 of 1386
26 25
18 17
10 9
2 1
ZEROLEN STALLEN
Reset Value
0x0000_0000
24
16
8
0
NAKCLR
Rev.1.05