Nuvoton NUC970 series Technical Reference Manual

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NUC970 Technical Reference Manual

ARM926EJ-S Based

32-bit Microcontroller

NUC970 Series

Technical Reference Manual

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based

system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com

Publication Release Date: Dec. 15, 2015

- 1 -

Revision V1.30

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Summary of Contents for Nuvoton NUC970 series

Page 1 The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.
Page 2 NUC970 Technical Reference Manual Publication Release Date: Dec. 15, 2015 - 2 - Revision V1.30...
Page 3: Table Of Contents
GENERAL DESCRIPTION ..................18 FEATURES ......................... 19 NUC970 Series Features ....................19 PARTS INFORMATION LIST AND PIN CONFIGURATION ........27 NUC970 Series Part Number Naming Guide..............27 NUC970 Series Part Selection Guide ................. 28 Pin Configuration ....................... 29 3.3.1 NUC972DFxxY Pin Diagram ......................29 3.3.2...
Page 4 NUC970 Technical Reference Manual 5.3.1 Overview ............................139 5.3.2 Features ............................139 5.3.3 Block diagram ..........................140 5.3.4 Functional description ........................149 5.3.5 Registers Map ..........................151 5.3.6 Register description ........................152 Advanced Interrupt Controller (AIC) ................. 186 5.4.1 Overview ............................186 5.4.2 Features ............................
Page 5 NUC970 Technical Reference Manual 5.7.6 Register Map ..........................263 5.7.7 Register Description ........................264 General Purpose I/O (GPIO) .................... 272 5.8.1 Overview ............................272 5.8.2 Features ............................272 5.8.3 Block Diagram ..........................273 5.8.4 Basic Configuration ........................273 5.8.5 Functional Description ........................273 5.8.6 Register Map ..........................
Page 6 NUC970 Technical Reference Manual 5.12.2 Features ............................347 5.12.3 Block Diagram ..........................348 5.12.4 Basic Configuration ........................348 5.12.5 Functional Description ........................348 5.12.6 Register Map ..........................352 5.12.7 Register Description ........................353 5.13 Watchdog Timer (WDT) ....................363 5.13.1 Overview ............................363 5.13.2 Features ............................
Page 7 NUC970 Technical Reference Manual 5.16.6 Register Map ..........................443 5.16.7 Register Description ........................445 5.17 Smart Card Host Interface (SC) ..................474 5.17.1 Overview ............................474 5.17.2 Features ............................474 5.17.3 Block Diagram ..........................475 5.17.4 Basic Configuration ........................476 5.17.5 Functional description ........................
Page 8 NUC970 Technical Reference Manual 5.21.2 Features ............................581 5.21.3 Block Diagram ..........................582 5.21.4 Basic Configuration ........................582 5.21.5 Functional Description ........................583 5.21.6 DMA Descriptors Data Structure ....................586 5.21.7 Register Map ..........................599 5.21.8 Register Description ........................603 5.22 USB 2.0 Device Controller (USBD) ..................
Page 9 NUC970 Technical Reference Manual 5.25.3 Block Diagram ..........................837 5.25.4 Basic Configuration ........................837 5.25.5 Functional Description ........................838 5.25.6 Register Map ..........................843 5.25.7 Register Description ........................846 5.26 Secure Digital Host Controller (SDH) ................907 5.26.1 Overview ............................907 5.26.2 Features ............................
Page 10 NUC970 Technical Reference Manual 5.29.7 Register Description ........................1051 5.30 LCD Display Interface Controller (LCM) ................. 1105 5.30.1 Overview ............................1105 5.30.2 Features ............................1105 5.30.3 Block Diagram ..........................1106 5.30.4 Basic Configuration ........................1106 5.30.5 Functional Description ........................1107 5.30.6 Register Map ..........................
Page 11 NUC970 Technical Reference Manual REVISION HISTORY ....................1250 Publication Release Date: Dec. 15, 2015 - 11 - Revision V1.30...
Page 12: List Of Figures
NUC970 Technical Reference Manual LIST OF FIGURES Figure 3.1-1 NUC970 Series Part Number Naming Guide ............27 Figure 3.3-1 NUC972DFxxY LQFP 216-pin Pin Diagram .............. 29 Figure 3.3-2 NUC976DKxxY LQFP 128-pin Pin Diagram.............. 30 Figure 3.3-3 NUC977DKxxY LQFP 128-pin Pin Diagram.............. 31 Figure 4.1-1 NUC970 Series Block Diagram .................
Page 13 NUC970 Technical Reference Manual Figure 5.10-1 Timer Controller Block Diagram ................323 Figure 5.11-1 Enhance Timer Controller Block Diagram ............. 332 Figure 5.11-2 Enhance Timer Clock Controller Diagram ............. 333 Figure 5.11-3 Timer Clock Controller Diagram ................335 Figure 5.12-1 Two channels of PWM in one pair ................. 348 Figure 5.12-2 Legend of Internal Comparator Output of PWM-Timer .........
Page 14 NUC970 Technical Reference Manual Figure 5.17-6 SC Deactivation Sequence ..................480 Figure 5.17-7 Basic Operation Flow..................... 481 Figure 5.17-8 Initial Character TS ....................482 Figure 5.17-9 SC Error Signal ...................... 482 Figure 5.18-1 I C Block Diagram ....................517 Figure 5.18-2 I C Bus Timing .......................
Page 15 NUC970 Technical Reference Manual Figure 5.24-3 CAN Core in Loop Back Mode ................775 Figure 5.24-4 CAN Core in Loop Back Mode Combined with Silent Mode ......... 776 Figure 5.24-5 Data transfer between IFn Registers and Message ..........779 Figure 5.24-6 Application Software Handling of a FIFO Buffer ............ 784 Figure 5.24-7 Bit Timing .......................
Page 16 NUC970 Technical Reference Manual Figure 5.30-1 LCD Display Interface Controller Functional Block Diagram ....1106 Figure 5.30-2 Display and Overlay Control Timing ............1107 Figure 5.31-1 Image Capture Functional Block Diagram ............1162 Figure 5.32-1 ADC Functional Block Diagram ................1199 Figure 5.32-2 ADC Transfer Function ..................
Page 17: List Of Tables
NUC970 Technical Reference Manual LIST OF TABLES Table 5.2-1 Address Space Assignments for On-Chip Controllers ..........68 Table 5.13-1 Watchdog Time-out Interval Period Selection ............365 Table 5.13-2 Watchdog Reset Period Selection ................365 Table 5.14-1 Window Watchdog Prescaler Value Selection ............373 Table 5.14-2 CMPDA Setting Limitation ..................
Page 18: General Description
Timer, WDT/Windowed-WDT, GPIO, Keypad, Smart Card I/F, 32.768 KHz XTL and RTC (Real Time Clock). In addition, the NUC970 series integrates a DRAM I/F, that runs up to 150MHz with supporting DDR2 type SDRAM, and an External Bus Interface (EBI) that supports SRAM and external device with DMA request and ack.
Page 19: Features
NUC970 Technical Reference Manual FEATURES NUC970 Series Features  Core – ARM® ARM926EJ-S™ processor core runs up to 300 MHz – Support 16 KB instruction cache and 16 KB data cache – Support MMU – Support JTAG Debug interface ...
Page 20 NUC970 Technical Reference Manual – Support USB Revision 2.0 specification – Support one set of USB 2.0 High-Speed (HS) Device/Host with embedded transceiver – Support one set of USB 2.0 High-Speed (HS) Host with embedded transceiver – Support Control, Bulk, Interrupt, Isochronous and Split transfers –...
Page 21 NUC970 Technical Reference Manual  Capture (CMOS Sensor Interface) – Support CCIR601 & CCIR656 interfaces to connect with CMOS image sensor – Support resolution up to 3M pixels – Support YUV422 and RGB565 color format for data output by CMOS image sensor –...
Page 22 NUC970 Technical Reference Manual – Support arbitrary width and height image encode and decode – Support three programmable quantization-tables – Support standard default Huffman-table and programmable Huffman-table for decode – Support arbitrarily 1X~8X image up-scaling function for encode mode – Support down-scaling function for encode and decode modes –...
Page 23 NUC970 Technical Reference Manual  UART – Support up to 11 UART controllers – Support 1 UART (UART 1) port with full model function (TXD, RXD, CTS, RTS, CDn, RIn, DTR and DSR) and 64-byte FIFO – Support 5 UART (UART 2/4/6/8/10) ports with flow control (TXD, RXD, CTS and RTS) and 64-byte FIFO –...
Page 24 NUC970 Technical Reference Manual  Windowed-Watchdog Timer – 6-bit down counter with 11-bit pre-scale for wide range window selected – Interrupt on windowed-watchdog timer time-out – Reset on windowed-watchdog timer time out or reload in an unexpected time window  Real Time Clock (RTC) –...
Page 25 NUC970 Technical Reference Manual triggered  GPIO – TTL/Schmitt trigger input selectable – I/O pin can be configured as interrupt source with edge/level setting – Support pull-up and pull-down control  – 12-bit SAR ADC with 1M/200K SPS – Up to 8-ch single-end input –...
Page 26 NUC970 Technical Reference Manual – All Green package (RoHS) – LQFP 216-pin – LQFP 128-pin Publication Release Date: Dec. 15, 2015 - 26 - Revision V1.30...
Page 27: Parts Information List And Pin Configuration
Product Number Package Type D: LQFP Pin Count K: 128pin 14x14mm Memory Size F: 216pin 24x24mm 5: 32M Bytes 6: 64M Bytes Figure 3.1-1 NUC970 Series Part Number Naming Guide Publication Release Date: Dec. 15, 2015 - 27 - Revision V1.30...
Page 28: Nuc970 Series Part Selection Guide
NUC970 Technical Reference Manual NUC970 Series Part Selection Guide Storage Timer Peripheral ADC (12-bit) Part No. ARM9 NUC972DF62Y 64 1 24 √ 2 2 2 1 √ √ √ 5 4 √ √ 4 √ 8 200K* √ √ √ 146 11 2 2 2 2 √...
Page 29: Pin Configuration
NUC970 Technical Reference Manual Pin Configuration 3.3.1 NUC972DFxxY Pin Diagram Figure 3.3-1 NUC972DFxxY LQFP 216-pin Pin Diagram Publication Release Date: Dec. 15, 2015 - 29 - Revision V1.30...
Page 30: Nuc976Dkxxy Pin Diagram
NUC970 Technical Reference Manual 3.3.2 NUC976DKxxY Pin Diagram Figure 3.3-2 NUC976DKxxY LQFP 128-pin Pin Diagram Publication Release Date: Dec. 15, 2015 - 30 - Revision V1.30...
Page 31: Nuc977Dkxxy Pin Diagram
NUC970 Technical Reference Manual 3.3.3 NUC977DKxxY Pin Diagram Figure 3.3-3 NUC977DKxxY LQFP 128-pin Pin Diagram Publication Release Date: Dec. 15, 2015 - 31 - Revision V1.30...
Page 32: Pin Description
NUC970 Technical Reference Manual Pin Description NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type PG.3 General purpose digital I/O pin Port G Pin 3. I2C1_SDA C1 data input/output pin. PG.2 General purpose digital I/O pin Port G Pin 2. I2C1_SCL C1 clock pin.
Page 33 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type UART6_TXD Data transmitter output pin for UART6. SC0_CLK SmartCard0 clock pin. PG.10 General purpose digital I/O pin Port G Pin 10. I2S_MCLK S master clock output pin. SC0_RST SmartCard0 reset pin.
Page 34 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type TM3_TGL Enhanced TIMER toggle output pin. INT2 External interrupt 2 input pin. PF.12 General purpose digital I/O pin Port F Pin 12. UART2_RXD Data receiver input pin for UART2. TM2_CAP Enhanced TIMER capture input pin.
Page 35 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type UART9_TXD Data transmitter output pin for UART9. PWM2 PWM2 output pin. EBI_nOE External I/O output enable. PD.13 General purpose digital I/O pin Port D Pin 13. LCD_DATA21 LCD pixel data output bit 21.
Page 36 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type PA.15 General purpose digital I/O pin Port A Pin 15. LCD_DATA15 LCD pixel data output bit 15. KPI_COL7 Keypad Column Scan Input Bus 7. PWM3 PWM3 output pin. PA.14 General purpose digital I/O pin Port A Pin 14.
Page 37 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type LCD_DATA9 LCD pixel data output bit 9. KPI_COL1 Keypad Column Scan Input Bus 1. PWRON_SET9 Power On Setting bit 9. PA.8 General purpose digital I/O pin Port A Pin 8. RMII0_CRSDV RMII0 carrier sense / receive data valid.
Page 38 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type LCD_DATA4 LCD pixel data output bit 4. KPI_ROW0 Keypad Row Scan Output Bus 0. PWRON_SET4 Power On Setting bit 4. PA.3 General purpose digital I/O pin Port A Pin 3. RMII0_TXDATA1 RMII0 transmit data bus bit 1.
Page 39 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type ADC5 ADC input channel 5 or YP. ADC1 ADC input channel 1. ADC3 ADC input channel 3 or VSENSE. ADC2 ADC input channel 2. VREF ADC voltage reference pin. RTC_VDD RTC power input.
Page 40 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type EBI_ADDR2 External I/O address bus bit 2. INT6 External interrupt 6 input pin. PH.7 General purpose digital I/O pin Port H Pin 7. KPI_ROW3 Keypad Row Scan Output Bus 3. SD/SDIO Port 1 –...
Page 41 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type SD1_DAT3 SD/SDIO mode #1 data line bit 3. UART4_CTS Clear to send input pin for UART4. EBI_ADDR7 External I/O address bus bit 7. PH.12 General purpose digital I/O pin Port H Pin 12. KPI_COL4 Keypad Column Scan Input Bus 4.
Page 42 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type UART8_CTS Clear to send input pin for UART8. CAN1_TXD CAN bus transmitter1 output. EBI_nBE1 External I/O high byte enable. PI.0 General purpose digital I/O pin Port I Pin 0. EBI_DATA0 External I/O data bus bit 0.
Page 43 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type I2C1_SDA C1 data input/output pin. EBI_DATA4 External I/O data bus bit 4. CAN0_TX CAN bus transmitter0 output. PI.5 General purpose digital I/O pin Port I Pin 5. VCAP_HSYNC Sensor interface HSYNC.
Page 44 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type EBI_DATA7 External I/O data bus bit 7. SD1_DAT0 SD/SDIO mode #1 data line bit 0. UART1_RTS Request to send output pin for UART1. SPI1_DO SPI1 Data out pin. SPI1 data 0 in dual/quad mode. (SPI1_DATA0) (I/O) PI.8...
Page 45 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type eMMC_DATA2 eMMC data line bit 2. SC1_CD SmartCard1 card detect pin. EBI_DATA10 External I/O data bus bit 10. SD1_DAT3 SD/SDIO mode #1 data line bit 3. UART4_RXD Data receiver input pin for UART4.
Page 46 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type VCAP_DATA6 Sensor interface data bus bit 6. NAND_DATA6 NAND flash data bus bit 6. UART8_RTS Request to send output pin for UART8. SC0_PWR SmartCard0 power pin. EBI_DATA14 External I/O data bus bit 14.
Page 47 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type SPI1_SS1 2nd SPI1 chip select pin. TM1_CAP Enhanced TIMER capture input pin. PB.2 General purpose digital I/O pin Port B Pin 2. UART6_TXD Data transmitter output pin for UART6. PWM0 PWM0 output pin.
Page 48 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type UART10_TXD Data transmitter output pin for UART10. SPI0_DATA2 SPI0 data 2 in dual/quad mode. CAN0_RXD CAN bus receiver0 input. PB.11 General purpose digital I/O pin Port B Pin 11. UART10_RXD Data receiver input pin for UART10.
Page 49 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type NAND_RDY1 NAND flash ready/busy channel 1. UART7_RXD Data receiver input pin for UART7. SPI1_DATA3 SPI1 data 3 in dual/quad mode. PC.0 General purpose digital I/O pin Port C Pin 0. NAND_DATA0 NAND flash data bus bit 0.
Page 50 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type PC.7 General purpose digital I/O pin Port C Pin 7. NAND_DATA7 NAND flash data bus bit 7. UART10_RXD Data receiver input pin for UART10. TM0_CAP Enhanced TIMER capture input pin. PC.8 General purpose digital I/O pin Port C Pin 8.
Page 51 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type NAND_RDY0 NAND flash ready/busy channel 0. UART4_CTS Clear to send input pin for UART4. TM3_CAP Enhanced TIMER capture input pin. PC.14 General purpose digital I/O pin Port C Pin 14. NAND_nWP NAND flash write protect.
Page 52 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type DDR_VDD DDR power pin. DDR_VSS DDR ground pin. DDR_VDD DDR power pin. DDR_VSS DDR ground pin. CORE_VSS MCU internal core ground pin. IO_VDD MCU I/O power pin. PD.0 General purpose digital I/O pin Port D Pin 0.
Page 53 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type PH.3 General purpose digital I/O pin Port H Pin 3. I2C1_SDA C1 data input/output pin. UART9_RXD Data receiver input pin for UART9. CAN0_TXD CAN bus transmitter0 output. PWM3 PWM3 output pin.
Page 54 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type PE.9 General purpose digital I/O pin Port E Pin 9. RMII1_RXDATA1 RMII1 receive data bus bit 1. SD1_nPWR SD/SDIO mode #1 power enable. UART1_CD Carrier detect input pin for UART1. PE.8 General purpose digital I/O pin Port E Pin 8.
Page 55 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type PE.3 General purpose digital I/O pin Port E Pin 3. RMII1_MDIO RMII1 Management Data I/O SD1_CLK SD/SDIO mode #1 clock. UART1_RXD Data receiver input pin for UART1. PE.2 General purpose digital I/O pin Port E Pin 2.
Page 56 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type RMII0_REFCLK RMII0 reference clock. PF.4 General purpose digital I/O pin Port F Pin 4. RMII0_TXEN RMII0 transmit enable. PF.3 General purpose digital I/O pin Port F Pin 3. RMII0_TXDATA1 RMII0 transmit data bus bit 1.
Page 57 NUC970 Technical Reference Manual NUC972D NUC976D NUC977D Pin Name Description FxxY KxxY KxxY Type CORE_VDD MCU internal core power pin. CORE_VDD MCU internal core power pin. USBPLL1_VDD USB1 PLL power pin. USB1_VSS USB1 ground pin. USB1_DM USB1 differential signal D-. USB1_DP USB1 differential signal D+.
Page 58: Block Diagram
SPI X 2, PIC Crystal Osc. High Speed Device 32.768 kHz (Touch Screen) C X 2 PLL x 2 Smart Card X 2 SDIO Figure 4.1-1 NUC970 Series Block Diagram Publication Release Date: Dec. 15, 2015 - 58 - Revision V1.30...
Page 59: Functional Description
NUC970 Technical Reference Manual FUNCTIONAL DESCRIPTION ® ARM926EJ-S CPU Core 5.1.1 Overview The ARM926EJ-S CPU core is a member of the ARM9 family of general-purpose microprocessors. The ARM926EJ-S CPU core is targeted at multi-tasking applications where full memory management, high performance, and low power are all important. The ARM926EJ-S CPU core supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to choose between high performance and high code density.
Page 60: System Control Coprocessor (Cp15)
NUC970 Technical Reference Manual ARM926EJ-S Processor Embedded ICE-RT Logic ARM9EJ-S Core Controller I-Cache D-Cache I-EXT D-EXT 16 kB 16 kB Bus Interface Unit Instruction Data JTAG AHB Interface AHB Interface Interface Figure 5.1-1 ARM926EJ-S Block Diagram 5.1.2 System Control Coprocessor (CP15) The system control coprocessor (CP15) is used to configure and control the ARM926EJ-S processor.
Page 61: Caches And Write Buffer
NUC970 Technical Reference Manual translation. The MMU puts the translated physical addresses into the MMU Translation Lookaside Buffer TLB. The MMU TLB has two parts, the main TLB and the lockdown TLB. The main TLB is a two-way, set-associative cache for page table information. It has 32 entries per way for a total of 64 entries. The lockdown TLB is an eight-entry fully-associative cache that contains locked TLB entries.
Page 62: Bus Interface Unit
NUC970 Technical Reference Manual 5.1.5 Bus Interface Unit The ARM926EJ-S Bus Interface Unit (BIU) arbitrates and schedules AHB requests. The BIU contains separate masters for both instruction and data access enabling complete AHB system flexibility. Each master is a fully compliant AHB bus master and implements the master functions as defined in the AMBA Specification (Rev 2.0).
Page 63: System Manager
NUC970 Technical Reference Manual System Manager 5.2.1 Overview The system management describes following information and functions.  System Resets  System Power Architecture  System Memory Map  System management registers for Product Identifier (PDID), Power-On Setting, System Wake-Up, Reset Control for on-chip controllers/peripherals, and multi-function pin control.
Page 64: System Power Distribution
IO power from DDR_VDD provides 1.8V to I/O pins used to connect DDR2 SDRAM.  IO power from IO_VDD provides 3.3V to MTP memory, HXT and I/O pins (PA ~ PJ). The following diagram shows the power distribution of the NUC970 series. DDR_VDD USB 2.0 PHY 0 USB 2.0 PHY 1...
Page 65: System Memory Map
NUC970 Technical Reference Manual 5.2.4 System Memory Map This chip support only little-endian data format and provides 4G-byte addressing space. The diagram shown below describes the memory space definition. The memory space from 0x0000_0000 to 0x2FFF_FFFF is for SDRAM and external devices. The memory space from 0x3C00_0000 to 0x3C00_DFFF is for embedded 56 k-byte SRAM.
Page 66 NUC970 Technical Reference Manual 0x7FFF_FFFF 0xFFFF_FFFF Reserved 0xFFFF_4000 Internal Boot ROM (IBR, 16 KB) 0xFFFF_0000 Reserved Reserved 0x4000_0000 0xC000_0000 Reserved Reserved 0x3C00_E000 0xBC00_E000 Internal SRAM (56 KB) Internal SRAM (56 KB) 0x3C00_0000 0xBC00_0000 On-Chip APB Peripherals Reserved 0xB800_0000 On-Chip AHB Peripherals 0x3000_0000 0xB000_0000 External Devices...
Page 67 NUC970 Technical Reference Manual The addressing space assigned to each on-chip controller or peripheral described in the table shown below. The detailed register definition, addressing space, and programming details will be described in the following sections. Addressing Space Token Modules SDRAM, External Devices and SRAM Memory Space 0x0000_0000 –...
Page 68: Table 5.2-1 Address Space Assignments For On-Chip Controllers
NUC970 Technical Reference Manual 0xB800_0500 – 0xB800_05FF UART5_BA UART 5 Control Registers 0xB800_0600 – 0xB800_06FF UART6_BA UART 6 Control Registers (High-Speed UART) 0xB800_0700 – 0xB800_07FF UART7_BA UART 7 Control Registers 0xB800_0800 – 0xB800_08FF UART8_BA UART 8 Control Registers (High-Speed UART) 0xB800_0900 –...
Page 69: Power-On Setting
NUC970 Technical Reference Manual 5.2.5 Power-On Setting After power on reset, Power-On setting registers are latched to configure this chip. The table shown below describes the definition of each power-on setting bit. Description Power-On Setting Register Power-On Setting Pin USB0_ID USB Port 0 Role Selection 0 = USB Port 0 act as a USB host.
Page 70 NUC970 Technical Reference Manual PA[9:8] NAND Flash ECC Type Selection 00 = NAND Flash ECC type is BCH T12. 01 = NAND Flash ECC type is BCH T15. PWRON[9:8] 10 = NAND Flash ECC type is BCH T24. 11 = Ignore Power-On Setting. Publication Release Date: Dec.
Page 71: Register Map
NUC970 Technical Reference Manual 5.2.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SYS Base Address: SYS_BA = 0xB000_0000 SYS_PDID SYS_BA+0x000 Product Identifier Register 0x0X30_D008 0xXXXX_XXXX SYS_PWRON SYS_BA+0x004 Power-On Setting Register SYS_LVRDCR SYS_BA+0x020 Low Voltage Reset &...
Page 72 NUC970 Technical Reference Manual SYS_GPE_MFP SYS_BA+0x094 GPIOE High Byte Multiple Function Control Register 0x0000_0000 SYS_GPF_MFP SYS_BA+0x098 GPIOF Low Byte Multiple Function Control Register 0x0000_0000 SYS_GPF_MFP SYS_BA+0x09C R/W GPIOF High Byte Multiple Function Control Register 0x0000_0000 SYS_GPG_MFP SYS_BA+0x0A0 GPIOG Low Byte Multiple Function Control Register 0x0000_0000 SYS_GPG_MFP SYS_BA+0x0A4...
Page 73: Register Description
NUC970 Technical Reference Manual 5.2.7 Register Description Publication Release Date: Dec. 15, 2015 - 73 - Revision V1.30...
Page 74 NUC970 Technical Reference Manual Product Identifier Register (SYS_PDID) Register Offset Description Reset Value SYS_PDID SYS_BA+0x000 Product Identifier Register 0xXX30_D008 Reserved PRDNUML6 PRDNUML5 PRDNUML4 PRDNUML3 PRDNUML2 PRDNUML1 Bits Description [31:24] Reserved Reserved. Product Number Letter 6 0 = D. [23:20] PRDNUML6 1 = F.
Page 75 NUC970 Technical Reference Manual Power-On Setting Register (SYS_PWRON) Register Offset Description Reset Value SYS_PWRON SYS_BA+0x004 Power-On Setting Register 0xXXXX_XXXX Reserved Reserved TICMOD USBID Reserved NECCSEL NPAGESEL URDBGON JTAGON WDTON SYSCKSEL BTSSEL Bits Description [31:28] Reserved Reserved. Device ID (Read Only) 0000 = NUC970.
Page 76 NUC970 Technical Reference Manual NAND Flash Page Size Selection When pin nRESET transited from low to high, the value of pin PA[7:6] latched to NPAGESEL. 00= NAND Flash page size is 2KB. [7:6] NPAGESEL 01= NAND Flash page size is 4KB. 10= NAND Flash page size is 8KB.
Page 77 NUC970 Technical Reference Manual Low Voltage Reset & Detect Control Register (SYS_LVRDCR) Register Offset Description Reset Value SYS_LVRDCR SYS_BA+0x020 Low Voltage Reset & Detect Control Register 0x0000_0001 Reserved Reserved Reserved LVD_SEL LVD_EN Reserved LVR_EN Bits Description [31:10] Reserved Reserved. Low Voltage Detect Threshold Selection LVD_SEL 0: Low voltage detection level is 2.6V 1: Low voltage detection level is 2.8V...
Page 78 NUC970 Technical Reference Manual Miscellaneous Function Control Register (SYS_MISCFCR) Register Offset Description Reset Value SYS_MISCFCR SYS_BA+0x030 Miscellaneous Function Control Register 0x0000_0200 Reserved Reserved UPHY1MEN UPHY0MEN Reserved GPIOLBEN USRHDSEN CAPEMAC1SWAP HDSPUEN WDTRSTEN Reserved TDESKYS AESKYS Bits Description [31:16] Reserved Reserved. USB PHY 1 Monitor Enable [15] UPHY1MEN 0 = USB 2.0 port 1 PHY monitor mode Disabled.
Page 79 NUC970 Technical Reference Manual WatchDog Timer Reset Connection Enable This bit is use to enable the function that connect watch-dog timer reset to nRESET pin. If this bit is enabled, the watch-dog timer reset is connected to nRESET pin internally WDTRSTEN 0 = Watch-dog timer reset not connected to nRESET pin internally.
Page 80 NUC970 Technical Reference Manual Miscellaneous Interrupt Enable Register (SYS_MISCIER) Register Offset Description Reset Value SYS_MISCIER SYS_BA+0x040 Miscellaneous Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved USBIDC_IEN LVD_IEN Bits Description [31:2] Reserved Reserved. USB0_ID Pin Status Change Interrupt Enable USBIDC_IEN 0 = Disable HDS status change interrupt. 1 = Enable HDS status change interrupt.
Page 81 NUC970 Technical Reference Manual Miscellaneous Interrupt Status Register (SYS_MISCISR) Register Offset Description Reset Value SYS_MISCISR SYS_BA+0x044 Miscellaneous Interrupt Status Register 0x0001_0000 Reserved Reserved USB0_IDS IBR_RUN_F Reserved Reserved USBIDC_IS LVD_IS Bits Description [31:18] Reserved Reserved. USB0_ID Status [17] USB0_IDS 0 = USB port 0 used as a USB device port. 1 = USB port 0 used as a USB host port.
Page 82 NUC970 Technical Reference Manual System Wakeup Source Enable Register (SYS_WKUPSER) Register Offset Description Reset Value SYS_WKUPSE SYS_BA+0x058 System Wakeup Source Enable Register 0x0000_0000 USBH USBD Reserved GPIO ETIMER3 ETIMER2 ETIMER1 ETIMER0 CAN1 CAN0 EMAC1 EMAC0 Reserved UART10 UART8 UART6 UART4 UART2 UART1 EINT7...
Page 83 NUC970 Technical Reference Manual Enhanced Timer 3 Wake System Up Enable [23] ETIMER3 0 = Enhanced Timer 3 wake system up function disabled. 1 = Enhanced Timer 3 wake system up function enabled. Enhanced Timer 2 Wake System Up Enable ETIMER2 0 = Enhanced Timer 2 wake system up function disabled.
Page 84 NUC970 Technical Reference Manual UART 2 Wake System Up Enable UART2 0 = UART 2 wake system up function disabled. 1 = UART 2 wake system up function enabled. UART 1 Wake System Up Enable UART1 0 = UART 1 wake system up function disabled. 1 = UART 1 wake system up function enabled.
Page 85 NUC970 Technical Reference Manual System Wakeup Source Status Register (SYS_WKUPSSR) Register Offset Description Reset Value SYS_WKUPSS SYS_BA+0x05C System Wakeup Source Status Register 0x0000_0000 USBH USBD Reserved GPIO ETIMER3 ETIMER2 ETIMER1 ETIMER0 CAN1 CAN0 EMAC1 EMAC0 Reserved UART10 UART8 UART6 UART4 UART2 UART1 EINT7...
Page 86 NUC970 Technical Reference Manual Enhanced Timer 3 Wake System Up Status [23] ETIMER3 0 = Enhanced Timer 3 didn’t wake system up. 1 = Enhanced Timer 3 waked system up. Enhanced Timer 2 Wake System Up Status ETIMER2 0 = Enhanced Timer 2 didn’t wake system up. [22] 1 = Enhanced Timer 2 waked system up.
Page 87 NUC970 Technical Reference Manual UART 2 Wake System Up Status UART2 0 = UART 2 didn’t wake system up. 1 = UART 2 waked system up. UART 1 Wake System Up Status UART1 0 = UART 1 didn’t wake system up. 1 = UART 1 waked system up.
Page 88 NUC970 Technical Reference Manual AHB IP Reset Control Register (SYS_AHBIPRST) Register Offset Description Reset Value SYS_AHBIPRS SYS_BA+0x060 AHB IP Reset Control Register 0x0000_0000 Reserved SDIO CRYPTO JPEG GE2D USBD USBH EMAC1 EMAC0 Reserved Reserved GDMA CPU_PLS Reserved CHIP Bits Description [31:25] Reserved Reserved.
Page 89 NUC970 Technical Reference Manual Ethernet MAC 1 Reset Enable [17] EMAC1 0 = Ethernet MAC 1 reset disabled. 1 = Ethernet MAC 1 reset enabled. Ethernet MAC 0 Reset Enable EMAC0 0 = Ethernet MAC 0 reset disabled. [16] 1 = Ethernet MAC 0 reset enabled. [15:11] Reserved Reserved.
Page 90 NUC970 Technical Reference Manual APB IP Reset Control Register 0 (SYS_APBIPRST0) Register Offset Description Reset Value SYS_APBIPRS SYS_BA+0x064 APB IP Reset Control Register 0 0x0000_0000 Reserved UART10 UART9 UART8 UART7 UART6 UART5 UART4 UART3 UART2 UART1 UART0 Reserved TIMER4 TIMER3 TIMER2 TIMER1 TIMER0...
Page 91 NUC970 Technical Reference Manual UART 3 Reset Enable [19] UART3 0 = UART 3 reset disabled. 1 = UART 3 reset enabled. UART 2 Reset Enable UART2 0 = UART 2 reset disabled. [18] 1 = UART 2 reset enabled. UART 1 Reset Enable UART1 [17]...
Page 92 NUC970 Technical Reference Manual GPIO Reset Enable GPIO 0 = GPIO reset disabled. 1 = GPIO reset enabled. [2:0] Reserved Reserved. Publication Release Date: Dec. 15, 2015 - 92 - Revision V1.30...
Page 93 NUC970 Technical Reference Manual APB IP Reset Control Register 1 (SYS_APBIPRST1) Register Offset Description Reset Value SYS_APBIPRS SYS_BA+0x068 APB IP Reset Control Register 1 0x0000_0000 Reserved MTPC Reserved Reserved SMC1 SMC0 Reserved CAN1 CAN0 Reserved SPI1 SPI0 Reserved I2C1 I2C0 Bits Description [31:28]...
Page 94 NUC970 Technical Reference Manual CAN 1 Reset Enable CAN1 0 = CAN 1 reset disabled. 1 = CAN 1 reset enabled. CAN 0 Reset Enable CNA0 0 = CAN 0 reset disabled. 1 = CAN 0 reset enabled. [7:6] Reserved Reserved.
Page 95 NUC970 Technical Reference Manual Reset Source Active Status Register (SYS_RSTSTS) Register Offset Description Reset Value SYS_RSTSTS SYS_BA+0x06C Reset Source Active Status Register 0x0000_00XX Reserved Reserved Reserved Reserved KPIRSTS WDTRSTS CPURSTS CHIPRSTS LVRRSTS PINRSTS PORRSTS Bits Description [31:7] Reserved Reserved. Chip Reset by KPI Status KPIRSTS 0 = No reset from KPI.
Page 96 NUC970 Technical Reference Manual GPIOA Low Byte Multiple Function Control Register (SYS_GPA_MFPL) Register Offset Description Reset Value SYS_GPA_MF SYS_BA+0x070 GPIOA Low Byte Multiple Function Control Register 0x0000_0000 MFP_GPA7 MFP_GPA6 MFP_GPA5 MFP_GPA4 MFP_GPA3 MFP_GPA2 MFP_GPA1 MFP_GPA0 Bits Description Pin PA.7 Multi Function Selection 0000 = PA.7.
Page 97 NUC970 Technical Reference Manual Pin PA.2 Multi Function Selection 0000 = PA.2. [11:8] MFP_GPA2 0010 = LCD_DATA2. Others = PA.2. Pin PA.1 Multi Function Selection 0000 = PA.1. [7:4] MFP_GPA1 0010 = LCD_DATA1. Others = PA.1. Pin PA.0 Multi Function Selection 0000 = PA.0.
Page 98 NUC970 Technical Reference Manual GPIOA High Byte Multiple Function Control Register (SYS_GPA_MFPH) Register Offset Description Reset Value SYS_GPA_MF SYS_BA+0x074 GPIOA High Byte Multiple Function Control Register 0x0000_0000 MFP_GPA15 MFP_GPA14 MFP_GPA13 MFP_GPA12 MFP_GPA11 MFP_GPA10 MFP_GPA9 MFP_GPA8 Bits Description Pin PA.15 Multi Function Selection 0000 = PA.15.
Page 99 NUC970 Technical Reference Manual Pin PA.11 Multi Function Selection 0000 = PA.11. [15:12] MFP_GPA11 0010 = LCD_DATA11. 0100 = KPI_COL3. Others = PA.11. Pin PA.10 Multi Function Selection 0000 = PA.10. [11:8] MFP_GPA10 0010 = LCD_DATA10. 0100 = KPI_COL2. Others = PA.10. Pin PA.9 Multi Function Selection 0000 = PA.9.
Page 100 NUC970 Technical Reference Manual GPIOB Low Byte Multiple Function Control Register (SYS_GPB_MFPL) Register Offset Description Reset Value SYS_GPB_MF SYS_BA+0x078 GPIOB Low Byte Multiple Function Control Register 0x0000_0000 MFP_GPB7 MFP_GPB6 MFP_GPB5 MFP_GPB4 MFP_GPB3 MFP_GPB2 MFP_GPB1 MFP_GPB0 Bits Description Pin PB.7 Multi Function Selection 0000 = PB.7.
Page 101 NUC970 Technical Reference Manual Pin PB.2 Multi Function Selection 0000 = PB.2. 1001 = UR6_TXD. [11:8] MFP_GPB2 1101 = PWM0. 1111 = ETMR0_TGL. Others = PB.2. Pin PB.1 Multi Function Selection 0000 = PB.1. 0101 = NAND_RDY1. [7:4] MFP_GPB1 1001 = UR5_RXD. 1011 = SPI1_SS1.
Page 102 NUC970 Technical Reference Manual GPIOB High Byte Multiple Function Control Register (SYS_GPB_MFPH) Register Offset Description Reset Value SYS_GPB_MF SYS_BA+0x07C GPIOB High Byte Multiple Function Control Register 0x0000_0000 MFP_GPB15 MFP_GPB14 MFP_GPB13 MFP_GPB12 MFP_GPB11 MFP_GPB10 MFP_GPB9 MFP_GPB8 Bits Description Pin PB.15 Multi Function Selection 0000 = PB.15.
Page 103 NUC970 Technical Reference Manual Pin PB.11 Multi Function Selection 0000 = PB.11. 1001 = UR10_RXD. [15:12] MFP_GPB11 1011 = SPI0_DATA3. 1100 = CAN0_TX. Others = PB.11. Pin PB.10 Multi Function Selection 0000 = PB.10. 1001 = UR10_TXD. [11:8] MFP_GPB10 1011 = SPI0_DATA2. 1100 = CAN0_RX.
Page 104 NUC970 Technical Reference Manual GPIOC Low Byte Multiple Function Control Register (SYS_GPC_MFPL) Register Offset Description Reset Value SYS_GPC_MF SYS_BA+0x080 GPIOC Low Byte Multiple Function Control Register 0x0000_0000 MFP_GPC7 MFP_GPC6 MFP_GPC5 MFP_GPC4 MFP_GPC3 MFP_GPC2 MFP_GPC1 MFP_GPC0 Bits Description Pin PC.7 Multi Function Selection 0000 = PC.7.
Page 105 NUC970 Technical Reference Manual Pin PC.3 Multi Function Selection 0000 = PC.3. [15:12] MFP_GPC3 0101 = NAND_DATA3. 0110 = eMMC_DATA3. Others = PC.3. Pin PC.2 Multi Function Selection 0000 = PC.2. [11:8] MFP_GPC2 0101 = NAND_DATA2. 0110 = eMMC_DATA2. Others = PC.2. Pin PC.1 Multi Function Selection 0000 = PC.1.
Page 106 NUC970 Technical Reference Manual GPIOC High Byte Multiple Function Control Register (SYS_GPC_MFPH) Register Offset Description Reset Value SYS_GPC_MF SYS_BA+0x084 GPIOC High Byte Multiple Function Control Register 0x0000_0000 Reserved MFP_GPC14 MFP_GPC13 MFP_GPC12 MFP_GPC11 MFP_GPC10 MFP_GPC9 MFP_GPC8 Bits Description [31:28] Reserved Reserved. Pin PC.14 Multi Function Selection 0000 = PC.14.
Page 107 NUC970 Technical Reference Manual Pin PC.10 Multi Function Selection 0000 = PC.10. 0101 = NAND_CLE. [11:8] MFP_GPC10 1001 = UR4_TXD. 1101 = ETMR2_TGL. Others = PC.10. Pin PC.9 Multi Function Selection 0000 = PC.9. 0101 = NAND_ALE. [7:4] MFP_GPC9 1001 = UR10_CTS. 1101 = ETMR1_CAP.
Page 108 NUC970 Technical Reference Manual GPIOD Low Byte Multiple Function Control Register (SYS_GPD_MFPL) Register Offset Description Reset Value SYS_GPD_MF SYS_BA+0x088 GPIOD Low Byte Multiple Function Control Register 0x0000_0000 MFP_GPD7 MFP_GPD6 MFP_GPD5 MFP_GPD4 MFP_GPD3 MFP_GPD2 MFP_GPD1 MFP_GPD0 Bits Description Pin PD.7 Multi Function Selection [31:28] MFP_GPD7 0000 = PD.7.
Page 109 NUC970 Technical Reference Manual Pin PD.1 Multi Function Selection 0000 = PD.1. [7:4] MFP_GPD1 0110 = SD0_CLK. Others = PD.1. Pin PD.0 Multi Function Selection 0000 = PD.0. [3:0] MFP_GPD0 0110 = SD0_CMD. Others = PD.0. Publication Release Date: Dec. 15, 2015 - 109 - Revision V1.30...
Page 110 NUC970 Technical Reference Manual GPIOD High Byte Multiple Function Control Register (SYS_GPD_MFPH) Register Offset Description Reset Value SYS_GPD_MF SYS_BA+0x08C GPIOD High Byte Multiple Function Control Register 0x0000_0000 MFP_GPD15 MFP_GPD14 MFP_GPD13 MFP_GPD12 MFP_GPD11 MFP_GPD10 MFP_GPD9 MFP_GPD8 Bits Description Pin PD.15 Multi Function Selection 0000 = PD.15.
Page 111 NUC970 Technical Reference Manual Pin PD.12 Multi Function Selection 0000 = PD.12. 0010 = LCD_DATA20. [19:16] MFP_GPD12 1001 = UR9_RXD. 1101 = PWM0. 1110 = EBI_nCS4. Others = PD.12. Pin PD.11 Multi Function Selection 0000 = PD.11. 0010 = LCD_DATA19. [15:12] MFP_GPD11 1001 = UR9_TXD.
Page 112 NUC970 Technical Reference Manual GPIOE Low Byte Multiple Function Control Register (SYS_GPE_MFPL) Register Offset Description Reset Value SYS_GPE_MFP SYS_BA+0x090 GPIOE Low Byte Multiple Function Control Register 0x0000_0000 MFP_GPE7 MFP_GPE6 MFP_GPE5 MFP_GPE4 MFP_GPE3 MFP_GPE2 MFP_GPE1 MFP_GPE0 Bits Description Pin PE.7 Multi Function Selection 0000 = PE.7.
Page 113 NUC970 Technical Reference Manual Pin PE.3 Multi Function Selection 0000 = PE.3. 0001 = RMII1_MDIO. [15:12] MFP_GPE3 0110 = SD1_CLK. 1001 = UR1_RXD. Others = PE.3. Pin PE.2 Multi Function Selection 0000 = PE.2. 0001 = RMII1_MDC. [11:8] MFP_GPE2 0110 = SD1_CMD. 1001 = UR1_TXD.
Page 114 NUC970 Technical Reference Manual GPIOE High Byte Multiple Function Control Register (SYS_GPE_MFPH) Register Offset Description Reset Value SYS_GPE_MFP SYS_BA+0x094 GPIOE High Byte Multiple Function Control Register 0x0000_0000 MFP_GPE15 MFP_GPE14 MFP_GPE13 MFP_GPE12 MFP_GPE11 MFP_GPE10 MFP_GPE9 MFP_GPE8 Bits Description Pin PE.15 Multi Function Selection 0000 = PE.15.
Page 115 NUC970 Technical Reference Manual Pin PE.10 Multi Function Selection 0000 = PE.10. [11:8] MFP_GPE10 0001 = RMII1_CRSDV. 1001 = UR8_TXD. Others = PE.10. Pin PE.9 Multi Function Selection 0000 = PE.9. 0001 = RMII1_RXDATA1. [7:4] MFP_GPE9 0110 = SD1_nPWR. 1001 = UR1_nCD. Others = PE.9.
Page 116 NUC970 Technical Reference Manual GPIOF Low Byte Multiple Function Control Register (SYS_GPF_MFPL) Register Offset Description Reset Value SYS_GPF_MFP SYS_BA+0x098 GPIOF Low Byte Multiple Function Control Register 0x0000_0000 MFP_GPF7 MFP_GPF6 MFP_GPF5 MFP_GPF4 MFP_GPF3 MFP_GPF2 MFP_GPF1 MFP_GPF0 Bits Description Pin PF.7 Multi Function Selection 0000 = PF.7.
Page 117 NUC970 Technical Reference Manual Pin PF.1 Multi Function Selection 0000 = PF.1. [7:4] MFP_GPF1 0001 = RMII0_MDIO. Others = PF.1. Pin PF.0 Multi Function Selection 0000 = PF.0. [3:0] MFP_GPF0 0001 = RMII0_MDC. Others = PF.0. Publication Release Date: Dec. 15, 2015 - 117 - Revision V1.30...
Page 118 NUC970 Technical Reference Manual GPIOF High Byte Multiple Function Control Register (SYS_GPF_MFPH) Register Offset Description Reset Value SYS_GPF_MFP SYS_BA+0x09C GPIOF High Byte Multiple Function Control Register 0x0000_0000 MFP_GPF15 MFP_GPF14 MFP_GPF13 MFP_GPF12 MFP_GPF11 MFP_GPF10 MFP_GPF9 MFP_GPF8 Bits Description Pin PF.15 Multi Function Selection 0000 = PF.15.
Page 119 NUC970 Technical Reference Manual Pin PF.11 Multi Function Selection 0000 = PF.11. 1001 = UR2_TXD. [15:12] MFP_GPF11 1101 = ETMR2_TGL. 1111 = EINT0. Others = PF.11. Pin PF.10 Multi Function Selection 0000 = PF.10. [11:8] MFP_GPF10 0111 = USBH_PPWR. Others = PF.10. Pin PF.9 Multi Function Selection 0000 = PF.9.
Page 120 NUC970 Technical Reference Manual GPIOG Low Byte Multiple Function Control Register (SYS_GPG_MFPL) Register Offset Description Reset Value SYS_GPG_MF SYS_BA+0x0A0 GPIOG Low Byte Multiple Function Control Register 0x0000_0000 MFP_GPG7 MFP_GPG6 MFP_GPG5 MFP_GPG4 MFP_GPG3 MFP_GPG2 MFP_GPG1 MFP_GPG0 Bits Description Pin PG.7 Multi Function Selection 0000 = PG.7.
Page 121 NUC970 Technical Reference Manual Pin PG.2 Multi Function Selection 0000 = PG.2. [11:8] MFP_GPG2 1000 = I2C1_SCL. Others = PG.2. Pin PG.1 Multi Function Selection 0000 = PG.1. [7:4] MFP_GPG1 1000 = I2C0_SDA. Others = PG.1. Pin PG.0 Multi Function Selection 0000 = PG.0.
Page 122 NUC970 Technical Reference Manual GPIOG High Byte Multiple Function Control Register (SYS_GPG_MFPH) Register Offset Description Reset Value SYS_GPG_MF SYS_BA+0x0A4 GPIOG High Byte Multiple Function Control Register 0x0000_0000 MFP_GPG15 MFP_GPG14 MFP_GPG13 MFP_GPG12 MFP_GPG11 MFP_GPG10 MFP_GPG9 MFP_GPG8 Bits Description Pin PG.15 Multi Function Selection 0000 = PG.15.
Page 123 NUC970 Technical Reference Manual Pin PG.11 Multi Function Selection 0000 = PG.11. 1000 = I2S_DATAO. [15:12] MFP_GPG11 1001 = UR6_TXD. 1010 = SMC0_CLK. Others = PG.11. Pin PG.10 Multi Function Selection 0000 = PG.10. [11:8] MFP_GPG10 1000 = I2S_SYSCLK. 1010 = SMC0_RST. Others = PG.10.
Page 124 NUC970 Technical Reference Manual GPIOH Low Byte Multiple Function Control Register (SYS_GPH_MFPL) Register Offset Description Reset Value SYS_GPH_MF SYS_BA+0x0A8 GPIOH Low Byte Multiple Function Control Register 0x0000_0000 MFP_GPH7 MFP_GPH6 MFP_GPH5 MFP_GPH4 MFP_GPH3 MFP_GPH2 MFP_GPH1 MFP_GPH0 Bits Description Pin PH.7 Multi Function Selection 0000 = PH.7.
Page 125 NUC970 Technical Reference Manual Pin PH.4 Multi Function Selection 0000 = PH.4. 0100 = KPI_ROW0. 1001 = UR1_TXD. [19:16] MFP_GPH4 1101 = RTC_TICK. 1110 = EBI_ADDR0. 1111 = EINT4. Others = PH.4. Pin PH.3 Multi Function Selection 0000 = PH.3. 1000 = I2C1_SDA.
Page 126 NUC970 Technical Reference Manual GPIOH High Byte Multiple Function Control Register (SYS_GPH_MFPH) Register Offset Description Reset Value SYS_GPH_MF SYS_BA+0x0AC GPIOH High Byte Multiple Function Control Register 0x0000_0000 MFP_GPH15 MFP_GPH14 MFP_GPH13 MFP_GPH12 MFP_GPH11 MFP_GPH10 MFP_GPH9 MFP_GPH8 Bits Description Pin PH.15 Multi Function Selection 0000 = PH.15.
Page 127 NUC970 Technical Reference Manual Pin PH.12 Multi Function Selection 0000 = PH.12. 0100 = KPI_COL4. 0110 = SD1_nCD. [19:16] MFP_GPH12 1001 = UR8_TXD. 1011 = SPI0_SS1. 1110 = EBI_ADDR8. Others = PH.12. Pin PH.11 Multi Function Selection 0000 = PH.11. 0100 = KPI_COL3.
Page 128 NUC970 Technical Reference Manual GPIOI Low Byte Multiple Function Control Register (SYS_GPI_MFPL) Register Offset Description Reset Value SYS_GPI_MFP SYS_BA+0x0B0 GPIOI Low Byte Multiple Function Control Register 0x0000_0000 MFP_GPI7 MFP_GPI6 MFP_GPI5 MFP_GPI4 MFP_GPI3 MFP_GPI2 MFP_GPI1 MFP_GPI0 Bits Description Pin PI.7 Multi Function Selection 0000 = PI.7.
Page 129 NUC970 Technical Reference Manual Pin PI.5 Multi Function Selection 0000 = PI.5. 0011 = VCAP_HSYNC. 0100 = SD1_CMD. 0101 = NAND_nWE. [23:20] MFP_GPI5 0110 = eMMC_CMD. 1001 = UR1_TXD. 1011 = SPI1_SS0. 1110 = EBI_DATA5. Others = PI.5. Pin PI.4 Multi Function Selection 0000 = PI.4.
Page 130 NUC970 Technical Reference Manual GPIOI High Byte Multiple Function Control Register (SYS_GPI_MFPH) Register Offset Description Reset Value SYS_GPI_MFP SYS_BA+0x0B4 GPIOI High Byte Multiple Function Control Register 0x0000_0000 MFP_GPI15 MFP_GPI14 MFP_GPI13 MFP_GPI12 MFP_GPI11 MFP_GPI10 MFP_GPI9 MFP_GPI8 Bits Description Pin PI.15 Multi Function Selection 0000 = PI.15.
Page 131 NUC970 Technical Reference Manual Pin PI.13 Multi Function Selection 0000 = PI.13. 0011 = VCAP_DATA5. 0100 = SD1_nPWR. MFP_GPI13 0101 = NAND_DATA5. [23:20] 1001 = UR8_RXD. 1010 = SMC0_DATA. 1110 = EBI_DATA13. Others = PI.13. Pin PI.12 Multi Function Selection 0000 = PI.12.
Page 132 NUC970 Technical Reference Manual Pin PI.8 Multi Function Selection 0000 = PI.8. 0011 = VCAP_DATA0. 0100 = SD1_DATA1. 0101 = NAND_DATA0. [3:0] MFP_GPI8 0110 = eMMC_DATA0. 1001 = UR1_CTS. 1010 = SMC1_DATA. 1011 = SPI1_DATAI (SPI1_DATA1). 1110 = EBI_DATA8. Others = PI.8. Publication Release Date: Dec.
Page 133 NUC970 Technical Reference Manual GPIOJ Low Byte Multiple Function Control Register (SYS_GPJ_MFPL) Register Offset Description Reset Value SYS_GPJ_MFP SYS_BA+0x0B8 GPIOJ Low Byte Multiple Function Control Register 0x000X_XXXX Reserved Reserved MFP_GPJ4 MFP_GPJ3 MFP_GPJ2 MFP_GPJ1 MFP_GPJ0 Bits Description [31:20] Reserved Reserved. Pin PJ.4 Multi Function Selection 0000 = PJ.4.
Page 134 NUC970 Technical Reference Manual DDR I/O Driving Strength Control Register (SYS_DDR_DSCTL) Register Offset Description Reset Value SYS_DDR_DS SYS_BA+0x0F0 DDR I/O Driving Strength Control Register 0x0000_0000 Reserved Reserved Reserved DATA_DS ADDR_DS CTRL_DS CLK_DS Bits Description [31:8] Reserved Reserved. DDR Data I/O Driving Strength Selection This bit controls the driving strength for DDR I/O used as data.
Page 135 NUC970 Technical Reference Manual DDR Clock I/O Driving Strength Selection This bit controls the driving strength for DDR I/O used as clock. [1:0] CLK_DS 00 = Reserved. 01 = Reduced Strength. 10 = Reserved. 11 = Full Strength. Publication Release Date: Dec. 15, 2015 - 135 - Revision V1.30...
Page 136 NUC970 Technical Reference Manual Power-On-Reset Disable Control Register (SYS_PORDISCR) Register Offset Description Reset Value SYS_PORDISC SYS_BA+0x100 Power-On-Reset Disable Control Register 0x0000_00XX Reserved Reserved POR_DIS_CODE POR_DIS_CODE Bits Description [31:16] Reserved Reserved. Power-on-reset Disable Code (Write-protection Bits) When powered on, the Power-On-Reset (POR) circuit generates a reset signal to reset whole chip function.
Page 137 NUC970 Technical Reference Manual Register Write-Protection Control Register (SYS_REGWPCTL) Some of the system control registers need to be protected to avoid inadvertent write and disturb the chip operation. These system control registers are protected after the power-on reset till user to disable register protection.
Page 138 NUC970 Technical Reference Manual Register Write-protection Disable Indicator (Read Only) 0 = Write-protection Enabled for writing protected registers. Any write to the protected register is ignored. 1 = Write-protection Disabled for writing protected registers. The protected registers are: REGPRTDIS SYS_PDID: Product Identifier Register, address 0xB000_0000 SYS_MISCFCR: Miscellaneous Function Control Register, address 0xB000_0030 SYS_AHBIPRST: AHB IP Reset Control Register, address 0xB000_0060 SYS_APBIPRST0: APB IP Reset Control Register 0, address 0xB000_0064...
Page 139: Clock Controller (Clk_Ctl)
NUC970 Technical Reference Manual Clock Controller (CLK_CTL) 5.3.1 Overview The clock controller generates all clocks for Video, Audio, CPU, system bus and all functionalities. This chip includes two PLL modules. The clock source for each functionality comes from the PLL, or from the external crystal input directly.
Page 140: Block Diagram
NUC970 Technical Reference Manual 5.3.3 Block diagram 5.3.3.1 Clock Controller Top View Publication Release Date: Dec. 15, 2015 - 140 - Revision V1.30...
Page 141: Figure 5.3-1 Clock Controller Block Diagram
NUC970 Technical Reference Manual XT1_IN (12 MHz) ADC_CLK ADC_SW_DIV APLLF ADivCLK[7:0] APLL ECLK APLL1to8 ADO_SW_DIV ECLK LCD_SW_DIV UPLLF UDivCLK[7:0] UPLL UPLL1to8 SD_CLK SD_SW_DIV XIN32K (32.768 kHz) ECLK SEN_CLK TIMER0 SEN_SW_DIV ECLK TIMER1 ECLK ECLK TIMER2 UART0 UART0_SW_DIV ECLK TIMER3 ECLK ECLK TIMER4 UART1...
Page 142: Figure 5.3-2 Adc Controller Clock Divider Block Diagram
NUC970 Technical Reference Manual 5.3.3.2 ADC Controller Clock Divider XT1_IN CLK_DIVn APLLFout (÷ (ADC_SDIV+1)) ACLKOut CLK_SW4 ADC_CLK ADC_SDIV ADC_SrcCLK CLK_DIVn (4-to-1) (CLK_DIVCTL7[18:16]) (÷ (ADC_N+1)) (MUX) UCLKout CLK_DIVn UPLLFout (÷ (ADC_SDIV+1)) Note: Before clock switching, both the pre-selected and ADC_S ADC_N (CLK_DIVCTL7[20:19]) (CLK_DIVCTL7[31:24]) (CLK_PCLKEN1[24])
Page 143: Figure 5.3-5 Ethernet Mac Controller Clock Divider Block Diagram
NUC970 Technical Reference Manual 5.3.3.5 Ethernet MAC Controller Clock Divider x = 0, 1 RMIIx_REFCLK ÷ 2 (50 MHz) EMACx_RXCLK 25 MHz CLK_SW4 EMACx_SrcCLK (2-to-1) (MUX) EMACx_TXCLK 2.5 MHz ÷ 20 Note: Before clock switching, both the pre-selected and OPMOD EMACx (EMACx_MCMDR[20]) (CLK_HCLKEN[x+16])
Page 144: Figure 5.3-8 Kpi Controller Clock Divider Block Diagram
NUC970 Technical Reference Manual 5.3.3.8 KPI Controller Clock Divider XT1_IN (12 MHz) CLK_SW2 ECLK KPI_SrcCLK CLK_DIVn (2-to-1) (÷ (KPI_N+1)) (MUX) X32_IN (32.768 kHz) Note: Before clock switching, both the pre-selected and KPI_S KPI_N (CLK_DIVCTL7[15]) (CLK_DIVCTL7[14:8]) (CLK_PCLKEN1[25]) newly selected clock sources must be turned on and stable. Figure 5.3-8 KPI Controller Clock Divider Block Diagram 5.3.3.9 LCD Display Controller Clock Divider...
Page 145: Figure 5.3-11 Sd Card Host Controller Clock Divider Block Diagram
NUC970 Technical Reference Manual 5.3.3.11 SD Card Host Controller Clock Divider XT1_IN CLK_DIVn APLLFout (÷ (SDH_SDIV+1)) ACLKOut CLK_SW4 SDH_CLK SDH_SDIV SDH_SrcCLK CLK_DIVn (4-to-1) (CLK_DIVCTL9[2:0]) (÷ (SDH_N+1)) (MUX) UCLKout CLK_DIVn UPLLFout (÷ (SDH_SDIV+1)) Note: Before clock switching, both the pre-selected and SDH_S SDH_N (CLK_DIVCTL9[4:3])
Page 146: Figure 5.3-14 Uart Clock Divider Block Diagram
NUC970 Technical Reference Manual 5.3.3.14 UART Clock Divider x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 m = 4, 5, 6 XT1_IN CLK_DIVn APLLFout (÷ (UART _SDIV+1)) ACLKOut CLK_SW4 ECLK UART _SDIV UART _SrcCLK CLK_DIVn UARTx (4-to-1) (CLK_DIVCTLm)
Page 147: Figure 5.3-17 Windowed Watchdog Timer Clock Divider Block Diagram
NUC970 Technical Reference Manual 5.3.3.17 Windowed Watchdog Timer Clock Divider XT1_IN (12 MHz) XT1_IN/128 CLK_SW4 ECLK WWDT_SrcCLK WWDT (4-to-1) (MUX) PCLK/4096 X32_IN (32.768 kHz) Note: Before clock switching, both the pre-selected and WWDT_S WWDT (CLK_DIVCTL8[11:10]) (CLK_PCLKEN0[1]) newly selected clock sources must be turned on and stable. Figure 5.3-17 Windowed Watchdog Timer Clock Divider Block Diagram Publication Release Date: Dec.
Page 148: Figure 5.3-18 Cpu_Hclk Clock Generator Block Diagram
NUC970 Technical Reference Manual 5.3.3.18 CPU_HCLK Clock Generator DRAM (CLK_HCLKEN[10]) DDR_CLK APLL HCLK (CLK_HCLKEN[1]) APLLF ADivCLK[7:0] ÷ 2 APLL DRAM_CLK 1to8 ÷ 2 HCLK UPLL SRAM (CLK_HCLKEN[8]) HCLK SRAM UPLLF UDivCLK[7:0] UPLL ÷ 1to8 HCLK1 (CLK_HCLKEN[2]) | (HCLK234_N+1) HCLK3 (CLK_HCLKEN[3]) | XT1_IN HCLK4 (CLK_HCLKEN[4]) HCLK2...
Page 149: Functional Description
NUC970 Technical Reference Manual 5.3.4 Functional description 5.3.4.1 Power management This chip provides four power management scenarios, including Deep Power-down, Power-down, Idle and Normal Operating modes, to manage the power consumption. The peripheral clocks can be enabled / disabled individually by controlling the corresponding bit in CLKSEL control register. User can turn-off the unused modules’...
Page 150 NUC970 Technical Reference Manual 5.3.4.5 Deep Power-down Mode To extremely reduce the power consumption, user could put the chip inot Deep Power-down mode without SRAM retention by turning off power supply to all power pin except RTC_VDD. In this mode, only RTC circuit and LXT (Ext.
Page 151: Registers Map
NUC970 Technical Reference Manual 5.3.5 Registers Map R: read only, W: write only, R/W: both read and write. Register Offset Description Reset Value CLK Base Address: CLK_BA = 0xB000_0200 CLK_PMCON CLK_BA+0x000 R/W Power Management Control Register 0xFFFF_FF03 CLK_HCLKEN CLK_BA+0x010 R/W AHB Devices Clock Enable Control Register 0x0000_0527 CLK_PCLKEN0 CLK_BA+0x018 R/W...
Page 152: Register Description
NUC970 Technical Reference Manual 5.3.6 Register description Publication Release Date: Dec. 15, 2015 - 152 - Revision V1.30...
Page 153 NUC970 Technical Reference Manual Power Management Control Register (CLK_PMCON) The chip clock source is from an external crystal. The crystal oscillator can be control on/off by the register XTAL_EN. When turn off the crystal, the chip into power down state. To avoid outputting an unstable clock to system, clock controller implements a pre-scalar counter.
Page 154 NUC970 Technical Reference Manual AHB Devices Clock Enable Control Register (CLK_HCLKEN) Register Offset Description Reset Value CLK_HCLKEN CLK_BA+0x010 AHB Devices Clock Enable Control Register 0x0000_0527 Reserved JPEG GE2D SENSOR CRYPTO eMMC NAND USBD USBH EMAC1 EMAC0 Reserved GDMA Reserved SRAM Reserved PCLK HCLK4...
Page 155 NUC970 Technical Reference Manual Crypto Engine Clock Enable [23] CRYPTO 0 = Crypto engine clock disabled. 1 = Crypto engine clock enabled. eMMC Engine Clock Enable eMMC 0 = eMMC controller clock disabled. [22] 1 = eMMC controller clock enabled. NAND Engine Clock Enable NAND [21]...
Page 156 NUC970 Technical Reference Manual TIC Clock Enable 0 = TIC clock disabled. 1 = TIC clock enabled. Reserved Reserved. Internal APB Bus Clock Enable PCLK 0 = Internal APB bus clock disabled. 1 = Internal APB bus clock enabled. Internal AHB-4 Bus Clock Enable HCLK4 0 = Internal AHB-4 bus clock disabled.
Page 157 NUC970 Technical Reference Manual APB Devices Clock Enable Control Register 0 (CLK_PCLKEN0) Register Offset Description Reset Value CLK_PCLKEN0 CLK_BA+0x018 APB Devices Clock Enable Control Register 0 0x0000_0000 Reserved UART10 UART9 UART8 UART7 UART6 UART5 UART4 UART3 UART2 UART1 UART0 Reserved TIMER4 TIMER3 TIMER2...
Page 158 NUC970 Technical Reference Manual UART 3 Clock Enable [19] UART3 0 = UART 3 clock disabled. 1 = UART 3 clock enabled. UART 2 Clock Enable UART2 0 = UART 2 clock disabled. [18] 1 = UART 2 clock enabled. UART 1 Clock Enable UART1 [17]...
Page 159 NUC970 Technical Reference Manual GPIO Controller Clock Enable GPIO 0 = GPIO controller clock disabled. 1 = GPIO controller clock enabled. RTC Clock Enable 0 = RTC clock disabled. 1 =RTC clock enabled. Windowed Watch-dog Clock Enable WWDT 0 = Windowed Watch-dog clock disabled. 1 = Windowed Watch-dog clock enabled.
Page 160 NUC970 Technical Reference Manual APB Devices Clock Enable Control Register 1 (CLK_PCLKEN1) Register Offset Description Reset Value CLK_PCLKEN1 CLK_BA+0x01C APB Devices Clock Enable Control Register 1 0x0000_0000 Reserved MTPC Reserved Reserved SMC1 SMC0 Reserved CAN1 CAN0 Reserved SPI1 SPI0 Reserved I2C1 I2C0 Bits...
Page 161 NUC970 Technical Reference Manual CAN 0 Clock Enable CAN0 0 = CAN 0 clock disabled. 1 = CAN 0 clock enabled. [7:6] Reserved Reserved. SPI Interface 1 Clock Enable SPI1 0 = SPI Interface 1 clock disabled. 1 = SPI Interface 1 clock enabled. SPI Interface 0 Clock Enable SPI0 0 = SPI Interface 0 clock disabled.
Page 162 NUC970 Technical Reference Manual Clock Divider Control Register 0 (CLK_DIVCTL0) Register Offset Description Reset Value CLK_DIVCTL0 CLK_BA+0x020 Clock Divider Control Register 0 0x0100_00XX Reserved PCLK_N HCLK234_N CPU_N Reserved SYSTEM_N Reserved SYSTEM_S SYSTEM_SDIV Bits Description [31:28] Reserved Reserved. APB Clock Divider This field defines the clock divide number for clock divider to generate the PCLK for APB bus and controllers in APB bus.
Page 163 NUC970 Technical Reference Manual System Clock Source Selection This field selects which clock is used to be the source of system clock SYS_CLK. 00 = SYSTEM_SrcCLK is from XIN. [4:3] SYSTEM_S 01 = Reserved. 10 = SYSTEM_SrcCLK is from ACLKOut. 11 = SYSTEM_SrcCLK is from UCLKOut.
Page 164 NUC970 Technical Reference Manual Clock Divider Control Register 1 (CLK_DIVCTL1) Register Offset Description Reset Value CLK_DIVCTL1 CLK_BA+0x024 Clock Divider Control Register 1 0x0000_0000 I2S_N Reserved I2S_S I2S_SDIV LCD_N Reserved LCD_S LCD_SDIV Bits Description S Controller Clock Divider This field defines the clock divide number for clock divider to generate the engine clock for I controller.
Page 165 NUC970 Technical Reference Manual LCD Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for LCD display controller. 00 = LCD_SrcCLK is from XIN. [4:3] LCD_S 01 = Reserved. 10 = LCD_SrcCLK is from ACLKOut. 11 = LCD_SrcCLK is from UCLKOut.
Page 166 NUC970 Technical Reference Manual Clock Divider Control Register 2 (CLK_DIVCTL2) Register Offset Description Reset Value CLK_DIVCTL2 CLK_BA+0x028 Clock Divider Control Register 2 0x0000_0000 Reserved GE2D_N Reserved Reserved Reserved USB_N Reserved USB_S Reserved Bits Description [31:30] Reserved Reserved. GE2D Engine Clock Divider This field defines the clock divide number for clock divider to generate the engine clock for GE2D codec.
Page 167 NUC970 Technical Reference Manual Clock Divider Control Register 3 (CLK_DIVCTL3) Register Offset Description Reset Value CLK_DIVCTL3 CLK_BA+0x02C Clock Divider Control Register 3 0x0000_0000 Reserved JPG_N SENSOR_N Reserved SENSOR_S SENSOR_SDIV eMMC_N Reserved eMMC_S eMMC_SDIV Bits Description JPEG Engine Clock Divider This field defines the clock divide number for clock divider to generate the engine clock for JPEG codec.
Page 168 NUC970 Technical Reference Manual eMMC Engine Clock Divider This field defines the clock divide number for clock divider to generate the engine clock for eMMC controller. eMMC_N [15:8] The actual clock divide number is (eMMC_N + 1). So, eMMC_CLK = eMMC_SrcCLK / (eMMC_N + 1). Reserved [7:5] Reserved.
Page 169 NUC970 Technical Reference Manual Clock Divider Control Register 4 (CLK_DIVCTL4) Register Offset Description Reset Value CLK_DIVCTL4 CLK_BA+0x030 Clock Divider Control Register 4 0x0000_0000 UART3_N UART3_S UART3_SDIV UART2_N UART2_S UART2_SDIV UART1_N UART1_S UART1_SDIV UART0_N UART0_S UART0_SDIV Bits Description UART3 Engine Clock Divider This field defines the clock divide number for clock divider to generate the engine clock for UART3.
Page 170 NUC970 Technical Reference Manual UART2 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART2 controller. 00 = UART2_SrcCLK is from XIN [20:19] UART2_S 01 = Reserved 10 = UART2_SrcCLK is from ACLKOut 11 = UART2_SrcCLK is from UCLKOut UART2 Engine Source Clock Divider This field defines the source clock divide number for clock divider of APLL and UPLL output.
Page 171 NUC970 Technical Reference Manual UART0 Engine Source Clock Divider This field defines the source clock divide number for clock divider of APLL and UPLL output. This field only takes effect while the UART0_S (CLK_DIVCTL4[4:3]) is 2’b10 (APLL) or 2’b11 (UPLL). If UART0_S (CLK_DIVCTL4[5:4]) is 2’b10, [2:0] ACLKOut = APLLFout ÷...
Page 172 NUC970 Technical Reference Manual Clock Divider Control Register 5 (CLK_DIVCTL5) Register Offset Description Reset Value CLK_DIVCTL5 CLK_BA+0x034 Clock Divider Control Register 5 0x0000_0000 UART7_N UART7_S UART7_SDIV UART6_N UART6_S UART6_SDIV UART5_N UART5_S UART5_SDIV UART4_N UART4_S UART4_SDIV Bits Description UART7 Engine Clock Divider This field defines the clock divide number for clock divider to generate the engine clock for UART7.
Page 173 NUC970 Technical Reference Manual UART6 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART6 controller. 00 = UART6_SrcCLK is from XIN. [20:19] UART6_S 01 = Reserved. 10 = UART6_SrcCLK is from ACLKOut. 11 = UART6_SrcCLK is from UCLKOut.
Page 174 NUC970 Technical Reference Manual UART4 Engine Source Clock Divider This field defines the source clock divide number for clock divider of APLL and UPLL output. This field only takes effect while the UART4_S (CLK_DIVCTL5[4:3]) is 2’b10 (APLL) or 2’b11 (UPLL). If UART4_S (CLK_DIVCTL5[4:3]) is 2’b10, [2:0] UART4_SDIV...
Page 175 NUC970 Technical Reference Manual Clock Divider Control Register 6 (CLK_DIVCTL6) Register Offset Description Reset Value CLK_DIVCTL6 CLK_BA+0x038 Clock Divider Control Register 6 0x0000_0000 SMC1_N SMC0_N UART10_N UART10_S UART10_SDIV UART9_N UART9_S UART9_SDIV UART8_N UART8_S UART8_SDIV Bits Description Smart Card 1 Engine Clock Divider This field defines the clock divide number for clock divider to generate the engine clock for Smart card controller.
Page 176 NUC970 Technical Reference Manual UART10 Engine Source Clock Divider This field defines the source clock divide number for clock divider of APLL and UPLL output. This field only takes effect while the UART10_S (CLK_DIVCTL6[20:19]) is 2’b10 (APLL) or 2’b11 (UPLL). [18:16] UART10_SDIV If UART10_S (CLK_DIVCTL6[20:19]) is 2’b10,...
Page 177 NUC970 Technical Reference Manual Clock Divider Control Register 7 (CLK_DIVCTL7) Register Offset Description Reset Value CLK_DIVCTL7 CLK_BA+0x03C Clock Divider Control Register 7 0x0000_0000 ADC_N Reserved ADC_S ADC_SDIV KPI_S KPI_N GPIO_S GPIO_N Bits Description ADC Engine Clock Divider This field defines the clock divide number for clock divider to generate the engine clock for ADC. ADC_N [31:24] The actual clock divide number is (ADC_N + 1).
Page 178 NUC970 Technical Reference Manual KPI Engine Clock Divider This field defines the clock divide number for clock divider to generate the engine clock for KPI controller. KPI_N [14:8] The actual clock divide number is (KPI_N + 1). So, ECLKkpi = KPI_SrcCLK / (KPI_N + 1). GPIO Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for GPIO controller.
Page 179 NUC970 Technical Reference Manual Clock Divider Control Register 8 (CLK_DIVCTL8) Register Offset Description Reset Value CLK_DIVCTL8 CLK_BA+0x040 Clock Divider Control Register 8 0x0000_0500 Reserved ETIMER3_S Reserved ETIMER2_S Reserved ETIMER1_S Reserved ETIMER0_S Reserved WWDT_S WDT_S MDCLK_N Bits Description Enhanced Timer 3 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for Enhanced Timer 3 controller.
Page 180 NUC970 Technical Reference Manual Enhanced Timer 0 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for Enhanced Timer 0 controller. 00: ETIMER0_SrcCLK = XIN. [17:16] ETIMER0_S 01: ETIMER0_SrcCLK = PCLK. 10: ETIMER0_SrcCLK = PCLK/4096.
Page 181 NUC970 Technical Reference Manual Clock Divider Control Register 9 (CLK_DIVCTL9) Register Offset Description Reset Value CLK_DIVCTL9 CLK_BA+0x044 Clock Divider Control Register 9 0x0000_0000 CKO_N Reserved CKO_S CKO_SDIV SDH_N Reserved SDH_S SDH_SDIV Bits Description Reference Clock Out Divide This field defines the clock divide number for clock divider to generate the reference clock output [31:24] CKO_N The actual clock divide number is (CKO_N + 1).
Page 182 NUC970 Technical Reference Manual SD Host Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for SD host controller. 00 = SDH_SrcCLK is from XIN. [4:3] SDH_S 01 = Reserved. 10 = SDH_SrcCLK is from ACLKOut. 11 = SDH_SrcCLK is from UCLKOut.
Page 183 NUC970 Technical Reference Manual APLL Control Register (CLK_APLLCON), UPLL Control Register (CLK_UPLLCON) Register Offset Description Reset Value CLK_APLLCON CLK_BA+0x060 APLL Control Register 0x1000_0015 CLK_UPLLCON CLK_BA+0x064 UPLL Control Register 0xX000_0015 PLL_STB RESETN BYPASS FRAC FRAC OUT_DV IN_DV IN_DV FB_DV Bits Description PLL Stable Flag [31] PLL_STB...
Page 184 NUC970 Technical Reference Manual Reference Input Divider Set the reference divider factor (M) from 1 to 64. [12:7] IN_DV The M = IN_DV[5:0] + 1. PLL VCO Output Clock Feedback Divider Integer Part Set the feedback divider factor (N) from 1 to 128. [6:0] FB_DV The N = FB_DV[6:0] + 1.
Page 185 NUC970 Technical Reference Manual PLL Stable Counter and Test Clock Control Register (CLK_PLLSTBCNTR) Register Offset Description Reset Value CLK_PLLSTBC CLK_BA+0x080 PLL Stable Counter and Test Clock Control Register 0x0000_1800 Reserved Reserved PLLSTBCNT PLLSTBCNT Bits Description [31:24] Reserved Reserved. [15:0] PLLSTBCNT PLL Stable Counter Publication Release Date: Dec.
Page 186: Advanced Interrupt Controller (Aic)
NUC970 Technical Reference Manual Advanced Interrupt Controller (AIC) 5.4.1 Overview An interrupt temporarily changes the sequence of program execution to react to a particular event such as power failure, watchdog timer timeout, transmit/receive request from Ethernet MAC Controller, and so on. The CPU processor provides two modes of interrupt, the Fast Interrupt (FIQ) mode for critical session and the Interrupt (IRQ) mode for general purpose.
Page 187: Block Diagram
NUC970 Technical Reference Manual 5.4.3 Block Diagram VECTOR NUMBER AIC_CTRL Vector Wr_IPER Rd_IPER Generator PRIOR (AIC_ IVEC) OIRQ POLAR TRIG mask rstatus astatus status CLREDG prior_status Encoder Recorder (AIC_ status nIRQ (AIC_IREC) IENC) nFIQ Figure 5.4-1 Advanced Interrupt Controller (AIC) Block Diagram 5.4.4 Functional Description 5.4.4.1...
Page 188 NUC970 Technical Reference Manual updated to the higher priority. If the AIC_IPER has not been read after the NIRQ line has been asserted, then the processor will read the new higher priority interrupt vector in the AIC_IPER register and the current priority level is updated.
Page 189 NUC970 Technical Reference Manual If there is no enabled pending interrupt, the fake vector will be returned. If an enabled interrupt with a higher priority than the current one is pending, it will be stacked. In the second case, an End-of-Service command would be necessary to restore the state of the AIC. This operation is generally not performed by the debug system.
Page 190 NUC970 Technical Reference Manual External Interrupt 2 Positive Level External Interrupt 2 External Interrupt 3 Positive Level External Interrupt 3 External Interrupt 4 Positive Level External Interrupt 4 External Interrupt 5 Positive Level External Interrupt 5 External Interrupt 6 Positive Level External Interrupt 6 External Interrupt 7 Positive Level...
Page 191 NUC970 Technical Reference Manual UART6_INT Positive Level UART 6 Interrupt UART8_INT Positive Level UART 8 Interrupt UART10_INT Positive Level UART 10 Interrupt UART3_INT Positive Level UART 3 Interrupt UART5_INT Positive Level UART 5 Interrupt UART7_INT Positive Level UART 7 Interrupt UART9_INT Positive Level UART 9 Interrupt...
Page 192: Register Map
NUC970 Technical Reference Manual 5.4.5 Register Map Register Offset Description Reset Value AIC Base Address: AIC_BA = 0xB800_2000 AIC_SCR1 AIC_BA+0x000 AIC Source Control Register 1 0x4747_4747 AIC_SCR2 AIC_BA+0x004 AIC Source Control Register 2 0x4747_4747 AIC_SCR3 AIC_BA+0x008 AIC Source Control Register 3 0x4747_4747 AIC_SCR4 AIC_BA+0x00C R/W...
Page 193 NUC970 Technical Reference Manual AIC_MDCRH AIC_BA+0x13C W AIC Mask Disable Command Register (High) Undefined AIC_SSCR AIC_BA+0x140 AIC Source Set Command Register Undefined AIC_SSCRH AIC_BA+0x144 AIC Source Set Command Register (High) Undefined AIC_SCCR AIC_BA+0x148 AIC Source Clear Command Register Undefined AIC_SCCRH AIC_BA+0x14C W AIC Source Clear Command Register (High) Undefined...
Page 194: Register Description
NUC970 Technical Reference Manual 5.4.6 Register Description Publication Release Date: Dec. 15, 2015 - 194 - Revision V1.30...
Page 195 NUC970 Technical Reference Manual AIC Source Control Register (AIC_SCR1 ~ AIC_SCR16) Register Offset Description Reset Value AIC_SCR1 AIC_BA+0x000 AIC Source Control Register 1 0x4747_4747 AIC_SCR2 AIC_BA+0x004 AIC Source Control Register 2 0x4747_4747 AIC_SCR3 AIC_BA+0x008 AIC Source Control Register 3 0x4747_4747 AIC_SCR4 AIC_BA+0x00C AIC Source Control Register 4...
Page 196 NUC970 Technical Reference Manual [5:3] Reserved Reserved. Priority Level (0 – 7) The level 0 indicates the highest priority and the level 7 indicates the lowest priority. [2:0] PRIORITY An interrupt is treated as a FIQ for the priority level 0, and is treated as an IRQ for other levels. If two or more interrupts have the identical priority level, the interrupts located in the upper rows of the interrupt source table, have higher priorities.
Page 197 NUC970 Technical Reference Manual AIC Interrupt Raw Status Register (AIC_IRSR) Register Offset Description Reset Value AIC_IRSR AIC_BA+0x100 AIC Interrupt Raw Status Register 0x0000_0000 IRS31 IRS30 IRS29 IRS28 IRS27 IRS26 IRS25 IRS24 IRS23 IRS22 IRS21 IRS20 IRS19 IRS18 IRS17 IRS16 IRS15 IRS14 IRS13 IRS12...
Page 198 NUC970 Technical Reference Manual AIC Interrupt Raw Status Register (High) (AIC_IRSRH) Register Offset Description Reset Value AIC_IRSRH AIC_BA+0x104 AIC Interrupt Raw Status Register (High) 0x0000_0000 Reserved ISR61 ISR60 ISR59 ISR58 ISR57 IRS56 IRS55 IRS54 IRS53 IRS52 IRS51 IRS50 IRS49 IRS48 IRS47 IRS46 IRS45...
Page 199 NUC970 Technical Reference Manual AIC Interrupt Active Status Register (AIC_IASR) This register indicates the status of each interrupt channel in consideration of the interrupt source type as defined in the corresponding Source Control Register, but regardless of its mask setting. Register Offset Description...
Page 200 NUC970 Technical Reference Manual AIC Interrupt Active Status Register (High) (AIC_IASRH) This register indicates the status of each interrupt channel in consideration of the interrupt source type as defined in the corresponding Source Control Register, but regardless of its mask setting. Register Offset Description...
Page 201 NUC970 Technical Reference Manual AIC Interrupt Status Register (AIC_ISR) This register identifies those interrupt channels whose are both active and enabled. Register Offset Description Reset Value AIC_ISR AIC_BA+0x110 AIC Interrupt Status Register 0x0000_0000 IS31 IS30 IS29 IS28 IS27 IS26 IS25 IS24 IS23 IS22...
Page 202 NUC970 Technical Reference Manual AIC Interrupt Status Register (High) (AIC_ISRH) This register identifies those interrupt channels whose are both active and enabled. Register Offset Description Reset Value AIC_ISRH AIC_BA+0x114 AIC Interrupt Status Register (High) 0x0000_0000 Reserved IS61 IS60 IS59 IS58 IS57 IS56 IS55...
Page 203 NUC970 Technical Reference Manual AIC Interrupt Priority Encoding Register (AIC_IPER) When the AIC generates the interrupt, VECTOR represents the interrupt channel number that is active, enabled, and has the highest priority. If the representing interrupt channel possesses a priority level 0, then the interrupt asserted is FIQ; otherwise, it is IRQ. The value of VECTOR is copied to the register AIC_ISNR thereafter by the AIC.
Page 204 NUC970 Technical Reference Manual AIC Interrupt Source Number Register (AIC_ISNR) The purpose of this register is to record the interrupt channel number that is active, enabled, and has the highest priority. Register Offset Description Reset Value AIC_ISNR AIC_BA+0x120 AIC Interrupt Source Number Register 0x0000_0000 Reserved Reserved...
Page 205 NUC970 Technical Reference Manual AIC Output Interrupt Status Register (AIC_OISR) The AIC classifies the interrupt into FIQ and IRQ. This register indicates whether the asserted interrupt is FIQ or IRQ. If both IRQ and FIQ are equal to 0, it means there is no interrupt occurred. Register Offset Description...
Page 206 NUC970 Technical Reference Manual AIC Interrupt Mask Register (AIC_IMR) Register Offset Description Reset Value AIC_IMR AIC_BA+0x128 AIC Interrupt Mask Register 0x0000_0000 IM31 IM30 IM29 IM28 IM27 IM26 IM25 IM24 IM23 IM22 IM21 IM20 IM19 IM18 IM17 IM16 IM15 IM14 IM13 IM12 IM11 IM10...
Page 207 NUC970 Technical Reference Manual AIC Interrupt Mask Register (High) (AIC_IMRH) Register Offset Description Reset Value AIC_IMRH AIC_BA+0x12C AIC Interrupt Mask Register (High) 0x0000_0000 Reserved IM61 IM60 IM59 IM58 IM57 IM56 IM55 IM54 IM53 IM52 IM51 IM50 IM49 IM48 IM47 IM46 IM45 IM44 IM43...
Page 208 NUC970 Technical Reference Manual AIC Mask Enable Command Register (AIC_MECR) Register Offset Description Reset Value AIC_MECR AIC_BA+0x130 AIC Mask Enable Command Register Undefined MEC31 MEC30 MEC29 MEC28 MEC27 MEC26 MEC25 MEC24 MEC23 MEC22 MEC21 MEC20 MEC19 MEC18 MEC17 MEC16 MEC15 MEC14 MEC13 MEC12...
Page 209 NUC970 Technical Reference Manual AIC Mask Enable Command Register (High) (AIC_MECRH) Register Offset Description Reset Value AIC_MECRH AIC_BA+0x134 AIC Mask Enable Command Register (High) Undefined Reserved MEC61 MEC60 MEC59 MEC58 MEC57 MEC56 MEC55 MEC54 MEC53 MEC52 MEC51 MEC50 MEC49 MEC48 MEC47 MEC46 MEC45...
Page 210 NUC970 Technical Reference Manual AIC Mask Disable Command Register (AIC_MDCR) Register Offset Description Reset Value AIC_MDCR AIC_BA+0x138 AIC Mask Disable Command Register Undefined MDC31 MDC30 MDC29 MDC28 MDC27 MDC26 MDC25 MDC24 MDC23 MDC22 MDC21 MDC20 MDC19 MDC18 MDC17 MDC16 MDC15 MDC14 MDC13 MDC12...
Page 211 NUC970 Technical Reference Manual AIC Mask Disable Command Register (High) (AIC_MDCRH) Register Offset Description Reset Value AIC_MDCRH AIC_BA+0x13C AIC Mask Disable Command Register (High) Undefined Reserved MDC61 MDC60 MDC59 MDC58 MDC57 MDC56 MDC55 MDC54 MDC53 MDC52 MDC51 MDC50 MDC49 MDC48 MDC47 MDC46 MDC45...
Page 212 NUC970 Technical Reference Manual AIC Source Set Command Register (AIC_SSCR) When chip is under debugging or verification, software can activate any interrupt channel by setting the corresponding bit in this register. This feature is useful in hardware verification or software debugging.
Page 213 NUC970 Technical Reference Manual AIC Source Set Command Register (High) (AIC_SSCRH) When chip is under debugging or verification, software can activate any interrupt channel by setting the corresponding bit in this register. This feature is useful in hardware verification or software debugging.
Page 214 NUC970 Technical Reference Manual AIC Source Clear Command Register (AIC_SCCR) When the chip is under debugging or verification, software can deactivate any interrupt channel by setting the corresponding bit in this register. This feature is useful in hardware verification or software debugging.
Page 215 NUC970 Technical Reference Manual AIC Source Clear Command Register (High) (AIC_SCCRH) When the chip is under debugging or verification, software can deactivate any interrupt channel by setting the corresponding bit in this register. This feature is useful in hardware verification or software debugging.
Page 216 NUC970 Technical Reference Manual AIC End of Service Command Register (AIC_EOSCR) This register is used by the interrupt service routine to indicate that it is completely served. Thus, the interrupt handler can write any value to this register to indicate the end of its interrupt service. Register Offset Description...
Page 217: Sdram Interface Controller (Sdic)
NUC970 Technical Reference Manual SDRAM Interface Controller (SDIC) 5.5.1 Overview The SDRAM Controller support SDR, DDR, Low-Power DDR and DDR2 type SDRAM. The memory device size type can be from 16M bit and up to 1G bits. Only 16-bit data bus width is supported. The total system memory size can be from 2M bytes and up to 256M bytes for different SDRAM configuration.
Page 218: Block Diagram
NUC970 Technical Reference Manual 5.5.3 Block Diagram AHB 1 Bus AHB 4 Bus AHB 3 Bus AHB Slave AHB Slave AHB Slave Control Registers Wrapper Wrapper Wrapper (SdramReg) (AHBCtrl1) (AHBCtrl2) (AHBCtrl2) BIST Scheduler (SDRAM (ReqSchedule) _BIST) DRAM_SDR GMISC HCLK Bank Control Queue 0 Queue 1 (BankCtl)
Page 219: Basic Configuration
NUC970 Technical Reference Manual 5.5.4 Basic Configuration Before using SDRAM, please refer to SDRAM Power-Up Sequence section to initial SDRAM. After completing the SDRAM power-up sequence, the SDRAM could be access correctly. 5.5.5 Functional Description 5.5.5.1 SDRAM Control Timing The SDIC supports programmable CAS Latency and Refresh Rate control. It also can control the SDRAM to enter self-refresh mode to reduce the power consumption in power-down mode.
Page 220 NUC970 Technical Reference Manual 5.5.5.2 SDRAM Power-Up Sequence Before the SDRAM can be accessed for after power on, or when exiting deep power-down mode, an SDRAM device must be initialized by software to progress an initialization sequence. Because the DDR, DDR2 and LPDDR SDRAM require different initialization sequences and different parameters, the sequence is driven by software manually by using the registers SDIC_CMD, SDIC_MR, SDIC_EMR, SDIC_EMR2 and SDIC_EMR3.
Page 221 NUC970 Technical Reference Manual Set the SDRAM controller in initialization state. This is accomplished by writing 1 to InitState (SDIC_CMD[0]). Set the CKE_H (SDIC_CMD[1]) to be 1 to force the CKE at high state. Apply a PRECHARGE ALL command. This is accomplished by writing 1 to PALL_CMD (SDIC_CMD[2]).
Page 222 NUC970 Technical Reference Manual 128M 12x9 8Mx16 256M 13x9 16Mx16 512M 13x10 R 32Mx16 14x10 R 64Mx16 For DDR2 SDRAM Type R X C R/C BA2 BA1 BA0 A12 A11 A08 A07 128M 12x9 8Mx16 256M 13x9 16Mx16 512M 13x10 R 32Mx16 13x10 R 64Mx16...
Page 223: Register Map
NUC970 Technical Reference Manual 5.5.6 Register Map Register Offset Description Reset Value SDIC Base Address: SDIC_BA = 0xB000_1800 SDRAM Controller Operation Mode Control SDIC_OPMCTL SDIC_BA + 0x000 0x0003_04x6 Register SDIC_CMD SDIC_BA + 0x004 SDRAM Command Register 0x0000_0021 SDIC_REFCTL SDIC_BA + 0x008 SDRAM Controller Refresh Control Register 0x0000_80FF SDIC_SIZE0...
Page 224 NUC970 Technical Reference Manual SDRAM Controller Operation Mode Control Register (SDIC_OPMCTL) Register Offset Description Reset Value SDIC_OPMCTL SDIC_BA + 0x000 R/W SDRAM Controller Operation Mode Control Register 0x0003_04x6 Reserved Reserved RD2WR_CTL OEDelay LowFreq PreActBnk AutoPDn Reserved RDBUFTH Reserved SD_TYPE PchMode OPMode MCLKMode DRAM_EN...
Page 225 NUC970 Technical Reference Manual Pre-active Bank If this bit is enabled, the SDRAM controller will open request bank early to get better performance. It means maybe more than one bank active and consumes more power. There are several bus requests in this chip and the SDRAM controller checks all these requests simultaneous.
Page 226 NUC970 Technical Reference Manual Auto Pre-charge Mode This bit controls if SDRAM controller will pre-charge all active banks while there is no new memory request. The SDRAM power consumption increases with the active bank number. If no new memory access request, the active bank can be pre-charge to save power, but the SDRAM controller may lose some performance.
Page 227 NUC970 Technical Reference Manual SDRAM Command Register (SDIC_CMD) Register Offset Description Reset Value SDIC_CMD SDIC_BA + 0x004 SDRAM Command Register 0x0000_0021 Reserved Reserved Reserved Reserved AutoExSelfRef SELF_REF REF_CMD PALL_CMD CKE_H InitState Bits Description Reserved [31:6] Reserved. Auto Exit Self-refresh This controls if the SDRAM will exit self refresh mode automatically while the system interrupt occurred.
Page 228 NUC970 Technical Reference Manual CKE High This bit indicates the CKE is controlled by SDRAM controller state machine or always keeps high. CKE_H 0 = Set the CKE signal in normal state and controlled by the SDRAM controller state machine. (Default) 1 = Set the CKE signal keep in llerateed by.
Page 229 NUC970 Technical Reference Manual SDRAM Controller Refresh Control Register (SDIC_REFCTL) Register Offset Description Reset Value SDIC_REFCTL SDIC_BA + 0x008 SDRAM Controller Refresh Control Register 0x0000_80FF Reserved Reserved REF_EN REFRAT REFRAT Bits Description [31:24] Reserved Reserved. Refresh Period Counter Enable This bit controls if the refresh period counter is enabled. If refresh period counter is disabled, the SDRAM controller would never issue auto-refresh command to SDRAM automatically.
Page 230 NUC970 Technical Reference Manual SDRAM Size Register (SDIC_SIZE) Register Offset Description Reset Value SDIC_SIZE0 SDIC_BA + 0x010 SDRAM 0 Size Register 0x0000_000X SDIC_SIZE1 SDIC_BA + 0x014 SDRAM 1 Size Register 0x1000_0000 Reserved BASADDR BASADDR Reserved Reserved Reserved BUSWD DRAMSIZE Bits Description [31:29] Reserved...
Page 231 NUC970 Technical Reference Manual Size of SDRAM Device This field indicates the size of SDRAM device. The default memory size is 2MB or 16MB depend on power on setting value. If the power on setting value indicates the SDRAM type is DDR/DDR2, the default size is 16MB (8Mx16). Otherwise, the default size is 2MB (1Mx16).
Page 232 NUC970 Technical Reference Manual SDRAM Mode Register (SDIC_MR) The SDRAM mode registers is used to configure the Mode Register of SDRAM device. This Mode Register value will be applied to both SDRAM 0 and SDRAM 1 devices. Write this register, the SDRAM controller will generate a Load Mode Register (LMR) command to the SDRAM device.
Page 233 NUC970 Technical Reference Manual CAS Latency This field defines the CAS latency parameter of external SDRAM device. In this chip, SDRAM controller doesn’t support the mode CAS latency is 2.5. Setting CAS latency to be 2.5 is inhibited. For DDR2 SDRAM, SDRAM controller only support CAS latency is 3 or 4. Setting CAS latency to be 5 or 6 is inhibited.
Page 234 NUC970 Technical Reference Manual Burst Length This field defines the burst length of external SDRAM device. SDRAM controller only supports the burst length 4. Setting burst length to be other value is inhibited. Burst Length DDR2 1 (Inhibit) Reserved Reserved 2 (Inhibit) 2 (Inhibit) Reserved...
Page 235 NUC970 Technical Reference Manual SDRAM Extended Mode Register (SDIC_EMR) The SDRAM Extended Mode Register is used to configure SDRAM Extend Mode Register. This Extended Mode Register value will be applied to both SDRAM 0 and SDRAM 1 devices. Write this register, the SDRAM controller will generate a Load Mode Register (LMR) command to the SDRAM.
Page 236 NUC970 Technical Reference Manual SDRAM Extended Mode Register 2 (SDIC_EMR2) The SDRAM Extended Mode Register 2 is used to configure SDRAM Extend Mode Register 2. This Extended Mode Register 2 value will be applied to both SDRAM 0 and SDRAM 1 devices. Write this register, the SDRAM controller will generate a Load Mode Register (LMR) command to the SDRAM.
Page 237 NUC970 Technical Reference Manual SDRAM Extended Mode Register 3 (SDIC_EMR3) The SDRAM Extended Mode Register 3 is used to configure SDRAM Extend Mode Register 3. This Extended Mode Register 3 value will be applied to both SDRAM 0 and SDRAM 1 devices. Write this register, the SDRAM controller will generate a Load Mode Register (LMR) command to the SDRAM.
Page 238 NUC970 Technical Reference Manual SDRAM Timing Control Register (SDIC_TIME) This timing control register defines some SDRAM timing parameters that should be followed during SDRAM access. These timing parameters are SDRAM dependent. Refer SDRAM devicend related SDRAM specification to know what value should be c Register Offset Description...
Page 239 NUC970 Technical Reference Manual AUTO REFRESH Period This timing defines the minimum delay latency from AUTO-REFRESH command to any other command. [16:12] tRFC tRFC = tHCLK * (tRFC+1). HCLK: It’s the operating clock of SDRAM controller. ACTIVE to PRECHARGE Command Delay This timing defines the minimum delay latency from a valid ACTIVE command to PRECHARGE command.
Page 240 NUC970 Technical Reference Manual DQS Output Delay Selection Register (SDIC_DQSODS) This register controls the DQS output delay and source selection circuit for DQS0 and DQS1 output generation. This control register only takes effect while SDRAM type is DDR or DDR2. The function equivalent circuit for DQS output delay selection is shown below.
Page 241 NUC970 Technical Reference Manual [12:8] DQS1_ODS DQS1 Output Delay Selection This field controls the DQS1 output delay value and source selection circuit for DQS1 output generation. The brief circuit for this function is listed below. DQS1_ODS DQS1 Output 5’b0_0000 The DQS1 is generated from DRAM_CLK. 5’b0_0001 The DQS1 is generated from DRAM_CLK with a delay value.
Page 242: Figure 5.5-2 Clock Delay Circuit
NUC970 Technical Reference Manual DQS0 Output Delay Selection Circuit {DQS_OSD_is_16, DQS_ODS_is_0} DQS_ODS 5-bit Comparator DQS_ODS[4] DDR_CLK iDDR_CLK DDR_CLKD2 XNOR DQSInvEn iDRAM_CLK DRAM_CLK DQS0_CLKO DQS_ODS DQS_ODS[3:0] 4-to-16 Decoder Figure 5.5-2 Clock Delay Circuit Publication Release Date: Dec. 15, 2015 - 242 - Revision V1.30...
Page 243 NUC970 Technical Reference Manual Clock and DQS Delay Selection Register (SDIC_CKDQSDS) Register Offset R/W Description Reset Value SDIC_CKDQSDS SDIC_BA + 0x034 R/W Clock and DQS Delay Selection Register 0x0044_4400 Reserved DQS1_DS1 DQS1_DS0 DQS0_DS1 DQS0_DS0 DCLK_DS DCLKSrcSel MCLK_ODS Bits Description Reserved [31:24] Reserved.
Page 244 NUC970 Technical Reference Manual [11:8] DQS0_DS0 DQS0 Input Delay Selection 0 This field controls the DQS0 input delay selection circuit to generate a clock signal DQS00_CLKIn. DQS00_CLKIn is used to sample the data bits [3:0] outputted by SDRAM device. This field only takes effect while the SDRAM type is DDR or DDR2. This delay value is controlled by the following equation: DQS00_CLKIn delay = DQS0_DS0 * DelayCLKMUX.
Page 245 NUC970 Technical Reference Manual Data Latch Enable Selection Register (SDIC_DAENSEL) Register Offset R/W Description Reset Value SDIC_DAENSEL SDIC_BA + 0x038 R/W Data Latch Enable Selection Register 0x0000_0000 Reserved Reserved Reserved DALATDLY Resrved DALATDS Bits Description Reserved [31:8] Reserved. DALATDLY Data Latch Delay 1 MCLK Enable 0 = Data latch delay 1 MCLK Disabled.
Page 246: Mtp Controller (Mtp)
NUC970 Technical Reference Manual MTP Controller (MTP) 5.6.1 Overview The MTP (Multi-Time Programmable) controller performs an easy way to use and program the 256-bit Key for IP Security Engine. There is a MTP EPROM in this chip, and it can be programmed 15 times.
Page 247: Block Diagram
NUC970 Technical Reference Manual 5.6.3 Block Diagram APB BUS APB_BIU_REGS MTP Control Logics Cryptographic MTP Macro Accelerator Figure 5.6-1 MTP Controller Block Diagram Publication Release Date: Dec. 15, 2015 - 247 - Revision V1.30...
Page 248: Basic Configuration
NUC970 Technical Reference Manual PRESET_n MTP_PDOB MTP_PA PCLK PADDR MPT_PTM PWRITE MTP_PDIN macro interface PWDATA MTP_PWE interface signals PSEL MTP_PPROG signals PENABLE MTP_PRD PRDATA 256 bits MTP MISC DFT_mode MTP_KEY KEY output interface signals Figure 5.6-2 MTP INTERFACE PIN DESCRIPTION 5.6.4 Basic Configuration Before using MTP, it’s necessary to enable clock of MTP.
Page 249: Functional Description
NUC970 Technical Reference Manual 5.6.5 Functional Description MTP provide the software control MTP macro and provide Key to the Cryptographic Accelerator. User can follow the recommended programing flow, enable MTP or write key to MTP or lock the MTP. Publication Release Date: Dec. 15, 2015 - 249 - Revision V1.30...
Page 250: Software Programming Flow
NUC970 Technical Reference Manual 5.6.6 Software Programming Flow  Enable MTP  Enable MTP IP clock (in CLK_APB)  Write 0x59, 0x16, 0x88 to MTP_REGLCTL, check REGLCTL(MTP_REGLCTL[0]) show 0x1.  Write 0x1 to MTP_KEYEN to enable MTP function.  Read MTP_STATUS , check until MTPEN (MTP_STATUS[0]) is set ...
Page 251: Register Map
NUC970 Technical Reference Manual 5.6.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value MTP Base Address: MTP_BA = 0xB800_C000 MTP_KEYEN MTP_BA+0x000 MTP Key Enable Register 0x0000_0000 MTP_USERDATA MTP_BA+0x00c MTP User Defined Data Register 0x0000_0000 MTP_KEY0 MTP_BA+0x010...
Page 252: Register Description
NUC970 Technical Reference Manual 5.6.8 Register Description Publication Release Date: Dec. 15, 2015 - 252 - Revision V1.30...
Page 253 NUC970 Technical Reference Manual MTP KEYEN Register (MTP_KEYEN) Register Offset Description Reset Value MTP_KEYEN MTP_BA+0x000 MTP Key Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved KEYEN Bits Description [31:1] Reserved Reserved. MTP Key Enable KEYEN 0 = MTP Key . 1 = Enable MTP Key . Check MTPEN in MTP_STATUS Publication Release Date: Dec.
Page 254 NUC970 Technical Reference Manual MTP User Defined Data Register (MTP_USERDATA) Register Offset Description Reset Value MTP_USERDATA MTP_BA+0x00c MTP User Defined Data Register 0x0000_0000 Reserved Reserved Reserved UDAT Bits Description MTP User Defined Data Register 8 bits in MTP for software use. [7:0] UDAT When MTP in program key mode, write this register to program user defined...
Page 255 NUC970 Technical Reference Manual MTP Key Value Registers (MTP_KEY0 ~ MTP_KEY7) Register Offset Description Reset Value MTP_KEY0 MTP_BA+0x010 MTP KEY Value 0 Register 0x0000_0000 MTP KEY Value 1 Register MTP_KEY1 MTP_BA+0x014 0x0000_0000 MTP KEY Value 2 Register MTP_KEY2 MTP_BA+0x018 0x0000_0000 MTP KEY Value 3 Register MTP_KEY3 MTP_BA+0x01c...
Page 256 NUC970 Technical Reference Manual MTP Program Cycle Register (MTP_PCYCLE) Register Offset Description Reset Value MTP_PCYCLE MTP_BA+0x030 MTP Program Cycle Control Register 0x0000_60AE Reserved Reserved PCYCLE PCYCLE Bits Description [31:16] Reserved Reserved. MTP CYCLE Register Set the cycle counts to meet 330us for write MTP. Example: PCLK = 75MHz (13.3333ns).
Page 257 NUC970 Technical Reference Manual MTP Mode Control Register (MTP_CTL) Register Offset Description Reset Value MTP_CTL MTP_BA+0x034 MTP Control Register 0x0000_0000 Reserved Reserved Reserved Reserved MODE Bits Description [31:2] Reserved Reserved. MTP Mode 2’b00 = MTP Idle Mode. 2’b01 = Reserved. [1:0] MODE 2’b10 = MTP Program Key Mode.
Page 258 NUC970 Technical Reference Manual MTP Program Start Register (MTP_PSTART) Register Offset Description Reset Value MTP_PSTART MTP_BA+0x038 MTP Program Start Register 0x0000_0000 Reserved Reserved Reserved Reserved PSTART Bits Description [31:1] Reserved Reserved. MTP Program Start Register PSTART Write 1 to start MTP Program/LOCK. Note: this bit will auto clear after MTP program/lock finish.
Page 259 NUC970 Technical Reference Manual MTP Status Register (MTP_STATUS) Register Offset Description Reset Value MTP_STATUS MTP_BA+0x040 MTP Status Register 0x0000_0000 Reserved BUSY Reserved PRGCNT Reserved Reserved PRGFAIL LOCKED NONPRG KEYVALID MTPEN Bits Description [31:25] Reserved Reserved. MTP Busy Status [24] BUSY 0 = MTP engine is idle.
Page 260 NUC970 Technical Reference Manual MTP Register Write-Protection Control Register (MTP_REGLCTL) Register Offset Description Reset Value MTP_REGLCTL MTP_BA+0x050 MTP Register Write-Protection Control Register 0x0000_0000 Reserved Reserved Reserved REGLCTL[0] REGLCTL[7:1] REGPRTDIS Bits Description [31:8] Reserved Reserved. Register Write-protection Code (Write Only) Some registers have write-protection function. Writing these registers have to [7:0] REGLCTL disable the protected function by writing the sequence value “59h”, “16h”, “88h”...
Page 261: External Bus Interface (Ebi)
NUC970 Technical Reference Manual External Bus Interface (EBI) 5.7.1 Overview This chip supports External Bus Interface (EBI), which controls the access to the external memory (SRAM) and External I/O devices. The EBI has up to 5 chip select signals to select different devices with 10-bit address bus.
Page 262: Basic Configuration
NUC970 Technical Reference Manual 5.7.4 Basic Configuration Before using External Bus Interface, it’s necessary to configure related pins as the EBI function and enable EBI’s clock. For EBI related pin configuration, please refer to the register SYS_MFP_GPDH, SYS_MFP_GPHL, SYS_MFP_GPHH, SYS_MFP_GPIL and SYS_MFP_GPIH to know how to configure related pins as the EBI function.
Page 263: Register Map
NUC970 Technical Reference Manual 5.7.6 Register Map Register Offset Description Reset Value EBI Base Address: EBI_BA = 0xB000_1000 EBI_CTL EBI_BA+0x000 EBI Control Register 0x0001_0001 EBI_BNKCTL0 EBI_BA+0x018 External Bus Bank 0 Control Register 0x0000_0000 EBI_BNKCTL1 EBI_BA+0x01C External Bus Bank 1 Control Register 0x0000_0000 EBI_BNKCTL2 EBI_BA+0x020 External Bus Bank 2 Control Register...
Page 264: Register Description
NUC970 Technical Reference Manual 5.7.7 Register Description Publication Release Date: Dec. 15, 2015 - 264 - Revision V1.30...
Page 265 NUC970 Technical Reference Manual EBI Control Register (EBI_CTL) Register Offset Description Reset Value EBI_CTL EBI_BA+0x000 EBI Control Register 0x0001_0001 Reserved EXBE4 EXBE3 EXBE2 EXBE1 EXBE0 M68E4 M68E3 M68E2 M68E1 M68E0 Reserved Reserved Reserved WAITVT LITTLE Bits Description [31:29] Reserved Reserved. External Bus Bank 4 Byte Enable This bit and M68E4 (EBI_CTL[23]) defines how the pins EBI_nBE1, EBI_nBE0 and EBI_nWE are used when external bus bank 4 accessed.
Page 266 NUC970 Technical Reference Manual External Bus Bank 3 Byte Enable This bit and M68E3(EBI_CTL[22]) defines how the pins EBI_nBE1, EBI_nBE0 and EBI_nWE are used when external bus bank 3 accessed. Please refer to the table shown below for detail information. EXBE3 M68E3 Description...
Page 267 NUC970 Technical Reference Manual External Bus Bank 0 Byte Enable This bit and M68E0(EBI_CTL[19]) defines how the pins EBI_nBE1, EBI_nBE0 and EBI_nWE are used when external bus bank 0 accessed. Please refer to the table shown below for detail information. EXBE0 M68E0 Description...
Page 268 NUC970 Technical Reference Manual External Bus Bank Control Register (EBI_BNKCTL0 – EBI_BNKCTL4) Register Offset Description Reset Value EBI_BNKCTL EBI_BA+0x018 External Bus Bank 0 Control Register 0x0000_0000 EBI_BNKCTL EBI_BA+0x01C External Bus Bank 1 Control Register 0x0000_0000 EBI_BNKCTL EBI_BA+0x020 External Bus Bank 2 Control Register 0x0000_0000 EBI_BNKCTL EBI_BA+0x024...
Page 269 NUC970 Technical Reference Manual Access Cycles (NOE or NWE Active Time) for External I/O Bank 0~4 0000 = Reserved. 0001 = Access Cycles (nOE or nWE active time) is 1 MCLK. 0010 = Access Cycles (nOE or nWE active time) is 2 MCLK. 0011 = Access Cycles (nOE or nWE active time) is 3 MCLK.
Page 270 NUC970 Technical Reference Manual Programmable Data Bus Width for External I/O Bank 0~4 00 = Disable bus. [1:0] DBWD 01 = 8-bit. 10 = 16-bit. 11 = Reserved. Publication Release Date: Dec. 15, 2015 - 270 - Revision V1.30...
Page 271: Figure 5.7-2 External I/O Write Operation Timing
NUC970 Technical Reference Manual Figure 5.7-2 External I/O Write operation timing Figure 5.7-3 External I/O Read operation timing Publication Release Date: Dec. 15, 2015 - 271 - Revision V1.30...
Page 272: General Purpose I/O (Gpio)
5.8.1 Overview The NUC970 series have up to 148 General-Purpose I/O (GPIO) pins and can be shared with other function pins depending on the chip configuration. These 148 pins are arranged in 10 ports named as PA, PB, PC, PD, PE, PF, PG, PH, PI and PJ. PA, PB, PD, PE, PF, PG, PH and PI have 16 pins on port, PC has 15 pins on port and PJ has 5 pins on port.
Page 273: Block Diagram
NUC970 Technical Reference Manual 5.8.3 Block Diagram Control Registers PA[15:0] PA[15:0] PF[15:0] PB[15:0] Control Register Control Register PC[14:0] PB[15:0] PG[15:0] Control Register Control Register PD[15:0] PC[14:0] PH[15:0] PE[15:0] Control Register Control Register PF[15:0] PD[15:0] PI[15:0] Control Register Control Register PG[15:0] PE[15:0] PJ[4:0] PH[15:0]...
Page 274: Register Map
NUC970 Technical Reference Manual 5.8.5.2 Output mode Set OUTEN (GPIOx_DIR[n]) to 1 as the Px.n pin is in output mode and the I/O pin reflects the value written in DATAOUT (GPIOx_DATAOUT[n]). 5.8.5.3 GPIO Interrupt Each GPIO pin can be set as chip interrupt source by setting correlative IMD (GPIOx_IMD[n]), IREN (GPIOx_IREN[n]) and IFEN (GPIOx_IFEN[n]).
Page 275 NUC970 Technical Reference Manual GPIOB_PUEN GPIO_BA+0x060 GPIO Port B Pull-Up Enable Register 0x0000_0000 GPIOB_PDEN GPIO_BA+0x064 GPIO Port B Pull-Down Enable Register 0x0000_0000 GPIOB_ICEN GPIO_BA+0x068 GPIO Port B CMOS Input Enable Register 0x0000_FFFF GPIOB_ISEN GPIO_BA+0x06C R/W GPIO Port B Schmitt-Trigger Input Enable Register 0x0000_0000 GPIOC_DIR GPIO_BA+0x080...
Page 276 NUC970 Technical Reference Manual GPIOE_IREN GPIO_BA+0x110 GPIO Port E Interrupt Rising-Edge or Level-High 0x0000_0000 Enable Register GPIOE_IFEN GPIO_BA+0x114 GPIO Port E Interrupt Falling-Edge or Level-Low 0x0000_0000 Enable Register GPIOE_ISR GPIO_BA+0x118 GPIO Port E Interrupt Status Register 0x0000_0000 GPIOE_DBEN GPIO_BA+0x11C R/W GPIO Port E De-bounce Enable Register 0x0000_0000 GPIOE_PUEN...
Page 277 NUC970 Technical Reference Manual GPIOG_ISEN GPIO_BA+0x1AC R/W GPIO Port G Schmitt-Trigger Input Enable Register 0x0000_0000 GPIOH_DIR GPIO_BA+0x1C0 R/W GPIO Port H Direction Control Register 0x0000_0000 GPIOH_DATAOUT GPIO_BA+0x1C4 R/W GPIO Port H Data Output Register 0x0000_0000 GPIOH_DATAIN GPIO_BA+0x1C8 R GPIO Port H Data Input Register 0x0000_xxxx GPIOH_IMD GPIO_BA+0x1CC R/W...
Page 278 NUC970 Technical Reference Manual GPIOJ_ISR GPIO_BA+0x258 GPIO Port J Interrupt Status Register 0x0000_0000 GPIOJ_DBEN GPIO_BA+0x25C R/W GPIO Port J De-bounce Enable Register 0x0000_0000 GPIOJ_PUEN GPIO_BA+0x260 GPIO Port J Pull-Up Enable Register 0x0000_0000 GPIOJ_PDEN GPIO_BA+0x264 GPIO Port J Pull-Down Enable Register 0x0000_0000 GPIOJ_ICEN GPIO_BA+0x268...
Page 279: Register Description
NUC970 Technical Reference Manual 5.8.7 Register Description Publication Release Date: Dec. 15, 2015 - 279 - Revision V1.30...
Page 280 NUC970 Technical Reference Manual GPIO Port A-J Direction Control Register (GPIOx_DIR) Register Offset Description Reset Value GPIOA_DIR GPIO_BA+0x000 GPIO Port A Direction Control Register 0x0000_0000 GPIOB_DIR GPIO_BA+0x040 GPIO Port B Direction Control Register 0x0000_0000 GPIOC_DIR GPIO_BA+0x080 GPIO Port C Direction Control Register 0x0000_0000 GPIOD_DIR GPIO_BA+0x0C0...
Page 281 NUC970 Technical Reference Manual GPIO Port A-J Data Output Register (GPIOx_DATAOUT) Register Offset Description Reset Value GPIOA_DATAOUT GPIO_BA+0x004 GPIO Port A Data Output Register 0x0000_0000 GPIOB_DATAOUT GPIO_BA+0x044 GPIO Port B Data Output Register 0x0000_0000 GPIOC_DATAOUT GPIO_BA+0x084 GPIO Port C Data Output Register 0x0000_0000 GPIOD_DATAOUT GPIO_BA+0x0C4...
Page 282 NUC970 Technical Reference Manual GPIO Port A-J Data Input Register (GPIOx_DATAIN) Register Offset Description Reset Value GPIOA_DATAIN GPIO_BA+0x008 GPIO Port A Data Input Register 0x0000_xxxx GPIOB_DATAIN GPIO_BA+0x048 GPIO Port B Data Input Register 0x0000_xxxx GPIOC_DATAIN GPIO_BA+0x088 GPIO Port C Data Input Register 0x0000_xxxx GPIOD_DATAIN GPIO_BA+0x0C8...
Page 283 NUC970 Technical Reference Manual GPIO Port A-J Interrupt Mode Register (GPIOx_IMD) Register Offset Description Reset Value GPIOA_IMD GPIO_BA+0x00C GPIO Port A Interrupt Mode Register 0x0000_0000 GPIOB_IMD GPIO_BA+0x04C GPIO Port B Interrupt Mode Register 0x0000_0000 GPIOC_IMD GPIO_BA+0x08C GPIO Port C Interrupt Mode Register 0x0000_0000 GPIOD_IMD GPIO_BA+0x0CC...
Page 284 NUC970 Technical Reference Manual GPIO Port A-J Interrupt Rising-Edge Or Level-High Enable Register (GPIOx_IREN) Register Offset Description Reset Value GPIOA_IREN GPIO_BA+0x010 GPIO Port A Interrupt Rising-Edge or Level-High 0x0000_0000 Enable Register GPIOB_IREN GPIO_BA+0x050 GPIO Port B Interrupt Rising-Edge or Level-High 0x0000_0000 Enable Register GPIOC_IREN...
Page 285 NUC970 Technical Reference Manual GPIO Interrupt Rising-edge or Level-high Enable This field controls the enable of rising-edge or level-high detection of a General-Purpose I/O. When this bit is high and corresponding bit of GPIOx_IMD is low, rising-edge detection enabled. When this bit is high and corresponding bit of GPIOx_IMD is high, level-high detection enabled.
Page 286 NUC970 Technical Reference Manual GPIO Port A-J Interrupt Falling-Edge Or Level-Low Enable Register (GPIOx_IFEN) Register Offset Description Reset Value GPIOA_IFEN GPIO_BA+0x014 GPIO Port A Interrupt Falling-Edge or Level-Low 0x0000_0000 Enable Register GPIOB_IFEN GPIO_BA+0x054 GPIO Port B Interrupt Falling-Edge or Level-Low 0x0000_0000 Enable Register GPIOC_IFEN...
Page 287 NUC970 Technical Reference Manual GPIO Interrupt Falling-edge or Level-low Enable This field controls the enable of falling-edge or level-low detection of a General-Purpose I/O. When this bit is high and corresponding bit of GPIOx_IMD is low, falling-edge detection enabled. When this bit is high and corresponding bit of GPIOx_IMD is high, level-low detection enabled.
Page 288 NUC970 Technical Reference Manual GPIO Port A-J Interrupt Status Register (GPIOx_ISR) Register Offset Description Reset Value GPIOA_ISR GPIO_BA+0x018 GPIO Port A Interrupt Status Register 0x0000_0000 GPIOB_ISR GPIO_BA+0x058 GPIO Port B Interrupt Status Register 0x0000_0000 GPIOC_ISR GPIO_BA+0x098 GPIO Port C Interrupt Status Register 0x0000_0000 GPIOD_ISR GPIO_BA+0x0D8...
Page 289 NUC970 Technical Reference Manual GPIO Port A-J De-bounce Enable Register (GPIOx_DBEN) Register Offset Description Reset Value GPIOA_DBEN GPIO_BA+0x01C GPIO Port A De-bounce Enable Register 0x0000_0000 GPIOB_DBEN GPIO_BA+0x05C GPIO Port B De-bounce Enable Register 0x0000_0000 GPIOC_DBEN GPIO_BA+0x09C GPIO Port C De-bounce Enable Register 0x0000_0000 GPIOD_DBEN GPIO_BA+0x0DC...
Page 290 NUC970 Technical Reference Manual GPIO Port A-J Pull-Up Enable Register (GPIOx_PUEN) Register Offset Description Reset Value GPIOA_PUEN GPIO_BA+0x020 GPIO Port A Pull-Up Enable Register 0x0000_0000 GPIOB_PUEN GPIO_BA+0x060 GPIO Port B Pull-Up Enable Register 0x0000_0000 GPIOC_PUEN GPIO_BA+0x0A0 GPIO Port C Pull-Up Enable Register 0x0000_0000 GPIOD_PUEN GPIO_BA+0x0E0...
Page 291 NUC970 Technical Reference Manual GPIO Port A-J Pull-Down Enable Register (GPIOx_PDEN) Register Offset Description Reset Value GPIOA_PDEN GPIO_BA+0x024 GPIO Port A Pull-Down Enable Register 0x0000_0000 GPIOB_PDEN GPIO_BA+0x064 GPIO Port B Pull-Down Enable Register 0x0000_0000 GPIOC_PDEN GPIO_BA+0x0A4 GPIO Port C Pull-Down Enable Register 0x0000_0000 GPIOD_PDEN GPIO_BA+0x0E4...
Page 292 NUC970 Technical Reference Manual GPIO Port A-J CMOS Input Enable Register (GPIOx_ICEN) Register Offset Description Reset Value GPIOA_ICEN GPIO_BA+0x028 GPIO Port A CMOS Input Enable Register 0x0000_FFFF GPIOB_ICEN GPIO_BA+0x068 GPIO Port B CMOS Input Enable Register 0x0000_FFFF GPIOC_ICEN GPIO_BA+0x0A8 GPIO Port C CMOS Input Enable Register 0x0000_EFFF GPIOD_ICEN GPIO_BA+0x0E8...
Page 293 NUC970 Technical Reference Manual GPIO Port A-J Schmitt-Trigger Input Enable Register (GPIOx_ISEN) Register Offset Description Reset Value GPIOA_ISEN GPIO_BA+0x02C GPIO Port A Schmitt-Trigger Input Enable 0x0000_0000 Register GPIOB_ISEN GPIO_BA+0x06C GPIO Port B Schmitt-Trigger Input Enable 0x0000_0000 Register GPIOC_ISEN GPIO_BA+0x0AC GPIO Port C Schmitt-Trigger Input Enable 0x0000_0000 Register GPIOD_ISEN...
Page 294 NUC970 Technical Reference Manual GPIO Schmitt Input Enable This fields controls the Schmitt trigger input buffer enable of the pin that can be configured as a General-Purpose I/O. This control bit always takes effect no matter the pin configured as a General-Purpose I/O or not.
Page 295 NUC970 Technical Reference Manual GPIO Debounce Control Register (GPIO_DBNCECON) Register Offset Description Reset Value GPIO_DBNCECON GPIO_BA+0x3F0 GPIO Debounce Control Register 0x0000_0020 Reserved Reserved Reserved Reserved ICLK_ON Reserved DBCLKSEL Bits Description Reserved [31:6] Reserved. Interrupt Clock on Mode This bit controls the interrupt detection clock enable of the pin that can be configured as a General-Purpose I/O.
Page 296 NUC970 Technical Reference Manual De-bounce Sampling Cycle Selection 0000 = Sample interrupt input once per 1 clocks. 0001 = Sample interrupt input once per 2 clocks. 0010 = Sample interrupt input once per 4 clocks. 0011 = Sample interrupt input once per 8 clocks. 0100 = Sample interrupt input once per 16 clocks.
Page 297 NUC970 Technical Reference Manual GPIO Port Interrupt Status Register (GPIO_ISR) Register Offset Description Reset Value GPIO_ISR GPIO_BA+0x3FC GPIO Port Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved GPIOJINT GPIOIINT GPIOHINT GPIOGINT GPIOFINT GPIOEINT GPIODINT GPIOCINT GPIOBINT GPIOAINT Bits Description Reserved [31:10] Reserved.
Page 298 NUC970 Technical Reference Manual GPIO Port F Interrupt Status This bit indicates if the GPIO interrupt triggered by pin of GPIO port F. GPIOFINT 0: GPIO port F did not trigger GPIO interrupt 1: GPIO port F trigger GPIO interrupt GPIO Port E Interrupt Status This bit indicates if the GPIO interrupt triggered by pin of GPIO port E.
Page 299: General Dma Controller (Gdma)
NUC970 Technical Reference Manual General DMA Controller (GDMA) 5.9.1 Overview The chip has a two-channel general DMA controller with or without descriptor fetch operation, called the GDMA. The two-channel GDMA performs the memory-to-memory data transfers without the CPU intervention: The on-chip GDMA can be started by the software. Software can also be used to restart the GDMA operation after it has been stopped.
Page 300: Basic Configuration
NUC970 Technical Reference Manual 5.9.4 Basic Configuration Before using GDMA, it’s necessary to enable clock of GDMA. Set GDMA (CLK_HCLKEN[12]) high to enable GDMA’s clock. 5.9.5 Functional Description 5.9.5.1 Non-Descriptor Mode The GDMA directly transfers data between source and destination. The GDMA starts to transfer data after it receives service requests from software.
Page 301 NUC970 Technical Reference Manual 5.9.5.5 Descriptor Fetch Function The Illustration of Descriptor list fetches: Fetch GDMA Memory Descriptor GDMA_DADRx Next Descriptor Address GDMA_DADRx[31:4] + A Descriptor Source Address 0 list finished Ordering GDMA_DADRx[31:4] + GDMA_DADRx[31:4] + Destination Address 0 GDMA_DADRx[31:4] + 0x10 GDMA_DADRx[31:4] + Command Information 0...
Page 302 NUC970 Technical Reference Manual Descriptor can only work when the [RUN][3] is set and [NON_DSPTRMODE][2] bit is cleared properly.) After sets current GDMA_DADRx register, the GDMA will fetch four-word information from memory immediately which contains the next Descriptor address, Source Address, Destination Address and Command information.
Page 303 NUC970 Technical Reference Manual 5.9.5.7 Ordering function in Descriptor fetch mode This function determines the source of next descriptor address. If [ORDEN] is set, the GDMA controller fetches the next descriptor from current GDMA_DADRx[Descriptor Address] + 16 bytes. If this bit is cleared, GDMA fetches the next descriptor from the current GDMA_DADRx[Descriptor Address] .
Page 304: Register Map
NUC970 Technical Reference Manual 5.9.6 Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Offset Description Reset Value GDMA Base Address: GDMA_BA = 0xB000_4000 GDMA_CTL0 GDMA_BA+0x000 Channel 0 Control Register 0x0000_0000 GDMA_SRCBA0 GDMA_BA+0x004...
Page 305: Register Description
NUC970 Technical Reference Manual 5.9.7 Register Description Publication Release Date: Dec. 15, 2015 - 305 - Revision V1.30...
Page 306 NUC970 Technical Reference Manual Channel 0/1 Control Register (GDMA_CTL0, GDMA_CTL1) Register Offset Description Reset Value GDMA_CTL0 GDMA_BA+0x000 Channel 0 Control Register 0x0000_0000 GDMA_CTL1 GDMA_BA+0x020 Channel 1 Control Register 0x0000_0000 The control registers has two formats for descriptor fetch and non-descriptor fetch function respectively.
Page 307 NUC970 Technical Reference Manual Control Register of Non-Descriptor fetches Mode: Bits Description [31:23] Reserved Reserved. Source Address Boundary Alignment Error Flag If TWS [13:12]=10, GDMA_SRCB [1:0] should be 00. If TWS [13:12]=01, GDMA_SRCB [0] should be 0. Except the SADIR function enabled. [22] SABNDERR The address boundary alignment should be depended on TWS [13:12].
Page 308 NUC970 Technical Reference Manual Single/Block Mode Select 0 = Selects single mode. It requires an external GDMA request for every incurring GDMA operation. SBMS [11] 1 = Selects block mode. It requires a single external GDMA request during the atomic GDMA operation.
Page 309 NUC970 Technical Reference Manual Bits Description [31:23] Reserved Reserved. Source Address Boundary Alignment Error Flag If TWS [13:12]=10, GDMA_SRCB [1:0] should be 00. If TWS [13:12]=01, GDMA_SRCB [0] should be 0. Except the SADIR function enabled. [22] SABNDERR The address boundary alignment should be depended on TWS [13:12]. 0 = the GDMA_SRCB is on the boundary alignment.
Page 310 NUC970 Technical Reference Manual Destination Address Fixed 0 = Destination address is changed during the GDMA operation. DAFIX 1 = Do not change the destination address during the GDMA operation. This feature can be used when data were transferred from multiple sources to a single destination. Source Address Direction SADIR 0 = Source address is incremented successively.
Page 311 NUC970 Technical Reference Manual Channel 0/1 Source Base Address Register (GDMA_SRCBA0, GDMA_SRCBA1) Register Offset Description Reset Value GDMA_SRCBA0 GDMA_BA+0x004 Channel 0 Source Base Address Register 0x0000_0000 GDMA_SRCBA1 GDMA_BA+0x024 Channel 1 Source Base Address Register 0x0000_0000 BADDR BADDR BADDR BADDR Bits Description Source Base Address BADDR...
Page 312 NUC970 Technical Reference Manual Channel 0/1 Destination Base Address Register (GDMA_DSTBA0, GDMA_DSTBA1) Register Offset Description Reset Value GDMA_DSTBA0 GDMA_BA+0x008 Channel 0 Destination Base Address Register 0x0000_0000 GDMA_DSTBA1 GDMA_BA+0x028 Channel 1 Destination Base Address Register 0x0000_0000 BADDR BADDR BADDR BADDR Bits Description Destination Base Address The GDMA channel starts writing its data to the destination address as defined in this...
Page 313 NUC970 Technical Reference Manual Channel 0/1 Transfer Count Register (GDMA_TCNT0, GDMA_TCNT1) Register Offset Description Reset Value GDMA_TCNT0 GDMA_BA+0x00C Channel 0 Transfer Count Register 0x0000_0000 GDMA_TCNT1 GDMA_BA+0x02C Channel 1 Transfer Count Register 0x0000_0000 Reserved COUNT COUNT COUNT Bits Description [31:24] Reserved Reserved.
Page 314 NUC970 Technical Reference Manual Channel 0/1 Current Source Address Register (GDMA_CSRCA0, GDMA_CSRCA1) Register Offset Description Reset Value GDMA_CSRCA0 GDMA_BA+0x010 Channel 0 Current Source Address Register 0x0000_0000 GDMA_CSRCA1 GDMA_BA+0x030 Channel 1 Current Source Address Register 0x0000_0000 CADDR CADDR CADDR CADDR Bits Description Current Source Address The CURRENT_SRC_ADDR indicates the source address where the GDMA...
Page 315 NUC970 Technical Reference Manual Channel 0/1 Current Destination Address Register (GDMA_CDSTA0, GDMA_CDSTA1) Register Offset Description Reset Value GDMA_CDSTA0 GDMA_BA+0x014 Channel 0 Current Destination Address Register 0x0000_0000 GDMA_CDSTA1 GDMA_BA+0x034 Channel 1 Current Destination Address Register 0x0000_0000 CADDR CADDR CADDR CADDR Bits Description Current Destination Address The CURRENT_DST_ADDR indicates the destination address where the GDMA...
Page 316 NUC970 Technical Reference Manual Channel 0/1 Current Transfer Count Register (GDMA_CTCNT0, GDMA_CTCNT1) Register Offset Description Reset Value GDMA_CTCNT0 GDMA_BA+0x018 Channel 0 Current Transfer Count Register 0x0000_0000 GDMA_CTCNT1 GDMA_BA+0x038 Channel 1 Current Transfer Count Register 0x0000_0000 Reserved CCNT CCNT CCNT Bits Description Current Transfer Count The Current transfer count register indicates the number of transfer being...
Page 317 NUC970 Technical Reference Manual Channel 0/1 Descriptor Register (GDMA_DADR0/1) Register Offset Description Reset Value GDMA_DADR0 GDMA_BA+0x01C Channel 0 Descriptor Address Register 0x0000_0004 GDMA_DADR1 GDMA_BA+0x03C Channel 1 Descriptor Address Register 0x0000_0004 ADDR ADDR ADDR ADDR NON_DSPTR ORDEN RESET Bits Description Descriptor Address [31:4] ADDR Contains address of next descriptor.
Page 318 NUC970 Technical Reference Manual If this bit is cleared, GDMA fetches the next descriptor address from the current GDMA_DADRx[Descriptor Address] register. GDMA_DADRx[ORDEN] is relevant only for descriptor-fetch function (GDMA_DADRx[NON_DSPTRMODE] = 0). 0 = Disable descriptor ordering. Fetch the next descriptor from register GDMA_DDADRx[Descriptor Address].
Page 319 NUC970 Technical Reference Manual GDMA Internal Buffer Word Register (GDMA_BUFFER) Softeware can set the [17-16] bit of GDMA_INTCS to select channels and watch the value which has read from memory. Register Offset Description Reset Value GDMA_BUFFER0 GDMA_BA+0x080 GDMA Internal Buffer Word 0 Register 0x0000_0000 GDMA_BUFFER1 GDMA_BA+0x084...
Page 320 NUC970 Technical Reference Manual GDMA Interrupt Control and Status Register (GDMA_INTS) Register Offset Description Reset Value GDMA_INTS GDMA_BA+0x0A0 GDMA Interrupt Control and Status Register 0x0000_0000 Reserved Reserved BUF_RD_SEL Reserved TERR1F TC1F TERR0F TC0F Reserved TERR1EN TC1EN TERR0EN TC0EN Bits Description [31:18] Reserved Reserved.
Page 321 NUC970 Technical Reference Manual Channel 0 Terminal Count 0 = Channel does not expire. TC0F 1 = Channel expires; this bit is set only by GDMA hardware, and clear by software to write logic 1. TC0 is the GDMA interrupt flag. TC0 or GDMATERR0 will generate interrupt Reserved [7:4] Reserved.
Page 322: Timer Controller (Tmr)
NUC970 Technical Reference Manual 5.10 Timer Controller (TMR) 5.10.1 Overview The general timer controller includes five channels, TIMER0, TIMER1, TIMER2, TIMER3, and TIMER4, which allow user to easily implement a counting scheme or timing control for applications. The timer possesses features such as adjustable resolution, and programmable counting period. The timer can generate an interrupt signal upon timeout, or provide the current value of count during operation.
Page 323: Block Diagram
NUC970 Technical Reference Manual 5.10.3 Block Diagram Each timer is equipped with an 8-bit pre-scale counter, a 24-bit up-counter, a 24-bit compare register and an interrupt request signal. WAKE_EN Timer (TMR0_CSR[23]) wakeup 24-bit TCMP (TMR0_CMPR[23:0]) Power-down TWKF CRST Reset counter (TMR0_ISR[8]) (TMR0_CSR[26]) Interrupt...
Page 324 NUC970 Technical Reference Manual counting initial value then timer counter enable bit CE (TMRx_CSR[30]) is cleared to 0 by timer controller automatically. That is to say, timer operates timer counting and compares with TCMP (TMRx_CMPR[23:0]) value function only one time after programming the timer compare register TCMP (TMRx_CMPR[23:0]) value and timer counter enable bit CE (TMRx_CSR[30]) is set to 1.
Page 325: Register Map
NUC970 Technical Reference Manual 5.10.6 Register Map R: read only, W: write only, R/W: both read and write. Register Offset Description Reset Value TMR Base Address: TMR0_BA = 0xB800_1000 TMR1_BA = 0xB800_1010 TMR2_BA = 0xB800_1020 TMR3_BA = 0xB800_1030 TMR4_BA = 0xB800_1040 TMR0_CSR TMR0_BA+0x000 Timer Control and Status Register 0...
Page 326: Register Description
NUC970 Technical Reference Manual 5.10.7 Register Description Timer Control and Status Register (TMR_CSR) Register Offset Description Reset Value TMR0_CSR TMR0_BA+0x000 Timer Control and Status Register 0 0x0000_0005 TMR1_CSR TMR1_BA+0x000 Timer Control and Status Register 1 0x0000_0005 TMR2_CSR TMR2_BA+0x000 Timer Control and Status Register 2 0x0000_0005 TMR3_CSR TMR3_BA+0x000...
Page 327 NUC970 Technical Reference Manual Note: This bit will be cleared by hardware automatically. Timer Is in Active This bit indicates the counter status of timer. [25] CACT 0 = Timer is not active. 1 = Timer is in active. [24:8] Reserved Reserved.
Page 328 NUC970 Technical Reference Manual Timer Compare Registers (TMR_CMPR) Register Offset Description Reset Value TMR0_CMPR TMR0_BA+0x004 Timer Compare Register 0 0x0000_0000 TMR1_CMPR TMR1_BA+0x004 Timer Compare Register 1 0x0000_0000 TMR2_CMPR TMR2_BA+0x004 Timer Compare Register 2 0x0000_0000 TMR3_CMPR TMR3_BA+0x004 Timer Compare Register 3 0x0000_0000 TMR4_CMPR TMR4_BA+0x004...
Page 329 NUC970 Technical Reference Manual Timer Data Registers (TMR_DR) Register Offset Description Reset Value TMR0_DR TMR0_BA+0x008 Timer Data Register 0 0x0000_0000 TMR1_DR TMR1_BA+0x008 Timer Data Register 1 0x0000_0000 TMR2_DR TMR2_BA+0x008 Timer Data Register 2 0x0000_0000 TMR3_DR TMR3_BA+0x008 Timer Data Register 3 0x0000_0000 TMR4_DR TMR4_BA+0x008...
Page 330 NUC970 Technical Reference Manual Timer Interrupt Status Registers (TMR_ISR) Register Offset Description Reset Value TMR_ISR TMR0_BA+0x060 Timer Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved TIF4 TIF3 TIF2 TIF1 TIF0 Bits Description [31:5] Reserved Reserved. Timer Interrupt Flag 4 0 = It indicates that the timer 4 does not count up to TCMP (TMR4_CMPR[23:0]) value yet.
Page 331 NUC970 Technical Reference Manual Timer Interrupt Flag 0 0 = It indicates that the timer 0 does not count up to TCMP (TMR0_CMPR[23:0]) value yet. Software can reset this bit after the timer interrupt 0 had occurred. TIF0 1 = It indicates that the counter of timer 0 is incremented to corresponding TCMP (TMR0_CMPR[23:0]) setting value.
Page 332: Enhance Timer Controller (Etmr)
NUC970 Technical Reference Manual 5.11 Enhance Timer Controller (ETMR) 5.11.1 Overview This chip is equipped with four enhance timer modules including ETIMER0, ETIMER1, ETIMER2 and ETIMER3, which allow user to easily implement a counting scheme or timing control for applications. The timer can perform functions like frequency measurement, interval measurement, clock generation, delay timing, and so on.
Page 333: Basic Configuration
NUC970 Technical Reference Manual ETIMERx_S(CLK_DIVCTL8) ETIMERx(CLK_PCLKEN0) 12MHz (HXT) PCLK ECLKetmrx PCLK/4096 32.768 kHz (LXT) Where x = 0, 1, 2, 3 Figure 5.11-2 Enhance Timer Clock Controller Diagram 5.11.4 Basic Configuration When using Enhance Timer, it’s necessary to configure related pins as the ETMR function and enable ETMR’s clock.
Page 334 NUC970 Technical Reference Manual 5.11.5.2 Periodic Mode If the timer is operated in Periodic mode (MODE_SEL[1:0] is 01) and ETMR_EN (ETMRn_CTL[0] timer counter enable bit) is set to 1, the timer counter starts up counting. Once the timer counter value (ETMRn_DR value) reaches timer compare register (ETMRn_CMPR) value, the ETMR_IS (ETMRn_ISR[0] timer interrupt status) will set to 1.
Page 335: Figure 5.11-3 Timer Clock Controller Diagram
NUC970 Technical Reference Manual For example, the timer compare register (ETMRn_CMPR) value is set as 80, first. (The timer compare register (ETMRn_CMPR) should be less than 2 and be greater than 1). Once the timer counter value (ETMRn_DR value) reaches to 80, ETMR_IS (ETMRn_ISR[0] timer interrupt status) will set to 1 and ETMR_EN (ETMRn_CTL[0] timer counter enable bit) is still kept at 1 (counting enable continuously).
Page 336: Register Map
NUC970 Technical Reference Manual edge could be detected. The reset value of de-bounce circuit is “0” and the de-bounce circuit would only active when both TCAP_DEB_EN and TCAP_EN are enabled. So, if the external pin level is “1” and TCAP_EDGE is set to detect rising-edge of external pin, then after de-bounce circuit active (TCAP_DEB_EN is “1”...
Page 337 NUC970 Technical Reference Manual Enhance Timer n Control Register (ETMRn_CTL) Register Offset Description Reset Value ETMRn_CTL ETMRn_BA+0x000 R/W Enhance Timer n Control Register 0x0000_0000 n=0,1,2,3 Reserved Reserved TCAP_DEB_EN Reserved CAP_CNT_MOD TCAP_EDGE TCAP_MODE TCAP_EN Reserved ETMR_ACT Reserved MODE_SEL DBGACK_EN WAKE_EN SW_RST ETMR_EN Bits Description...
Page 338 NUC970 Technical Reference Manual Bits Description Tcapture Pin Edge Detect Selection This field defines that active transition of Tcapture pin is for timer counter reset function or for timer capture function. For timer counter reset function and free-counting mode of timer capture function, the configurations are: TCAP_EDGE Tcapture Pin Edge Detect...
Page 339 NUC970 Technical Reference Manual Bits Description Timer Active Status Bit (Read Only) This bit indicates the timer counter status of timer. ETMR_ACT 0 = Timer is not active. 1 = Timer is in active. Reserved Reserved. Timer Operating Mode Select MODE_SEL Timer Operating Mode The timer is operating in the one-shot mode.
Page 340 NUC970 Technical Reference Manual Bits Description Software Reset Set this bit will reset the timer counter, pre-scale counter and also force ETMR_CTL [ETMR_EN] to 0. SW_RST 0 = No effect. 1 = Reset Timer’s pre-scale counter, internal 24-bit up-counter and ETMR_CTL [ETMR_EN] bit.
Page 341 NUC970 Technical Reference Manual Enhance Timer n Pre-Scale Counter Register (ETMRn_PRECNT) Register Offset Description Reset Value ETMRn_PRE ETMRn_BA+0x004 R/W Enhance Timer n Pre-Scale Counter Register 0x0000_0000 n=0,1,2,3 Reserved Reserved Reserved PRESCALE_CNT Bits Description [31:8] Reserved Reserved. Pre-scale Counter [7:0] PRESCALE_CNT Clock input is divided by PRESCALE_CNT + 1 before it is fed to the counter.
Page 342 NUC970 Technical Reference Manual Enhance Timer n Compare Register (ETMRn_CMPR) Register Offset Description Reset Value ETMRn_CMP ETMRn_BA+0x008 R/W Enhance Timer n Compare Register 0x0000_0000 n=0,1,2,3 Reserved ETMR_CMP ETMR_CMP ETMR_CMP Bits Description [31:24] Reserved Reserved. Timer Compared Value ETMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to ETMR_CMP value, a Timer Interrupt is requested if the timer interrupt is enabled with ETMR_IER [ETMR_IE] is enabled.
Page 343 NUC970 Technical Reference Manual Enhance Timer n Interrupt Enable Register (ETMRn_IER) Register Offset Description Reset Value ETMRn_IER ETMRn_BA+0x00 Enhance Timer n Interrupt Enable Register 0x0000_0000 n=0,1,2,3 Reserved Reserved Reserved Reserved TCAP_IE ETMR_IE Bits Description [31:2] Reserved Reserved. Timer Capture Function Interrupt Enable 0 = Timer External Pin Function Interrupt Disabled.
Page 344 NUC970 Technical Reference Manual Enhance Timer n Interrupt Status Register (ETMRn_ISR) Register Offset Description Reset Value ETMRn_ISR ETMRn_BA+0x010 R/W Enhance Timer n Interrupt Status Register 0x0000_0000 n=0,1,2,3 Reserved Reserved Reserved Reserved NCAP_DET_STS ETMR_WAKE_STS Reserved TCAP_IS ETMR_IS Bits Description [31:6] Reserved Reserved.
Page 345 NUC970 Technical Reference Manual Enhance Timer n Data Register (ETMRn_DR) Register Offset Description Reset Value ETMRn_DR ETMRn_BA+0x014 R Enhance Timer n Data Register 0x0000_0000 n=0,1,2,3 Reserved Bits Description [31:24] Reserved Reserved. Timer Data Register [23:0] User can read this register for internal 24-bit timer up-counter value. Publication Release Date: Dec.
Page 346 NUC970 Technical Reference Manual Enhance Timer n Capture Data Register (ETMRn_TCAP) Register Offset Description Reset Value ETMRn_TCAP ETMRn_BA+0x018 R Enhance Timer n Capture Data Register 0x0000_0000 n=0,1,2,3 Reserved Bits Description [31:24] Reserved Reserved. Timer Capture Data Register When TCAP_EN is set, TCAP_MODE is 0, and the transition of external pin matches the [23:0] TCAP_EDGE setting, the value of 24-bit up-counting timer will be saved into register ETMRn_TCAP.
Page 347: Pulse Width Modulation (Pwm)
NUC970 Technical Reference Manual 5.12 Pulse Width Modulation (PWM) 5.12.1 Overview This chip has one PWM controller, and it has 4 independent PWM outputs, CH0~CH3, or as 2 complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable dead-zone generators. Each PWM pair has one Prescaler, one clock divider, two clock selectors, two 16-bit PWM counters, two 16-bit comparators, and one Dead-Zone generator.
Page 348: Block Diagram
NUC970 Technical Reference Manual 5.12.3 Block Diagram The following figure describes the architecture of one PWM pair. PWM0_CLK Dead-Zone DZEN01 Generator 0 (PWM_PCR[4]) CLKSEL0 (PWM_CSR[2:0]) PWM0_CNR PWM0_CMR CH1_INV (PWM_PCR[10]) Control logic DZEN01 PCLK (PWM_PCR[4]) CLKSEL1 8-bit (PWM_CSR[6:4]) Prescaler PWM1_CNR CH0_INV PWM1_CMR 1/16 (PWM_PCR[2])
Page 349: Figure 5.12-2 Legend Of Internal Comparator Output Of Pwm-Timer
NUC970 Technical Reference Manual Note: 1. Unit = one PWM clock cycle. Start Update Initialize new CMR CMR+1 PWM Timer Comparator Output Ouput CMR+1 CNR+1 Figure 5.12-2 Legend of Internal Comparator Output of PWM-Timer 5.12.5.2 PWM Double Buffering, Periodic and One-shot Operation The PWM timers have double buffering function;...
Page 350: Figure 5.12-4 Pwm Controller Output Duty Ratio
NUC970 Technical Reference Manual cycle. The loaded value will take effect from next cycle. Write Write Write CMR=100 CMR=50 CMR=0 1 PWM cycle = 151 1 PWM cycle = 151 1 PWM cycle = 151 Modulate PWM controller ouput duty ratio (CNR=150) Figure 5.12-4 PWM Controller Output Duty Ratio 5.12.5.4 Dead-Zone Generator...
Page 351 NUC970 Technical Reference Manual Setup clock selector CLKSEL0 (PWM_CSR[2:0]) Setup prescaler PRESCALE01 (PWM_PPR[7:0]) Setup inverter on/off, dead zone generator on/off, periodic/one-shot mode and Stop PWM-timer (PWM_PCR) Setup interrupt enable register PIER0 (PWM_PIER[0]) Setup the corresponding GPI/O pins to PWM function Setup PWM comparator register CMR (PWM_CMR[15:0]) and PWM counter register CNR (PWM_CNR[15:0]) for setting PWM period and duty length Enable PWM down-counter start running (Set CH0EN = 1 (PWM_PCR[0]))
Page 352: Register Map
NUC970 Technical Reference Manual 5.12.6 Register Map R: read only, W: write only, R/W: both read and write. Register Offset Description Reset Value PWM Base Address: PWM_BA = 0xB800_7000 PWM_PPR PWM_BA+0x000 PWM Pre-scale Register 0x0000_0000 PWM_CSR PWM_BA+0x004 PWM Clock Select Register 0x0000_0000 PWM_PCR PWM_BA+0x008...
Page 353: Register Description
NUC970 Technical Reference Manual 5.12.7 Register Description Publication Release Date: Dec. 15, 2015 - 353 - Revision V1.30...
Page 354 NUC970 Technical Reference Manual PWM Pre-scale Register (PWM_PPR) Register Offset Description Reset Value PWM_PPR PWM_BA+0x000 PWM Pre-scale Register 0x0000_0000 DZL23 DZL01 PRESCALE23 PRESCALE01 Bits Description Dead Zone Length Register 1 [31:24] DZL23 These 8 bits determine the dead-zone length of channel 2, 3 pair. The unit time of dead zone length is received from clock selector 1.
Page 355 NUC970 Technical Reference Manual PWM Clock Select Register (PWM_CSR) Register Offset Description Reset Value PWM_CSR PWM_BA+0x004 PWM Clock Select Register 0x0000_0000 Reserved Reserved Reserved CLKSEL3 Reserved CLKSEL2 Reserved CLKSEL1 Reserved CLKSEL0 Bits Description Reserved [31:15] Reserved. Channel 3 Clock Source Selection Select PWM clock source for PWM timer channel 3 000 = Prescale output divided by 2.
Page 356 NUC970 Technical Reference Manual PWM Control Register (PWM_PCR) Register Offset Description Reset Value PWM_PCR PWM_BA+0x008 PWM Control Register 0x0000_0000 Reserved Reserved CH3MOD CH3INV Reserved CH3EN CH2MOD CH2INV Reserved CH2EN CH1MOD CH1INV Reserved CH1EN Reserved DZEN23 DZEN01 CH0MOD CH0INV Reserved CH0EN Bits Description [31:20]...
Page 357 NUC970 Technical Reference Manual Channel 1 Inverter Switch [10] CH1INV 0: Inverter OFF. The output polarity of PWM channel 1 will be kept as usual 1: Inverter ON. The output polarity of PWM channel 1 will be inverted Reserved Reserved. Channel 1 Enable/Disable CH1EN 0: Disable the output of PWM channel 1...
Page 358 NUC970 Technical Reference Manual PWM Counter Register (PWM_CNR) Register Offset Description Reset Value PWM0_CNR PWM_BA+0x00C PWM Counter Register 0 0x0000_0000 PWM1_CNR PWM_BA+0x018 PWM Counter Register 1 0x0000_0000 PWM2_CNR PWM_BA+0x024 PWM Counter Register 2 0x0000_0000 PWM3_CNR PWM_BA+0x030 PWM Counter Register 3 0x0000_0000 Reserved Reserved...
Page 359 NUC970 Technical Reference Manual PWM Comparator Register (PWM_CMR) Register Offset Description Reset Value PWM0_CMR PWM_BA+0x010 PWM Comparator Register 0 0x0000_0000 PWM1_CMR PWM_BA+0x01C PWM Comparator Register 1 0x0000_0000 PWM2_CMR PWM_BA+0x028 PWM Comparator Register 2 0x0000_0000 PWM3_CMR PWM_BA+0x034 PWM Comparator Register 3 0x0000_0000 Reserved Reserved...
Page 360 NUC970 Technical Reference Manual PWM Data Register (PWM_PDR) Register Offset Description Reset Value PWM0_PDR PWM_BA+0x014 PWM Data Register 0 0x0000_0000 PWM1_PDR PWM_BA+0x020 PWM Data Register 1 0x0000_0000 PWM2_PDR PWM_BA+0x02C PWM Data Register 2 0x0000_0000 PWM3_PDR PWM_BA+0x038 PWM Data Register 3 0x0000_0000 Reserved Reserved...
Page 361 NUC970 Technical Reference Manual PWM Timer Interrupt Enable Register (PWM_PIER) Register Offset Description Reset Value PWM_PIER PWM_BA+0x03C PWM Timer Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved PIER3 PIER2 PIER1 PIER0 Bits Description Reserved [31:4] Reserved. PWM Timer Channel 3 Interrupt Enable PIER3 0: Disable the PWM interrupt function of channel 3 1: Enable the PWM interrupt function of channel 3...
Page 362 NUC970 Technical Reference Manual PWM Timer Interrupt Indication Register (PWM_PIIR) Register Offset Description Reset Value PWM_PIIR PWM_BA+0x040 PWM Timer Interrupt Indication Register 0x0000_0000 Reserved Reserved Reserved Reserved PIIR3 PIIR2 PIIR1 PIIR0 Bits Description Reserved [31:4] Reserved. PWM Timer Channel 3 Interrupt Flag PIIR3 This flag is set by hardware when PWM3 down-counter reaches zero, software can clear this bit by writing a one into this bit.
Page 363: Watchdog Timer (Wdt)
NUC970 Technical Reference Manual 5.13 Watchdog Timer (WDT) 5.13.1 Overview The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
Page 364: Functional Description
NUC970 Technical Reference Manual WDT_S(CLKDIV8[9:8]) WDT(PCLKEN0[0]) 12MHz(HXT) WDT _CLK 12MHz/128 PCLK/4096 32.768 kHz (LXT) Figure 5.13-2 Watchdog Timer Clock Control The WDT peripheral clock is enabled in WDT (PCLKEN0[0]) and clock source can be selected in WDT_S (CLKDIV8[9:8]). WDT controller also can be forced enabled and active in 32 kHz after chip powered on or reset while WDTON is configure to 1 in PWRON register.
Page 365: Figure 5.13-3 Watchdog Timer Time-Out Interval And Reset Period Timing
NUC970 Technical Reference Manual (3/18/130/1026) * T (3/18/130/1026) * T (3/18/130/1026) * T (3/18/130/1026) * T (3/18/130/1026) * T (3/18/130/1026) * T Table 5.13-1 Watchdog Time-out Interval Period Selection WDT_S (CLK_DIVCTL8 [9:8]) Watchdog Reset Period (T 5.3 us 682 us 87.3 ms 1.95 ms Table 5.13-2 Watchdog Reset Period Selection...
Page 366 NUC970 Technical Reference Manual while WDT time-out interrupt signal is generated and WKEN (WDT_CTL[4]) enabled. Notice that user should set XTAL_EN (CLK_PMCON[0]) to enable crystal clock source before system entries power down mode because the system peripheral clock are disabled when system is power down mode.
Page 367: Register Map
NUC970 Technical Reference Manual 5.13.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value WDT Base Address: WDT_BA = 0xB800_1800 WDT_CTL WDT_BA+0x00 WDT Control Register 0x0000_0700 WDT_ALTCTL WDT_BA+0x04 WDT Alternative Control Register 0x0000_0000 Publication Release Date: Dec.
Page 368: Register Description
NUC970 Technical Reference Manual 5.13.7 Register Description Publication Release Date: Dec. 15, 2015 - 368 - Revision V1.30...
Page 369 NUC970 Technical Reference Manual WDT Control Register (WDT_CTL) Register Offset Description Reset Value WDT_CTL WDT_BA+0x00 WDT Control Register 0x0000_0700 ICEDEBUG Reserved Reserved Reserved TOUTSEL WDTEN INTEN Reserved WKEN RSTF RSTEN RSTCNT Bits Description ICE Debug Mode Acknowledge Disable Control (Write Protect) 0 = ICE debug mode acknowledgement affects WDT counting.
Page 370 NUC970 Technical Reference Manual WDT Time-out Interrupt Enable Control (Write Protect) If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. INTEN 0 = WDT time-out interrupt Disabled. 1 = WDT time-out interrupt Enabled. Note: This bit is write protected.
Page 371 NUC970 Technical Reference Manual WDT Alternative Control Register (WDT_ALTCTL) Register Offset Description Reset Value WDT_ALTCTL WDT_BA+0x04 WDT Alternative Control Register 0x0000_0000 Reserved Reserved Reserved Reserved WTRDSEL Bits Description [31:2] Reserved Reserved. WDT Reset Delay Selection (Write Protect) When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened.
Page 372: Windowed Watchdog Timer (Wwdt)
NUC970 Technical Reference Manual 5.14 Windowed Watchdog Timer (WWDT) 5.14.1 Overview The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 5.14.2 Features ...
Page 373: Function Description
NUC970 Technical Reference Manual The WWDT peripheral clock is enabled in WWDT (PCLKEN[1]) and clock source can be selected in WWDT_S[1:0] (CLKDIV8[11:10]). 5.14.5 Function Description The WWDT includes a 6-bit down counter with programmable prescale value to define different WWDT time-out intervals. The clock source of 6-bit WWDT is based on system clock divide 4096 (PCLK/4096), external 12 MHz oscillator or internal 32 kHz oscillator with a programmable 11-bit prescale counter value which controlled by PSCSEL (WWDT_CTL[11:8]).
Page 374 NUC970 Technical Reference Manual 5.14.5.2 WWDT Compare Match Interrupt During down counting by the WWDT counter, the WWDTIF (WWDT_STATUS[0]) is set to 1 while the WWDT counter value (CNTDAT) is equal to window compare value (CMPDAT) and WWDTIF can be cleared by user; if INTEN (WWDT_CTL[1]) is also set to 1 by user, the WWDT compare match interrupt signal is generated also while WWDTIF is set to 1 by hardware.
Page 375: Figure 5.14-3 Wwdt Reset And Reload Behavior
NUC970 Technical Reference Manual 5.14.5.3 WWDT Reset System When WWDTIF (WWDT_STATUS[0]) is generated, user must reload WWDT counter value to 0x3F by writing 0x00005AA5 to WWDT_RLDCNT register, and also to prevent WWDT counter value reached to 0 and generate WWDT reset system signal to info system reset. If current CNTDAT (WWDT_CNT[5:0]) is larger than CMPDAT (WWDT_CTL[21:16]) and user writes 0x00005AA5 to the WWDT_RLDCNT register, the WWDT reset system signal will be generated immediately to cause chip reset also.
Page 376: Table 5.14-2 Cmpda Setting Limitation
NUC970 Technical Reference Manual 5.14.5.4 WWDT Window Setting Limitation When user writes 0x00005AA5 to WWDT_RLDCNT register to reload WWDT counter value to 0x3F, it needs 3 WWDT clocks to sync the reload command to actually perform reload action. Notice that if user set PSCSEL (WWDT_CTL[11:8]) to 0000, the counter prescale value should be as 1, and the CMPDAT (WWDT_CTL[21:16]) must be larger than 2.
Page 377: Register Map
NUC970 Technical Reference Manual 5.14.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value WWDT Base Address: WWDT_BA = 0xB800_1900 WWDT_RLDC WWDT_BA+0x00 WWDT Reload Counter Register 0x0000_0000 WWDT_CTL WWDT_BA+0x04 WWDT Control Register 0x003F_0800 WWDT_STAT WWDT_BA+0x08...
Page 378: Register Description
NUC970 Technical Reference Manual 5.14.7 Register Description Publication Release Date: Dec. 15, 2015 - 378 - Revision V1.30...
Page 379 NUC970 Technical Reference Manual WWDT Reload Counter Register (WWDT_RLDCNT) Register Offset Description Reset Value WWDT_RLDC WWDT_BA+0x00 WWDT Reload Counter Register 0x0000_0000 WWDT_RLDCNT[31:24] WWDT_RLDCNT[23:16] WWDT_RLDCNT[15:8] WWDT_RLDCNT[7:0] Bits Description WWDT Reload Counter Register Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. Note: User can only write WWDT_RLDCNT register to reload WWDT counter value [31:0] WWDT_RLDCNT...
Page 380 NUC970 Technical Reference Manual WWDT Control Register (WWDT_CTL) Register Offset Description Reset Value WWDT_CTL WWDT_BA+0x04 WWDT Control Register 0x003F_0800 Note: This register can be write only one time after chip is powered on or reset. ICEDEBUG Reserved Reserved CMPDAT Reserved PSCSEL Reserved INTEN...
Page 381 NUC970 Technical Reference Manual 1011 = Pre-scale is 512; Max time-out period is 512 * 64 * T WWDT 1100 = Pre-scale is 768; Max time-out period is 768 * 64 * T WWDT 1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * T WWDT 1110 = Pre-scale is 1536;...
Page 382 NUC970 Technical Reference Manual WWDT Status Register (WWDT_STATUS) Register Offset Description Reset Value WWDT_STAT WWDT_BA+0x08 WWDT Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WWDTRF WWDTIF Bits Description [31:2] Reserved Reserved. WWDT Timer-out Reset Flag This bit indicates the system has been reset by WWDT time-out reset or not. WWDTRF 0 = WWDT time-out reset did not occur.
Page 383 NUC970 Technical Reference Manual WWDT Counter Value Register (WWDT_CNT) Register Offset Description Reset Value WWDT_CNT WWDT_BA+0x0C R WWDT Counter Value Register 0x0000_003F Reserved Reserved Reserved Reserved CNTDAT Bits Description [31:6] Reserved Reserved. WWDT Counter Value CNTDAT [5:0] CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. Publication Release Date: Dec.
Page 384: Real Time Clock (Rtc)
NUC970 Technical Reference Manual 5.15 Real Time Clock (RTC) 5.15.1 Overview The Real Time Clock (RTC) controller provides the real time clock and calendar information. The clock source of RTC controller is from an external 32.768 kHz low-speed crystal which connected at pins X32_IN and X32_OUT (refer to pin Description).
Page 385: Block Diagram
NUC970 Technical Reference Manual 5.15.3 Block Diagram Alarm interrupt generator Alarm interrupt Compensate frequency by software Time alarm Calendar alarm counter counter XTALOUT 1 Day 1 Hz Time counter Calendar counter 2^15 clock divider Day of the week counter Select one Tick Tick interrupt period generator...
Page 386 NUC970 Technical Reference Manual be raised high. Then user can feel free to write data into register. RWENF will keep high for a short period (about 24ms) and it will be pull low by internal state machine automatically. 5.15.5.3 Frequency Compensation The RTC_FREQADJ allows software control digital compensation of a 32.768 KHz crystal oscillator.
Page 387: Register Map
NUC970 Technical Reference Manual 5.15.6 Register Map Register Offset Description Reset Value RTC Base Address: RTC_BA = 0xB800_4000 RTC_INIT RTC_BA+0x000 RTC Initiation Register 0x0000_0000 RTC_RWEN RTC_BA+0x004 RTC Access Enable Register 0x0000_0000 RTC_FREQADJ RTC_BA+0x008 RTC Frequency Compensation Register 0x0000_0700 RTC_TIME RTC_BA+0x00C RTC Time Counter Register 0x0000_0000 RTC_CAL...
Page 388 NUC970 Technical Reference Manual RTC_SPR15 RTC_BA+0x07C RTC Spare Register 15 0x0000_0000 Publication Release Date: Dec. 15, 2015 - 388 - Revision V1.30...
Page 389: Register Description
NUC970 Technical Reference Manual 5.15.7 Register Description Publication Release Date: Dec. 15, 2015 - 389 - Revision V1.30...
Page 390 NUC970 Technical Reference Manual RTC Initiation Register (RTC_INIT) Register Offset Description Reset Value RTC_INIT RTC_BA+0x000 RTC Initiation Register 0x0000_0000 INIT INIT INIT INIT INIT/Active Bits Description RTC Initiation After RTC block is powered on, RTC is at reset state. User has to write a number (0x [31:1] INIT a5eb1357) to INIT to make RTC leaving reset state.
Page 391 NUC970 Technical Reference Manual RTC Access Enable Register (RTC_RWEN) Register Offset Description Reset Value RTC_RWEN RTC_BA+0x004 RTC Access Enable Register 0x0000_0000 Reserved Reserved RWENF RWENPASSWD RWENPASSWD Bits Description Reserved [31:17] Reserved. RTC Register Access Enable Flag (Read Only) 0 = RTC register read/write Disabled. [16] RWENF 1 = RTC register read/write Enabled.
Page 392 NUC970 Technical Reference Manual RTC Frequency Compensation Register (RTC_FREQADJ) Register Offset Description Reset Value RTC_FREQADJ RTC_BA+0x008 RTC Frequency Compensation Register 0x0000_0700 Reserved Reserved Reserved INTEGER Reserved FRACTION Bits Description Reserved [31:12] Reserved. Integer Part Integer part of RTC_FREQADJ[11:8] Integer part of RTC_FREQADJ[11:8] detected value detected value...
Page 393 NUC970 Technical Reference Manual Fraction part: 0.27 X 60 = 16.2(0x10) => RTC_FREQADJ[5:0] = 0x10 Publication Release Date: Dec. 15, 2015 - 393 - Revision V1.30...
Page 394 NUC970 Technical Reference Manual RTC Time Counter Register (RTC_TIME) Register Offset Description Reset Value RTC_TIME RTC_BA+0x00C RTC Time Counter Register 0x0000_0000 Reserved Reserved TENHOUR HOUR Reserved TENMINUTE MINUTE Reserved TENSECOND SECOND Bits Description Reserved [31:22] Reserved. [21:20] TENHOUR 10 Hour Time Digit (0 ~ 2) [19:16] HOUR 1 Hour Time Digit (0 ~ 9)
Page 395 NUC970 Technical Reference Manual RTC Calendar Counter Register (RTC_CAL) Register Offset Description Reset Value RTC_CAL RTC_BA+0x010 RTC Calendar Counter Register 0x0005_0101 Reserved TENYEAR YEAR Reserved TENMONTH MONTH Reserved TENDAY Bits Description Reserved [31:24] Reserved. [23:20] TENYEAR 10-Year Calendar Digit (0 ~ 9) [19:16] YEAR 1-Year Calendar Digit (0 ~ 9)
Page 396 NUC970 Technical Reference Manual RTC Time Format Selection Register (RTC_TIMEFMT) Register Offset Description Reset Value RTC_TIMEFMT RTC_BA+0x014 RTC Time Format Selection Register 0x0000_0001 Reserved Reserved Reserved Reserved 24HEN Bits Description [31:1] Reserved Reserved. 24HEN 24-hour / 12-hour Mode Selection It indicate that TLR and TAR are in 24-hour mode or 12-hour mode 0 = 12-hour time format with am and pm indication selected.
Page 397 NUC970 Technical Reference Manual RTC Day of the Week Register (RTC_WEEKDAY) Register Offset Description Reset Value RTC_WEEKDAY RTC_BA+0x018 RTC Day of the Week Register 0x0000_0006 Reserved Reserved Reserved Reserved WEEKDAY Bits Description Reserved [31:3] Reserved. Day of the Week 0x0 = Sunday. 0x1 = Monday.
Page 398 NUC970 Technical Reference Manual RTC Time Alarm Register (RTC_TALM) Register Offset Description Reset Value RTC_TALM RTC_BA+0x01C RTC Time Alarm Register 0x0000_0000 Reserved HRALM_MSK MINALM_MSK SECALM_MSK Reserved Reserved TENHOUR HOUR Reserved TENMINUTE MINUTE Reserved TENSECOND SECOND Bits Description Reserved [31] Reserved. Hour Alarm Mask This bit control if TENHOUR (RTC_TALM[21:20] and HOUR (RTC_TALM[19:16]) could trigger RTC timer alarm.
Page 399 NUC970 Technical Reference Manual [11:8] MINUTE 1 Min Time Digit (0 ~ 9) Reserved Reserved. [6:4] TENSECOND 10 Sec Time Digit (0 ~ 5) [3:0] SECOND 1 Sec Time Digit (0 ~ 9) Note1: RTC_TALM is a BCD digit counter and RTC will not check loaded data. Note2: Set all MSK bits high would disable calendar alarm functionality.
Page 400 NUC970 Technical Reference Manual RTC Calendar Alarm Register (RTC_CALM) Register Offset Description Reset Value RTC_CALM RTC_BA+0x020 RTC Calendar Alarm Register 0x0000_0000 WKDALM_MSK YRALM_MSK MONALM_MSK DAYALM_MSK Reserved WEEKDAY TENYEAR YEAR Reserved TENMONTH MONTH Reserved TENDAY Bits Description Day of Week Alarm Mask This bit controls if WEEKDAY (RTC_CALM[26:24]) could trigger RTC timer alarm.
Page 401 NUC970 Technical Reference Manual Day of the Week 000 = Sunday. 001 = Monday. 010 = Tuesday. WEEKDAY 011 = Wednesday. [26:24] 100 = Thursday. 101 = Friday. 110 = Saturday. 111 = Reserved. [23:20] TENYEAR 10-Year Calendar Digit (0 ~ 9) [19:16] YEAR 1-Year Calendar Digit (0 ~ 9)
Page 402 NUC970 Technical Reference Manual RTC Leap Year Indicator Register (RTC_LEAPYEAR) Register Offset Description Reset Value RTC_LEAPYEAR RTC_BA+0x024 RTC Leap Year Indicator Register 0x0000_0000 Reserved Reserved Reserved Reserved LEAPYEAR Bits Description [31:1] Reserved Reserved. Leap Year Indicator (Read Only) LEAPYEAR 0 = It indicates that this year is not a leap year. 1 = It indicates that this year is leap year.
Page 403 NUC970 Technical Reference Manual RTC Interrupt Enable Register (RTC_INTEN) Register Offset Description Reset Value RTC_INTEN RTC_BA+0x028 RTC Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved KEYPRESIEN RELALMIEN PWRSWIEN WAKEUPIEN TICKIEN ALMIEN Bits Description [31:6] Reserved Reserved. Key Press Interrupt Enable KEYPRESIEN 0 = Key Press interrupt disable.
Page 404 NUC970 Technical Reference Manual RTC Interrupt Status Register (RTC_INTSTS) Register Offset Description Reset Value RTC_INTSTS RTC_BA+0x02C RTC Interrupt Status Register 0x0000_0000 REGWRBUSY Reserved Reserved Reserved Reserved KEYPRESINT RELALMINT PWRSWINT WAKEUPINT TICKINT ALMINT Bits Description Register Write Operation Busy [31] REGWRBUSY 0 = The new register write operation is acceptable.
Page 405 NUC970 Technical Reference Manual Wakeup Interrupt Status This bit indicates the RTC generates a wakeup event to wakeup system from power down mode. In RTC, the wakeup source includes the RTC alarm and RTC related alarm. WAKEUPINT User can write 1 to clear this bit. 0 = System power control pin SYS_PWREN state didn’t change.
Page 406 NUC970 Technical Reference Manual RTC Time Tick Register (RTC_TICK) Register Offset Description Reset Value RTC_TICK RTC_BA+0x030 RTC Time Tick Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description RTC Tick Time Interrupt Request Interval The TTR [2:0] is used to select tick time interrupt request interval. The period of tick time interrupt is as follow: 000 = 1 second.
Page 407 NUC970 Technical Reference Manual RTC Power Control Register (RTC_PWRCTL) Register Offset Description Reset Value RTC_PWRCTL RTC_BA+0x034 RTC Power Control Register 0x0000_7000 Reserved ALARM_MODE RELALM_TIME RELALM_TIME PWROFF_TIME PWRON_TIME PWR_KEY Reserved EDGE_TRIG REL_ALARM_EN ALARM_EN HW_PCLR_EN SW_PCLR PWR_ON Bits Description [31:29] Reserved Reserved. Alarm Function Mode Selection This bit controls if pin SYS_PWREN be forced to low when RTC Time and Date counter or relative alarm counter meets the alarm condition.
Page 408 NUC970 Technical Reference Manual Relative Alarm Function Enable Set this bit high would enable the relative alarm function. When the relative alarm condition met, RTC would set RELALMINT (RTC_INTSTS[4]) interrupt status to high. REL_ALARM_EN 0 = Relative alarm function Disabled. 1 = Relative alarm function Enabled.
Page 409 NUC970 Technical Reference Manual RTC Power Control Counter Register (RTC_PWRCNT) Register Offset Description Reset Value RTC_PWRCNT RTC_BA+0x038 RTC Power Control Counter Register 0x0000_0000 Reserved Reserved PWROFF_CNT PWRON_CNT RELARM_CNT RELARM_CNT Bits Description [31:21] Reserved Reserved. Power Off Counter Current Value PWR_OFF_CNT This field shows the current value of power off counter.
Page 410 NUC970 Technical Reference Manual RTC Spare Register (RTC_SPRn, n = 0, 1, .., 15) Register Offset Description Reset Value RTC_SPR0 RTC_BA+0x040 RTC Spare Register 0 0x0000_0000 RTC_SPR1 RTC_BA+0x044 RTC Spare Register 1 0x0000_0000 RTC_SPR2 RTC_BA+0x048 RTC Spare Register 2 0x0000_0000 RTC_SPR3 RTC_BA+0x04C RTC Spare Register 3...
Page 411: Uart Interface Controller (Uart)
8-bit data format with 1-bit stop bit are required in accordance with the LIN standard. For the NUC970 series, another alternate function of UART controllers is RS-485 9-bit mode function, and direction control provided by RTS pin to implement the function by software. The RS-485 mode is selected by setting the (FUN_SEL(UA_FUN_SEL[2:0]) = 011) to select RS-485 function.
Page 412: Features
NUC970 Technical Reference Manual 5.16.2 Features  Full duplex, asynchronous communications  Separate receive / transmit 64/16 bytes entry FIFO for data payloads  Supports hardware auto flow control/flow control function (CTS, RTS) and programmable RTS flow control trigger level ...
Page 413: Block Diagram
NUC970 Technical Reference Manual 5.16.3 Block Diagram APB_BUS Status & Control Status & Control Control and Status TX_FIFO RX_FIFO Registers TX Shift Register RX Shift Register Baud Rate Baud Out Baud Out Generator Serial Data Out Serial Data In UART_CLK IrDA Encode IrDA Decode UART / IrDA / LIN / RS-485 Device or Transceiver...
Page 414: Basic Configuration
NUC970 Technical Reference Manual (UA_FSR), and line control register (UA_LCR) for transmitter and receiver. The time-out control register (UA_TOR) identifies the condition of time-out interrupt. This register set also includes the interrupt enable register (UA_IER) and interrupt status register (UA_ISR) to enable or disable the responding interrupt and to identify the occurrence of the responding interrupt.
Page 415: Figure 5.16-3 Uart Line Control Of Word And Stop Length Setting
NUC970 Technical Reference Manual parity bit. The following tables list the UART word and stop bit length settings and the UART parity bit settings. Word Length (Bit) Stop Length (Bit) (UA_LCR[2]) (UA_LCR[1:0]) Figure 5.16-3 UART Line Control of Word and Stop Length Setting Parity Description Type...
Page 416: Table 5.16-1 Baud Rate Equation Table
NUC970 Technical Reference Manual Mode DIV_X_EN DIV_X_ONE DIVIDER X Baud Rate Equation Don’t Care Disable UART_CLK / [16 * (A+2)] Enable UART_CLK / [(B+1) * (A+2)] , B must >= 8 Don’t care Enable UART_CLK / (A+2), A must >=9 Table 5.16-1 Baud Rate Equation Table System Clock = XT1_IN (12 MHz) Mode0...
Page 417: Figure 5.16-5 Uart Auto-Flow Control Block Diagram
NUC970 Technical Reference Manual 5.16.5.4 Auto-Flow Control The UART controllers support auto-flow control function that uses two low-level signals, CTSn (clear- to-send) and RTSn (request-to-send) to control the flow of data transfer between the UART and external devices (ex: Modem). When auto-flow is enabled, the UART is not allowed to receive data until the UART asserts RTSn (RTSn high) to external device.
Page 418: Figure 5.16-7 Uart Ctsn Wake-Up Case 2
NUC970 Technical Reference Manual sleep mode CTSn WAKE_ SYSTEM INT_WAKE Figure 5.16-7 UART CTSn Wake-Up Case 2 5.16.5.6 IrDA Mode The UART Controller provides Serial IrDA (SIR, Serial Infrared) transmit encoder and receive decoder function. The IrDA_EN(UART_FUN_SEL[2:0] = 010) bit are used to select IrDA function. The SIR specification defines a short-range infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit.
Page 419 NUC970 Technical Reference Manual IrDA SIR Transmit Encoder The IrDA SIR Transmit Encoder modulate Non-Return-to Zero (NRZ) transmit bit stream output from UART. The IrDA SIR physical layer specifies use of Return-to-Zero, Inverted (RZI) modulation scheme which represent logic 0 as an infra light pulse. The modulated output pulse stream is transmitted to an external output driver and infrared Light Emitting Diode.
Page 420 NUC970 Technical Reference Manual IrDA SIR Receive Decoder The IrDA SIR Receive Decoder demodulates the return-to-zero bit stream from the input detector and outputs the NRZ serial bits stream to the UART received data input. The decoder input is normally high in the idle state.
Page 421: Figure 5.16-9 Irda Tx/Rx Timing Diagram
NUC970 Technical Reference Manual IrDA SIR Operation The IrDA SIR Encoder/Decoder provides functionality which converts between UART data stream and half duplex serial SIR interface. Refer to UA_IRCR register for detail description. The following diagram shows the IrDA encoder/decoder waveform. STOP BIT START BIT SOUT...
Page 422 NUC970 Technical Reference Manual RS-485 Normal Multidrop Operation Mode (NMM) In RS-485 Normal Multi-drop operation mode, software must decide whether receiver will ignore data before an address byte is detected (bit 9 = “1”). If software wants to receive any data before address byte detected, the flow is disable RX_DIS(UA_FCR [8]) then enable RS485_NMM(UA_ALT_CSR[8]) and the receiver will received any data.
Page 423 NUC970 Technical Reference Manual RS-485 Auto Address Detection Operation Mode (AAD) In RS-485 Auto Address Detection Operation Mode, the receiver will ignore any data until an address byte is detected (bit9 =1) and the address byte data match the ADDR_MATCH(UA_ALT_CSR[31:24]) value.
Page 424 NUC970 Technical Reference Manual RS-485 Auto Direction Mode (AUD) Another option function of RS-485 controllers is RS-485 auto direction control function. The RS-485 driver control is implemented using the RTS control signal from an asynchronous serial port to enable the RS-485 driver. The RTS line is connected to the RS-485 driver enable such that setting the RTS line to high (logic 1) enables the RS-485 driver.
Page 425: Figure 5.16-10 Rs-485 Frame Structure
NUC970 Technical Reference Manual Program Sequence example: Program FUN_SEL(UA_FUN_SEL[2:0]) to select RS-485 function. Program the RX_DIS(UA_FCR[8]) to determine enable or disable RS-485 receiver Program the RS485_NMM(UA_ALT_CSR[6]) or RS485_AAD(UA_ALT_CSR[9]) mode. If the RS-485_AAD mode is selected, the ADDR_MATCH is programmed for auto address match value.
Page 426: Figure 5.16-11 Lin Frame Structure
NUC970 Technical Reference Manual Structure of LIN Frame According to the LIN protocol, all information is transmitted packed as frames; a frame consist (provided by the master task) a header and a response (provided by a slave task). That is any communication on the LIN bus is started by the master sending a header, followed by the response.
Page 427 NUC970 Technical Reference Manual LIN Master Mode The UART controller supports LIN master mode. In LIN mode, each byte field is initialed by a start bit with value zero (dominant), followed by 8 data bits (WLS(UA_LCR[1:0]) = 11) and no parity bit, LSB is first and ended by 1 stop bit (NSB(UA_LCR[2]) = 1) with value one (recessive) in accordance with the LIN standard.
Page 428 NUC970 Technical Reference Manual Note3: If the header includes “break field, sync field and frame ID field”, software must fill frame ID in LIN_PID(UA_LIN_CTL[31:24]) before trigger header transmission (setting the LIN_SHD(UA_LIN_CTL[8]) bit. The frame ID parity can be generated by software or hardware depends on LIN_IDPEN(UA_LIN_CTL[9]).
Page 429: Figure 5.16-12 Break Detection In Lin Mode
NUC970 Technical Reference Manual LIN break and delimiter detection When software enable the break detection function by setting LIN_BKDET_EN(UA_LIN_CTL[10]), the break detection circuit is activated. When the break detection function is enabled, the circuit looks at the input SIN pin for a start signal. If more than 11 bits are detected as 0, and are followed by a delimiter character, the LIN_BKDET_F (UA_LIN_SR[8]) flag is set at the end of break field.
Page 430: Figure 5.16-13 Relationship Between Break Detection And Frame Error Detection
NUC970 Technical Reference Manual Case 1 : break occurring at master sending break state SOUT IDLE Break Sync (0x55) Data IDLE Break Sync (0x55) Data RDA_IF / FEF 1 bit time LIN_BRDET_F Case 2 : break occurring after an idle (not master sending break state) SOUT IDLE IDLE...
Page 431 NUC970 Technical Reference Manual LIN response transmission The LIN master can transmitter response (master is the publisher of the response) and receive response (master is the subscriber of the response). When the master is the publisher of the response, the master send response by writing UA_THR register, and if the master is the subscriber of the response, the master will received n data bytes by other slave node (the maximum of n is 8).
Page 432 NUC970 Technical Reference Manual LIN Slave Mode The UART controller support LIN slave mode by setting the LINS_EN(UA_LIN_CTL[0]) bit. In LIN mode, each byte field is initialed by a start bit with value zero (dominant), followed by 8 data bits (WLS(UA_LCR[1:0]) = 11) and no parity bit, LSB is first and ended by 1 stop bit (NSB(UA_LCR[2]) = 1) with value one (recessive) in accordance with the LIN standard.
Page 433 NUC970 Technical Reference Manual LIN header reception According to the LIN protocol, a slave node must wait for a valid header which coming from the master node. Then application has to take following action (depending on the master header frame ID value). Receive the response.
Page 434 NUC970 Technical Reference Manual LIN response transmission The LIN slave can transmitter response (slave is the publisher of the response) and receive response (slave is the subscriber of the response). When the slave is the publisher of the response, the slave send response by writing UA_THR register, and if the slave is the subscriber of the response, the slave received n data bytes by other slave node (the maximum of n is 8).
Page 435 NUC970 Technical Reference Manual LIN header time-out error The LIN slave controller contains a header time-out counter. If the entire header is not received within the maximum time limit of 57 bit times, the header error flag LIN_HERR_F (UA_LIN_SR [1]) will be set.
Page 436 NUC970 Technical Reference Manual Mute mode and LIN wake-up In mute mode, it allows detection of headers only and prevents the reception of any other characters. User can enable mute mode by setting LIN_MUTE_EN(UA_LIN_CTL[4]) bit and wake-up condition can be selected by LIN_HEAD_SEL(UA_LIN_CTL[23:22]). Note: It is recommended to put LIN in mute mode by setting LIN_MUTE_EN(UA_LIN_CTL[4]) bit after checksum transmission.
Page 437 NUC970 Technical Reference Manual Slave mode without automatic resynchronization User can disable automatic resynchronization function to fix the communication baud rate. When operating in without automatic resynchronization mode, software needs some initial process, and the initialization process flow of without automatic resynchronization mode is shown as follows: 1.
Page 438: Figure 5.16-14 Lin Sync Field Measurement
NUC970 Technical Reference Manual Slave mode with automatic resynchronization User can enable automatic resynchronization function by setting LINS_ARS_EN(UA_LIN_CTL[2]) bit. In automatic resynchronization mode, the controller will adjust the baud rate generator after each sync field reception. The other program sequence is similar to Slave mode without automatic resynchronization section.
Page 439: Figure 5.16-15 Ua_Baud Update Method
NUC970 Technical Reference Manual Case1: UA_BAUD read/write operation when LINS_DUM_EN(UA_LIN_CTL[3]) = 0 Case2: UA_BAUD read/write operation when LINS_DUM_EN(UA_LIN_CTL[3]) = 1 Figure 5.16-15 UA_BAUD Update Method Publication Release Date: Dec. 15, 2015 - 439 - Revision V1.30...
Page 440 NUC970 Technical Reference Manual Deviation error on the sync field When operating in automatic resynchronization mode, the controller will check the deviation error on the sync field. The deviation error is checked by comparing the current baud rate with the received sync field.
Page 441 NUC970 Technical Reference Manual LIN header error detection In LIN slave function mode, when user enables header detection function by setting LINS_HDET_EN(UA_LIN_CTL[1]) bit, the hardware will handle the header detect flow. If the header has error, the LIN header error flag LINS_HERR_F(UA_LIN_SR[1]) will be set and an interrupt is generated if the LIN_RX_BRK_IEN(UA_IER[8]) bit is set.
Page 442: Table 5.16-3 Uart Interrupt Sources And Flag List In Software Mode
NUC970 Technical Reference Manual RX_OVER_ERETRY Transmit Holding Register Empty Interrupt THRE_IEN THRE_INT THRE_IF Write UA_THR INT_THRE Receive Data Available Interrupt RDA_IEN RDA_INT RDA_IF Read UA_RBR INT_RDA Table 5.16-3 UART Interrupt Sources and Flag List in Software Mode 5.16.5.10 Time-Out The time-out counter resets and starts counting (the counting clock = baud rate clock) whenever the RX FIFO receives a new data word.
Page 443: Register Map
NUC970 Technical Reference Manual 5.16.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value UART Base Address: UART0_BA = 0xB800_0000 UART1_BA = 0xB800_0100 UART2_BA = 0xB800_0200 UART3_BA = 0xB800_0300 UART4_BA = 0xB800_0400 UART5_BA = 0xB800_0500 UART6_BA = 0xB800_0600 UART7_BA = 0xB800_0700...
Page 444 NUC970 Technical Reference Manual UAn_BAUD UARTn_BA+0x024 R/W UART n Baud Rate Divisor Register 0x0F00_0000 n=0,1,2,3,4,5,6,7 ,8,9,10 UAn_IRCR UARTn_BA+0x028 R/W UART n IrDA Control Register 0x0000_0040 n=0,1,2,3,4,5,6,7 ,8,9,10 UAn_ALT_CSR UARTn_BA+0x02C R/W UART n Alternate Control/Status Register 0x0000_000C n=0,1,2,3,4,5,6,7 ,8,9,10 UAn_FUN_SEL UARTn_BA+0x030 R/W UART n Function Select Register 0x0000_0000 n=0,1,2,3,4,5,6,7...
Page 445: Register Description
NUC970 Technical Reference Manual 5.16.7 Register Description Publication Release Date: Dec. 15, 2015 - 445 - Revision V1.30...
Page 446 NUC970 Technical Reference Manual UART n Receive Buffer Register (UAn_RBR) Register Offset Description Reset Value UAn_RBR UARTn_BA+0x000 R UART n Receive Buffer Register Undefined n=0,1,2,3,4,5,6, 7,8,9,10 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Receive Buffer (Read Only) [7:0] By reading this register, the UART will return an 8-bit data received from RX pin (LSB first).
Page 447 NUC970 Technical Reference Manual UART n Transmit Holding Register (UAn_THR) Register Offset Description Reset Value UAn_THR UARTn_BA+0x000 W UART n Transmit Holding Register Undefined n=0,1,2,3,4,5,6, 7,8,9,10 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Transmit Holding Register [7:0] By writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first).
Page 448 NUC970 Technical Reference Manual UART n Interrupt Enable Register (UAn_IER) Register Offset Description Reset Value UAn_IER UARTn_BA+0x004 R/W UART n Interrupt Enable Register 0x0000_0000 n=0,1,2,3,4,5,6,7 ,8,9,10 Reserved Reserved TIME_OUT_ Reserved AUTO_CTS_EN AUTO_RTS_EN Reserved LIN_RX_BRK_IEN Reserved WAKE_EN BUF_ERR_IEN RTO_IEN MODEM_IEN RLS_IEN THRE_IEN RDA_IEN Bits...
Page 449 NUC970 Technical Reference Manual Note: CTS change will wake up chip from Power-down mode. Buffer Error Interrupt Enable Control BUF_ERR_IEN 0 = INT_BUF_ERR masked off. 1 = INT_BUF_ERR Enabled. RX Time-out Interrupt Enable Control RTO_IEN 0 = INT_TOUT masked off. 1 = INT_TOUT Enabled.
Page 450 NUC970 Technical Reference Manual UART n FIFO Control Register (UAn_FCR) Register Offset Description Reset Value UAn_FCR UARTn_BA+0x008 R/W UART n FIFO Control Register 0x0000_0000 n=0,1,2,3,4,5,6,7 ,8,9,10 Reserved Reserved RTS_TRI_LEV Reserved RX_DIS RFITL Reserved Reserved Bits Description [31:20] Reserved Reserved. RTS Trigger Level for Auto-flow Control Use 0000 = 1 Trigger Level (Bytes).
Page 451 NUC970 Technical Reference Manual 0100 = 30/14 (High-speed/Normal Speed) Trigger Level (Bytes). 0101 = 46/14 (High-speed/Normal Speed) Trigger Level (Bytes). 0110 = 62/14 (High-speed/Normal Speed) Trigger Level (Bytes). others = 62/14 (High-speed/Normal Speed) Trigger Level (Bytes). Reserved Reserved. TX Field Software Reset When TFR(UA_FCR[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
Page 452 NUC970 Technical Reference Manual UART n Line Control Register (UAn_LCR) Register Offset Description Reset Value UAn_LCR UARTn_BA+0x00C R/W UART n Line Control Register 0x0000_0000 n=0,1,2,3,4,5,6,7 ,8,9,10 Reserved Reserved Reserved Reserved Bits Description [31:7] Reserved Reserved. Break Control 0 = The serial data output (TX) is not forced to the Spacing State (logic 0). 1 = The serial data output (TX) is forced to the Spacing State (logic 0).
Page 453 NUC970 Technical Reference Manual 01 = 6-bit character length. 10 = 7-bit character length. 11 = 8-bit character length. Publication Release Date: Dec. 15, 2015 - 453 - Revision V1.30...
Page 454 NUC970 Technical Reference Manual UART n MODEM Control Register (UAn_MCR) Register Offset Description Reset Value UAn_MCR UARTn_BA+0x010 UART n Modem Control Register 0x0000_0000 n=0,1,2,3,4,5,6,7 ,8,9,10 Reserved Reserved Reserved RTS_ST Reserved LEV_RTS Reserved Reserved Reserved Bits Description [31:14] Reserved Reserved. RTS Pin State (Read Only) 0 = This output pin status of RTS is ‘0’.
Page 455 NUC970 Technical Reference Manual RTS Trigger Level This bit can change the RTS trigger level. 0= Low level triggered. 1= High level triggered. UART Mode: LEV_RTS (MCR[9]) = 1 RTS Pin RTS_ST (MCR[13]) UART Mode: LEV_RTS (MCR[9]) = 0 RTS Pin RTS_ST (MCR[13]) LEV_RTS RS-485 Mode: LEV_RTS (MCR[9]) = 0...
Page 456 NUC970 Technical Reference Manual UART n Modem Status Register (UAn_MSR) Register Offset Description Reset Value UAn_MSR UARTn_BA+0x014 R/W UART n Modem Status Register 0x0000_0000 n=0,1,2,3,4,5,6,7 ,8,9,10 Reserved Reserved Reserved LEV_CTS Reserved CTS_ST Reserved DCTSF Bits Description [31:9] Reserved Reserved. CTS Trigger Level This bit can change the CTS trigger level.
Page 457 NUC970 Technical Reference Manual UART n FIFO Status Register (UAn_FSR) Register Offset Description Reset Value UAn_FSR UARTn_BA+0x018 UART n FIFO Status Register 0x1040_4000 n=0,1,2,3,4,5,6, 7,8,9,10 Reserved TE_FLAG Reserved TX_OVER_IF TX_FULL TX_EMPTY TX_POINTER RX_FULL RX_EMPTY RX_POINTER Reserved RS485_ADD_DETF SC_OVEREF Reserved RX_OVER_IF Bits Description [31:29]...
Page 458 NUC970 Technical Reference Manual UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one. Receiver FIFO Full (Read Only) 0 = RX FIFO is not full. [15] RX_FULL 1 = RX FIFO is full. Note: This bit is set when RX_POINTER is equal to 64/16(High Speed UART/Low Speed UART), otherwise is cleared by hardware.
Page 459 NUC970 Technical Reference Manual 0 = RX FIFO no overflow. 1 = RX FIFO overflow. Note: If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of High Speed UART/Low Speed UART, this bit will be set. Note: This bit is read only, but it can be cleared by writing ‘1’...
Page 460 NUC970 Technical Reference Manual UART n Interrupt Status Control Register (UAn_ISR) Register Offset Description Reset Value UAn_ISR UARTn_BA+0x01C R/W UART n Interrupt Status Register 0x0000_0002 n=0,1,2,3,4,5,6,7, 8,9,10 Reserved Reserved BUF_ERR_ LIN_INT Reserved TOUT_INT MODEM_INT RLS_INT THRE_INT RDA_INT LIN_IF Reserved BUF_ERR_IF TOUT_IF MODEM_IF RLS_IF...
Page 461 NUC970 Technical Reference Manual Transmit Holding Register Empty Interrupt Indicator (Read Only) This bit is set if THRE_IEN(UA_IER[1]) and THRE_IF(UA_ISR[1]) are both set to 1. THRE_INT 0 = No THRE interrupt is generated. 1 = THRE interrupt is generated. Receive Data Available Interrupt Indicator (Read Only) This bit is set if RDA_IEN(UA_IER[0]) and RDA_IF(UA_ISR[0]) are both set to 1.
Page 462 NUC970 Technical Reference Manual Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If RDA_IF RDA_IEN(UA_IER[0]) is enabled, the RDA interrupt will be generated. Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
Page 463 NUC970 Technical Reference Manual UART n Time-out Register (UAn_TOR) Register Offset Description Reset Value UAn_TOR UARTn_BA+0x020 R/W UART n Time-out Register 0x0000_0000 n=0,1,2,3,4,5,6, 7,8,9,10 Reserved Reserved TOIC Bits Description [31:16] Reserved Reserved. TX Delay Time Value This field is use to programming the transfer delay time between the last stop bit and next start bit.
Page 464 NUC970 Technical Reference Manual UART n Baud Rate Divider Register (UAn_BAUD) Register Offset Description Reset Value UAn_BAUD UARTn_BA+0x024 R/W UART n Baud Rate Divisor Register 0x0F00_0000 n=0,1,2,3,4,5,6,7 ,8,9,10 Reserved DIV_X_EN DIV_X_ONE DIVIDER_X Reserved Bits Description [31:30] Reserved Reserved. Divider X Enable Control 0 = Divider X Disabled (the equation of M = 16).
Page 465 NUC970 Technical Reference Manual UART n IrDA Control Register (UAn_IRCR) Register Offset Description Reset Value UAn_IRCR UARTn_BA+0x028 R/W UART n IrDA Control Register 0x0000_0040 n=0,1,2,3,4,5,6,7 ,8,9,10 Reserved Reserved Reserved INV_RX INV_TX Reserved TX_SELECT Reserved Bits Description [31:7] Reserved Reserved. TX Pulse Width 0 = IrDA TX output Pulse width is equal to UART’s 3/16 bit frame.
Page 466 NUC970 Technical Reference Manual UART n Alternate Control/Status Register (UAn_ALT_CSR) Register Offset Description Reset Value UAn_ALT_CSR UARTn_BA+0x02C R/W UART n Alternate Control/Status Register 0x0000_000C n=0,1,2,3,4,5,6, 7,8,9,10 ADDR_MATCH Reserved RS485_ADD_EN Reserved RS485_AUD RS485_AAD RS485_NMM LIN_TX_EN LIN_RX_EN Reserved UA_LIN_BKFL Bits Description Address Match Value [31:24] ADDR_MATCH This field contains the RS-485 address match values.
Page 467 NUC970 Technical Reference Manual The LIN TX header can be “break field” or “break and sync field” or “break, sync and frame ID field” depending on the setting LIN_HEAD_SEL(UA_LIN_CTL[23:22]) register. 0 = Send LIN TX header Disabled. 1 = Send LIN TX header Enabled. Note: When transmitter header field (it may be “break”...
Page 468 NUC970 Technical Reference Manual UART n Function Select Register (UAn_FUN_SEL) Register Offset Description Reset Value UAn_FUN_SEL UARTn_BA+0x030 R/W UART n Function Select Register 0x0000_0000 n=0,1,2,3,4,5,6, 7,8,9,10 Reserved Reserved Reserved Reserved FUN_SEL Bits Description [31:3] Reserved Reserved. Function Select Enable Control 000 = UART function.
Page 469 NUC970 Technical Reference Manual UART n LIN Control Register (UAn_LIN_CTL) Register Offset Description Reset Value UAn_LIN_CTL UARTn_BA+0x034 R/W UART n LIN Control Register 0x000C_0000 n=0,1,2,3,4,5,6, 7,8,9,10 LIN_PID LIN_HEAD_SEL LIN_BS_LEN LIN_BKFL LIN_BKDET_ LIN_LBDL Reserved BIT_ERR_EN LIN_RX_DIS LIN_IDPEN LIN_SHD Reserved LIN_MUTE_EN LINS_DUM_EN LINS_ARS_EN LINS_HDET_EN LINS_EN Bits Description...
Page 470 NUC970 Technical Reference Manual LIN Break/Sync Delimiter Length 00 = LIN break/sync delimiter length is 1 bit time. 10 = The LIN break/sync delimiter length is 2 bit time. 10 = The LIN break/sync delimiter length is 3 bit time. 11 = The LIN break/sync delimiter length is 4 bit time.
Page 471 NUC970 Technical Reference Manual LIN TX Send Header Enable Control The LIN TX header can be “break field” or “break and sync field” or “break, sync and frame ID field” depending on the setting LIN_HEAD_SEL(UA_LIN_CTL[23:22]) register. 0 = Send LIN TX header Disabled. LIN_SHD 1 = Send LIN TX header Enabled.
Page 472 NUC970 Technical Reference Manual UART n LIN Status Register (UAn_LIN_SR) Register Offset Description Reset Value UAn_LIN_SR UARTn_BA+0x038 UART n LIN Status Register 0x0000_0000 n=0,1,2,3,4,5,6, 7,8,9,10 Reserved Reserved Reserved BIT_ERR_F LIN_BKDET_F Reserved LINS_SYNC_F LINS_IDPERR_F LINS_HERR_F LINS_HDET_F Bits Description [31:10] Reserved Reserved. Bit Error Detect Status Flag (Read Only) 0 = The input pin (SIN) state is equals to the output pin (SOUT) state.
Page 473 NUC970 Technical Reference Manual LIN Slave Sync Field This bit indicates that the LIN sync field is being analyzed. When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit. 0 = The current character is not at LIN sync state.
Page 474: Smart Card Host Interface (Sc)
NUC970 Technical Reference Manual 5.17 Smart Card Host Interface (SC) 5.17.1 Overview The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully compliant with PC/SC Specifications. It also provides status of card insertion/removal. 5.17.2 Features ...
Page 475: Block Diagram
NUC970 Technical Reference Manual 5.17.3 Block Diagram The SC clock control and block diagram are shown as follows. The PCLK should be higher or equal than the frequency of peripheral clock (SCx_CLK). Clock Controller SC Controller CLK_KEEPx 1/(SCx_N+1) SCx_CLK Engine Clock SCx_EN SCx_N SCx_EN...
Page 476: Basic Configuration
NUC970 Technical Reference Manual 5.17.4 Basic Configuration The SC function pins are configured in SYS_GPA_MFPL, SYS_GPB_MFPL, SYS_GPE_MFPL and SYS_GPE_MPFH Multiple Function Pin Registers. SC Host Controller Pin description is shown as follows: Type Description SC_DATA Bi-direction SC Host Controller DATA SC_CD Input SC Host Controller Card Detect...
Page 477: Figure 5.17-4 Sc Activation Sequence
NUC970 Technical Reference Manual De-assert SC_RST to high by programming RSTSTS (SC_PINCTL[18]) to ‘1’. The activation sequence can be controlled in two ways. The procedure is shown as follows: Software Timing Control: Set SC_PINCTL and SC_TMRCTLx (x = 0, 1, 2) to process the activation sequence. SC_PWR, SC_CLK, SC_RST and SC_DATA pin state can be programmed by SC_PINCTL.
Page 478 NUC970 Technical Reference Manual The warm reset sequence is showed as follows. Set SC_RST to low by programming RSTSTS (SC_PINCTL[18]) to ‘0’. Set SC_DAT to high by programming DATSTS (SC_PINCTL[16]) to ‘1’. Set SC_RST to high by programming RSTSTS (SC_PINCTL[18]) to ‘1’. The warm reset sequence can be controlled in two ways.
Page 479: Figure 5.17-5 Sc Warm Reset Sequence
NUC970 Technical Reference Manual INT_ INIT SC_ RST Undefined SC_ DATA INIT_SEL (SC_ ALTCTL [9:8]) Time Comment SC_RST to SC_DATA Reception Mode SC_DATA Reception Mode to SC_RST Assert Unit : SC Clock 42106 SC_CLK Start to ATR Appear Note : This value is measured by chip IO pin and the real value will depend on system design Figure 5.17-5 SC Warm Reset Sequence Deactivation...
Page 480: Figure 5.17-6 Sc Deactivation Sequence
NUC970 Technical Reference Manual When hardware de-asserts SC_PWR to low, the controller will generate an interrupt to CPU at the same time (if INITIEN (SC_IER[8]) = 1). INT_INIT SC_PWR SC_CLK SC_RST SC_DATA Undefined INITSEL (SC_ALTCTL[9:8]) Time Comment Deactivation Trigger to SC_RST Low SMC_RST Low to Stop SC_CLK Stop SC_CLK to Stop SC_PWR Unit: SC Clock...
Page 481: Figure 5.17-7 Basic Operation Flow
NUC970 Technical Reference Manual Start Init system clock Configure SC function pin Card inertion? Insert smart card Activation sequence Receive ATR? Check parameter ok? Warm reset In specific mode? Negotiabled transmission protocol Application Deactivation sequence Card removal Figure 5.17-7 Basic Operation Flow 5.17.5.2 Initial Character TS According to 7816-3, the initial character TS has two possible patterns shown in the following...
Page 482: Figure 5.17-8 Initial Character Ts
NUC970 Technical Reference Manual change the CONSEL (SC_CTL[5:4]) register automatically. If the first data is neither 0x3B nor 0x3F, the hardware will generate an interrupt (if ACERRIEN (SC_INTEN[10]) = ‘1’) to CPU. Start Character T0 Direct Convention Start t = 12 ~ 9600 ETU Start Character T0 Start...
Page 483 NUC970 Technical Reference Manual Enable counter by setting TMRSEL (SC_CTL[14:13]). Select operation mode OPMODE (SC_TMRCTLx[27:24]) and give a count value CNT (SC_TMRCTLx[23:0]) by setting SC_TMRCTLx register. Set CNTEN0 (SC_ALTCTL[5]), CNTEN1 (SC_ALTCTL[6]) or CNTEN2 (SC_ALTCTL[7]) is to start counting. The SC_TMRCTL0, SC_TMRCTL1 and SC_TMRCTL2 timer operation mode are listed in below table.
Page 484 NUC970 Technical Reference Manual Same as 0001, but when the down counter equals to 0, hardware will set TMRxIF (SC_INTSTS[5:3]) and counter will re-load the CNT (SC_TMRCTL0[23:0], SC_TMRCTL1[7:0], SC_TMRCTL2[7:0]) value. When the next START bit is detected, counter will re-count until software clears CNTENx (SC_ALTCTL[7:5]). 0101 When ACTSTSx...
Page 485 NUC970 Technical Reference Manual 4. Select the UART baud rate by setting ETURDIV (SC_ETUCR[11:0]) fields. For example, if smartcard module clock is 12 MHZ and target baud rate is 115200bps, ETURDIV should fill with (12000000 / 115200 - 1). 5. Select the data format include data length (by setting WLS (SC_UARTCTL[5:4]), parity format (by setting OPE (SC_UARTCTL[7]) and PBOFF (SC_UARTCTL[6])) and stop bit length (by setting NSB (SC_CTL[15]) or EGT (SC_EGT[7:0])).
Page 486: Register Map
NUC970 Technical Reference Manual 5.17.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SC Base Address: SC0_BA = 0xB800_5000 SC1_BA = 0xB800_5400 SC_DAT SCx_BA+0x000 SC Receiving/Transmit Holding Buffer Register 0xXXXX_XXXX x = 0,1 SC_CTL SCx_BA+0x004...
Page 487 NUC970 Technical Reference Manual Publication Release Date: Dec. 15, 2015 - 487 - Revision V1.30...
Page 488: Register Description
NUC970 Technical Reference Manual 5.17.7 Register Description SC Receiving/Transmit Holding Buffer Register (SC_DAT) Register Offset R/W Description Reset Value SC_DAT SCx_BA+0x000 R/W SC Receiving/Transmit Holding Buffer Register 0xXXXX_XXXX x=0,1 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Receiving/ Transmit Holding Buffer Write Operation: By writing data to DAT, the SC will send out an 8-bit data.
Page 489 NUC970 Technical Reference Manual SC Control Register (SC_CTL) Register Offset Description Reset Value SC_CTL SCx_BA+0x004 SC Control Register 0x0000_0000 x=0,1 Reserved SYNC Reserved CDLV CDDBSEL TXRTYEN TXRTY RXRTYEN RXRTY TMRSEL RXTRGLV CONSEL AUTOCEN TXOFF RXOFF SCEN Bits Description [31] Reserved Reserved.
Page 490 NUC970 Technical Reference Manual 0 = TX error retry function Disabled. 1 = TX error retry function Enabled. TX Error Retry Count Number This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. [22:20] TXRTY Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
Page 491 NUC970 Technical Reference Manual Rx Buffer Trigger Level When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if SC_INTEN[RDAIEN] is enabled, an interrupt will be generated). 00 = INTR_RDA Trigger Level with 01 Bytes. [7:6] RXTRGLV 01 = INTR_RDA Trigger Level with 02 Bytes.
Page 492 NUC970 Technical Reference Manual SC Alternate Control Register (SC_ALTCTL) Register Offset Description Reset Value SC_ALTCTL SCx_BA+0x008 SC Alternate Control Register 0x0000_0000 x=0,1 Reserved Reserved OUTSEL ACTSTS2 ACTSTS1 ACTSTS0 RXBGTEN ADACEN Reserved INITSEL CNTEN2 CNTEN1 CNTEN0 WARSTEN ACTEN DACTEN RXRST TXRST Bits Description [31:17]...
Page 493 NUC970 Technical Reference Manual Auto Deactivation When Card Removal 0 = Auto deactivation Disabled when hardware detected the card removal. 1 = Auto deactivation Enabled when hardware detected the card removal. [11] ADACEN Note: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set).
Page 494 NUC970 Technical Reference Manual Internal Timer0 Start Enable Bit This bit enables Timer 0 to start counting. Software can fill in 0 to stop it and set 1 to reload and count. 0 = Stops counting. 1 = Starts counting. CNTEN0 Note1: This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 01.
Page 495 NUC970 Technical Reference Manual TX Software Reset When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. TXRST 0 = No effect. 1 = Reset the TX internal state machine and pointers. Note: This bit will be auto cleared after reset is complete.
Page 496 NUC970 Technical Reference Manual SC Extend Guard Time Register (SC_EGT) Register Offset Description Reset Value SC_EGT SCx_BA+0x00C SC Extend Guard Time Register 0x0000_0000 x=0,1 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Extended Guard Time [7:0] This field indicates the extended guard timer value. Note: The counter is ETU base and the real extended guard time is EGT.
Page 497 NUC970 Technical Reference Manual SC Receiver Buffer Time-out Register (SC_RXTOUT) Register Offset Description Reset Value SC_RXTOUT SCx_BA+0x010 SC Receive Buffer Time-out Register 0x0000_0000 x=0,1 Reserved Reserved Reserved RFTM RFTM Bits Description [31:9] Reserved Reserved. SC Receiver FIFO Time-out (ETU Base) The time-out counter resets and starts counting whenever the RX buffer received a new data word.
Page 498 NUC970 Technical Reference Manual SC Clock Divider Control Register (SC_ETUCTL) Register Offset Description Reset Value SC_ETUCTL SCx_BA+0x014 SC ETU Control Register 0x0000_0173 x=0,1 Reserved Reserved CMPEN Reserved ETURDIV ETURDIV Bits Description [31:16] Reserved Reserved. Compensation Mode Enable Bit This bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written [15] CMPEN...
Page 499 NUC970 Technical Reference Manual SC Interrupt Control Register (SC_INTEN) Register Offset Description Reset Value SC_INTEN SCx_BA+0x018 SC Interrupt Enable Control Register 0x0000_0000 x=0,1 Reserved Reserved Reserved ACERRIEN RXTOIEN INITIEN CDIEN BGTIEN TMR2IEN TMR1IEN TMR0IEN TERRIEN TBEIEN RDAIEN Bits Description [31:11] Reserved Reserved.
Page 500 NUC970 Technical Reference Manual This field is used for TMR2 interrupt enable. 0 = Timer2 interrupt Disabled. 1 = Timer2 interrupt Enabled. Timer1 Interrupt Enable Bit This field is used to enable the TMR1 interrupt. TMR1IEN 0 = Timer1 interrupt Disabled. 1 = Timer1 interrupt Enabled.
Page 501 NUC970 Technical Reference Manual SC Interrupt Status Register (SC_INTSTS) Register Offset Description Reset Value SC_INTSTS SCx_BA+0x01C SC Interrupt Status Register 0x0000_0002 x=0,1 Reserved Reserved Reserved ACERRIF RBTOIF INITIF CDIF BGTIF TMR2IF TMR1IF TMR0IF TERRIF TBEIF RDAIF Bits Description [31:11] Reserved Reserved.
Page 502 NUC970 Technical Reference Manual This field is used for TMR2 interrupt status flag. Note: This bit is read only, but it can be cleared by writing 1 to it. Timer1 Interrupt Status Flag (Read Only) TMR1IF This field is used for TMR1 interrupt status flag. Note: This bit is read only, but it can be cleared by writing 1 to it.
Page 503 NUC970 Technical Reference Manual SC Transfer Status Register (SC_STATUS) Register Offset Description Reset Value SC_STATUS SCx_BA+0x020 SC Status Register 0x0000_0202 x=0,1 TXACT TXOVERR TXRERR Reserved TXPOINT RXACT RXOVERR RXRERR Reserved RXPOINT Reserved CDPINSTS CINSERT CREMOVE TXFULL TXEMPTY TXOV Reserved Reserved RXFULL RXEMPTY RXOV...
Page 504 NUC970 Technical Reference Manual Receiver Retry Error (Read Only) This bit is set by hardware when RX has any error and retries transfer. Note1: This bit is read only, but it can be cleared by writing 1 to it. [21] RXRERR Note2 This bit is a flag and cannot generate any interrupt to CPU.
Page 505 NUC970 Technical Reference Manual Note2: If CPU sets receiver retries function by setting RXRTYEN (SC_CTL[19]) , hardware will not set this flag. Receiver Frame Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid “stop bit” (that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
Page 506 NUC970 Technical Reference Manual SC PIN Control State Register (SC_PINCTL) Register Offset Description Reset Value SC_PINCTL SCx_BA+0x024 SC Pin Control State Register 0x0000_00x0 x=0,1 Reserved SYNC Reserved Reserved RSTSTS PWRSTS DATSTS Reserved SCDOSTS PWRINV Reserved SCDOUT Reserved Reserved CLKKEEP Reserved SCRST PWREN Bits...
Page 507 NUC970 Technical Reference Manual 1 = The SC_DAT pin is high. [15:13] Reserved Reserved. SC Data Pin Output Status This bit is the pin status of SCDATAOUT. [12] SCDOSTS 0 = SCDATAOUT pin to low. 1 = SCDATAOUT pin to high. SC_PWR Pin Inverse This bit is used for inverse the SC_PWR pin.
Page 508 NUC970 Technical Reference Manual Write this field to drive SC_PWR pin. Refer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level. Read this field to get SC_PWR pin status. 0 = SC_PWR pin status is low. 1 = SC_PWR pin status is high. Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
Page 509 NUC970 Technical Reference Manual SC Timer Control Register 0 (SC_TMRCTL0) Register Offset Description Reset Value SC_TMRCTL0 SCx_BA+0x028 SC Internal Timer Control Register 0 0x0000_0000 x=0,1 Reserved OPMODE Bits Description [31:28] Reserved Reserved. Timer 0 Operation Mode Selection [27:24] OPMODE This field indicates the internal 24-bit timer operation selection. Refer to Error! Reference source not found.
Page 510 NUC970 Technical Reference Manual SC Timer Control Register 1 (SC_TMRCTL1) Register Offset Description Reset Value SC_TMRCTL1 SCx_BA+0x02C SC Internal Timer Control Register 1 0x0000_0000 x=0,1 Reserved OPMODE Reserved Reserved Bits Description [31:28] Reserved Reserved. Timer 1 Operation Mode Selection [27:24] OPMODE This field indicates the internal 8-bit timer operation selection.
Page 511 NUC970 Technical Reference Manual SC Timer Control Register 2 (SC_TMRCTL2) Register Offset Description Reset Value SC_TMRCTL2 SCx_BA+0x030 SC Internal Timer Control Register 2 0x0000_0000 x=0,1 Reserved OPMODE Reserved Reserved Bits Description [31:28] Reserved Reserved. Timer 2 Operation Mode Selection [27:24] OPMODE This field indicates the internal 8-bit timer operation selection.
Page 512 NUC970 Technical Reference Manual SC UART Mode Control Register (SC_UARTCTL) Register Offset Description Reset Value SC_UARTCTL SCx_BA+0x034 SC UART Mode Control Register 0x0000_0000 x=0,1 Reserved Reserved Reserved PBOFF Reserved UARTEN Bits Description [31:8] Reserved Reserved. Odd Parity Enable Bit 0 = Even number of logic 1’s are transmitted or check the data word and parity bits in receiving mode.
Page 513 NUC970 Technical Reference Manual Bits Description = 0. Note3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine. Publication Release Date: Dec. 15, 2015 - 513 - Revision V1.30...
Page 514 NUC970 Technical Reference Manual SC Timer Current Data Register 0 (SC_TMRDAT0) Register Offset Description Reset Value SC_TMRDAT0 SCx_BA+0x038 SC Timer Current Data Register 0 0x0000_07FF x=0,1 Reserved CNT0 CNT0 CNT0 Bits Description [31:24] Reserved Reserved. Timer0 Current Data Value (Read Only) CNT0 [23:0] This field indicates the current count values of timer0.
Page 515 NUC970 Technical Reference Manual SC Timer Current Data Register 1 (SC_TMRDAT1) Register Offset Description Reset Value SC_TMRDAT1 SCx_BA+0x03C R SC Timer Current Data Register 1 0x0000_7F7F x=0,1 Reserved Reserved CNT2 CNT1 Bits Description [31:16] Reserved Reserved. Timer2 Current Data Value (Read Only) CNT2 [15:8] This field indicates the current count values of timer2.
Page 516: I 2 C Synchronous Serial Interface Controller (I 2 C)
NUC970 Technical Reference Manual 5.18 C Synchronous Serial Interface Controller (I 5.18.1 Overview C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.
Page 517: Block Diagram
NUC970 Technical Reference Manual 5.18.3 Block Diagram The block diagram of I C Serial Interface controller is shown as following. pclk Clock Prescale preset_n paddr pwrite i2c_int_o psel Decoder Registers penable pwdata scl_pad_i pben sda_pad_i prdata Core Logic scl_pad_o/scl_padoen_o sda_pad_o/sda_padoen_o Figure 5.18-1 I C Block Diagram NOTE1: scl_pad_o and sda_pad_o are always tied to 1’b0.
Page 518: Functional Description
NUC970 Technical Reference Manual To enable I C’s clock, please refer to register CLK_PCLKEN1. Set I2C0 (CLK_PCLKEN1[0]) high to enable I C 0 clock while set I2C1 (CLK_PCLKEN1[1]) high to enable I C 1 clock. 5.18.5 Functional Description On I C bus, data is transferred between a Master and a Slave.
Page 519 NUC970 Technical Reference Manual SLAVE ADDRESS DATA DATA data transfer (n bytes + acknowledge) '0'(write) from master to slave A = acknowledge (SDA low) A = not acknowledge (SDA high) S = START condition from slave to master P = STOP condition A master-transmitter addressing a slave receiver with a 7-bit address.
Page 520: Figure 5.18-4 Start And Stop Conditions
NUC970 Technical Reference Manual START condition STOP condition Figure 5.18-4 START and STOP conditions 5.18.5.4 Slave Address Transfer The first byte of data transferred by the master immediately after the START signal is the slave address (SLA). This is a 7-bits calling address followed by a Read/Write (R/W) bit. The R/W bit signals of the slave indicate the data transfer direction.
Page 521: Figure 5.18-5 Bit Transfer On The I 2 C-Bus
NUC970 Technical Reference Manual data line change stable; of data data valid allowed Figure 5.18-5 Bit transfer on the I C-bus Clock pulse for acknowledgement SCL FROM MASTER DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge START condition Figure 5.18-6 Acknowledge on the I C-bus...
Page 522: Figure 5.18-8 Master Reads Data From Slave
NUC970 Technical Reference Manual The following figure shows a master read data from slave. A master addresses a slave with a 7- bit address and 1-bit read index to denote that the master wants to read data from the slave. The slave will start transmitting data after the slave returns acknowledge to the master.
Page 523: Figure 5.18-9 Write 1 Byte Of Data To A Slave
NUC970 Technical Reference Manual –– Wait for interrupt or I2C_TIP flag to negate –– Read I2C_RxACK bit from CSR Register, it should be ‘0’. Set Tx_NUM = 0x0. Set STOP bit. –– Wait for interrupt or I2C_TIP flag to negate –– First command sequence Second command sequence Figure 5.18-9 Write 1 byte of data to a slave...
Page 524: Figure 5.18-10 Read A Byte Of Data
NUC970 Technical Reference Manual Read I2C_RxACK bit from CSR Register, it should be ‘0’. Write 0x20 to TxR[7:0], set WRITE bit. –– Wait for interrupt or I2C_TIP flag to negate –– Read I2C_RxACK bit from CSR Register, it should be ‘0’. Write 0x9D (address + read bit) to TxR[7:0], set START bit, set WRITE bit.
Page 525 NUC970 Technical Reference Manual sda_pad_i. Software can read/write this register at any time, but the output enable – scl_padoen_o and sda_padoen_o are controlled by software only when I2C_EN = 0. Publication Release Date: Dec. 15, 2015 - 525 - Revision V1.30...
Page 526: Register Map
NUC970 Technical Reference Manual 5.18.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value C Base Address: I2C0_BA = 0xB800_6000 I2C1_BA = 0xB800_6100 I2Cn_CSR I2Cn_BA+0x000 I2C n Control and Status Register 0x0000_0000 n=0,1 I2Cn_DIVIDER...
Page 527: Register Description
NUC970 Technical Reference Manual 5.18.7 Register Description Publication Release Date: Dec. 15, 2015 - 527 - Revision V1.30...
Page 528 NUC970 Technical Reference Manual I2C n Control and Status Register (I2Cn_CSR) Register Offset Description Reset Value I2Cn_CSR I2Cn_BA+0x000 I2C n Control and Status Register 0x0000_0000 n=0,1 Reserved Reserved Reserved I2C_RxACK I2C_BUSY I2C_AL I2C_TIP Reserved Tx_NUM Reserved I2C_EN Bits Description [31:12] Reserved Reserved.
Page 529 NUC970 Technical Reference Manual Reserved Reserved. Interrupt Flag The Interrupt Flag is set when: Transfer has been completed. Transfer has not been completed, but slave responded NACK (in multi-byte transmit mode). Arbitration is lost. NOTE: This bit is read only, but can be cleared by writing 1 to this bit. Interrupt Enable 0 = Disable I C Interrupt.
Page 530 NUC970 Technical Reference Manual I2C n Prescale Register (I2Cn_DIVIDER) Register Offset Description Reset Value I2Cn_DIVIDER I2Cn_BA+0x004 I2C n Clock Prescale Register 0x0000_0000 n=0,1 Reserved Reserved DIVIDER[15:8] DIVIDER[7:0] Bits Description Clock Prescale Register It is used to prescale the SCL clock line. Due to the structure of the I C interface, the core uses a 5*SCL clock internally.
Page 531 NUC970 Technical Reference Manual I2C n Command Register (I2Cn_CMDR) Register Offset Description Reset Value I2Cn_CMDR I2Cn_BA+0x008 I2C n Command Register 0x0000_0000 n=0,1 Reserved Reserved Reserved Reserved START STOP READ WRITE NOTE: Software can write this register only when I2C_EN = 1. Bits Description [31:5]...
Page 532 NUC970 Technical Reference Manual I2C n Software Mode Register (I2Cn_SWR) Register Offset Description Reset Value I2Cn_SWR I2Cn_BA+0x00C I2C n Software Mode Control Register 0x0000_003F n=0,1 Reserved Reserved Reserved Reserved Reserved Bits Description [31:5] Reserved Reserved. Serial Interface SDA Status (Read Only) 0 = SDA is Low.
Page 533 NUC970 Technical Reference Manual I2C n Data Receive Register (I2Cn_RXR) Register Offset Description Reset Value I2Cn_RXR I2Cn_BA+0x010 I2C n Data Receive Register 0x0000_0000 n=0,1 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Data Receive Register [7:0] The last byte received via I C bus will put on this register.
Page 534 NUC970 Technical Reference Manual I2C n Data Transmit Register (I2Cn_TXR) Register Offset Description Reset Value I2Cn_TXR I2Cn_BA+0x014 I2C n Data Transmit Register 0x0000_0000 n=0,1 Bits Description Data Transmit Register [31:0] 32-bit transmit buffer. Refer to Section of “Data transfer on the I C bus”...
Page 535: Spi Interface Controller (Spi)
NUC970 Technical Reference Manual 5.19 SPI Interface Controller (SPI) 5.19.1 Overview The SPI is a synchronous serial interface performs a serial-to-parallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion on data characters received from CPU. This interface can drive up to 2 external peripherals and is seen as the master. 5.19.2 Features ...
Page 536: Block Diagram
NUC970 Technical Reference Manual 5.19.3 Block Diagram mw_sclk_o pclk Clock Generator preset_n paddr SPI Core Logic pwrite psel Decoder mw_int_o Registers penable mw_ss_o[1:0] pwdata pben Tx/Rx prdata mw_so_o Buffer mw_si_i Figure 5.19-1 SPI Block Diagram Pin descriptions: mw_sclk_o: SPI serial clock output pin. mw_int_o: SPI interrupt signal output.
Page 537: Function Description
NUC970 Technical Reference Manual Write 0xB to MFP_GPI5 (SYS_GPI_MFPL[23:20]), MFP_GPI6 (SYS_GPI_MFPL[27:24]), MFP_GPI7 (SYS_GPI_MFPL[31:28]) and MFP_GPI8 (SYS_GPI_MFPH[3:0]) configures pin PI.5, PI.6, PI.7 and PI.8 to be SPI1_SS0, SPI1_CLK, SPI1_DATA0 and SPI1_DATA1 resepctively. Please note that configure different pins to be same functionality is prohibited. For example, please don’t configure PB.14 and PI.6 to be SPI1_DATA0 functionality in the same time.
Page 538: Figure 5.19-2 Normal Spi Timing
NUC970 Technical Reference Manual These four bits provide the configuration of suspend interval between two successive transmit/receive in a transfer. The default value is 0x0. When CNTRL[Tx_NUM] = 00, setting this field has no effect on transfer. The desired interval is obtained according to the following equation (from the last falling edge of current sclk to the first rising edge of next sclk).
Page 539: Figure 5.19-3 Alternate Phase Sclk Clock Timing
NUC970 Technical Reference Manual mw_ss_o mw_sclk_o mw_so_o Tx[1] Tx[2] Tx[3] Tx[4] Tx[5] Tx[6] (Tx[0]) (Tx[7]) mw_si_i Rx[1] Rx[2] Rx[3] Rx[4] Rx[5] Rx[6] (Rx[0]) (Rx[7]) CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08, CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1, SSR[SS_LVL]=0 Figure 5.19-3 Alternate Phase SCLK Clock Timing 5.19.5.3 Dual and Quad IO Mode This SPI controller also supports dual and quad IO transfer for SPI Flash when set the DUALM or QUAD bit (CNTRL[21:20]) to 1.
Page 540: Figure 5.19-5 Dual-Io Input Sequence
NUC970 Technical Reference Manual SCLK mw_si_i[0] (Input) mw_si_i[1] (Input) DUALM DIR_2QM Figure 5.19-5 Dual-IO Input Sequence Publication Release Date: Dec. 15, 2015 - 540 - Revision V1.30...
Page 541 NUC970 Technical Reference Manual 5.19.5.4 SPI Programming Example If a device with following specifications: Data bit latches on positive edge of serial clock Data bit drives on negative edge of serial clock Data is transferred with the MSB first Only one byte transmits/receives in a transfer Chip select signal is active low Do following actions basically (Should refer to the specification of device for the detailed steps): Write a divisor into DIVIDER to determine the frequency of serial clock.
Page 542: Registers Map
NUC970 Technical Reference Manual 5.19.6 Registers Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SPI Base Address: SPI0_BA = 0xB800_6200 SPI1_BA = 0xB800_6300 SPIn_CNTRL SPIn_BA+0x000 SPI n Control and Status Register 0x0000_0004 n=0,1 SPIn_DIVIDER...
Page 543: Register Description
NUC970 Technical Reference Manual 5.19.7 Register Description Publication Release Date: Dec. 15, 2015 - 543 - Revision V1.30...
Page 544 NUC970 Technical Reference Manual SPI n Control and Status Register (SPIn_CNTRL) Register Offset Description Reset Value SPIn_CNTRL SPIn_BA+0x000 SPI n Control and Status Register 0x0000_0004 n=0,1 CLK_POL Reserved Reserved DUALM QUADM DIR_2QM Reserved SLEEP Reserved Tx_NUM Tx_BIT_LEN Tx_NEG Rx_NEG GO_BUSY Bits Description Clock Polarity...
Page 545 NUC970 Technical Reference Manual 0100 = SPI transfer suspended 6 SCLK clock cycle. 0101 = SPI transfer suspended 7 SCLK clock cycle. 0110 = SPI transfer suspended 8 SCLK clock cycle. 0111 = SPI transfer suspended 9 SCLK clock cycle. 1000 = SPI transfer suspended 10 SCLK clock cycle.
Page 546 NUC970 Technical Reference Manual SPI n Divider Register (SPIn_DIVIDER) Register Offset Description Reset Value SPIn_DIVIDER SPIn_BA+0x004 SPI n Clock Divider Register 0x0000_0000 n=0,1 Reserved Reserved DIVIDER DIVIDER Bits Description Clock Divider Register [15:0] DIVIDER The divider value of serial clock. NOTE: Suggest DIVIDER should be at least 1.
Page 547 NUC970 Technical Reference Manual SPI n Slave Select Register (SPIn_SSR) Register Offset Description Reset Value SPIn_SSR SPIn_BA+0x008 SPI n Slave Select Register 0x0000_0000 n=0,1 Reserved Reserved Reserved Reserved AUTOSS SS_LVL Bits Description Automatic Slave Select Function Enable Control AUTOSS 0 = Automatic slave select function Disabled. 1 = Automatic slave select function Enabled.
Page 548 NUC970 Technical Reference Manual SPI n Data Receive Register (SPIn_RX) Register Offset Description Reset Value SPIn_RX0 SPIn_BA+0x010 SPI n Data Receive Register 0 0x0000_0000 n=0,1 SPIn_RX1 SPIn_BA+0x014 SPI n Data Receive Register 1 0x0000_0000 n=0,1 SPIn_RX2 SPIn_BA+0x018 SPI n Data Receive Register 2 0x0000_0000 n=0,1 SPIn_RX3...
Page 549 NUC970 Technical Reference Manual SPI n Data Transmit Register (SPIn_TX) Register Offset Description Reset Value SPIn_TX0 SPIn_BA+0x010 SPI n Data Transmit Register 0 0x0000_0000 n=0,1 SPIn_TX1 SPIn_BA+0x014 SPI n Data Transmit Register 1 0x0000_0000 n=0,1 SPIn_TX2 SPIn_BA+0x018 SPI n Data Transmit Register 2 0x0000_0000 n=0,1 SPIn_TX3...
Page 550: I 2 S Controller (I 2 S)
NUC970 Technical Reference Manual 5.20 S Controller (I 5.20.1 Overview The I S controller consists of I S and PCM protocols to interface with external audio CODEC. The I and PCM interface supports 8, 16, 18, 20 and 24-bit left/right precision in record and playback. When operating in 18/20/24-bit precision, each left/right-channel sample is stored in a 32-bit word.
Page 551: Block Diagram
NUC970 Technical Reference Manual 5.20.3 Block Diagram Control Register Play I2S_BCLK FIFO I2S_LRCK PFIFO Control I2S_DO Interface Unit I2S_DI I2S_MCLK RFIFO Control Record FIFO Figure 5.20-1 I S Controller Block Diagram 5.20.4 Basic Configuration S functionality, it’s necessary to configure I/O pins as the I Before using I S function and enable I S’s...
Page 552: Functional Description
NUC970 Technical Reference Manual 5.20.5 Functional Description 5.20.5.1 S interface The I S interface signals are shown as the following figure. I2S_BCLK I2S_LRCK Audio I2S_DO Controller Codec (Master) (Slave) I2S_DI I2S_MCLK Figure 5.20-2 I S Interface Signal of Master Mode I2S_BCLK I2S_LRCK Audio...
Page 553: Figure 5.20-4 I 2 S Msb-Justified Format
NUC970 Technical Reference Manual BCLK DI / DO word N-1 word N word N+1 right channel left channel right channel I2S Bus BCLK DI / DO word N-1 word N+1 word N right channel right channel lef channel MSB –Justified format Figure 5.20-4 I S MSB-Justified Format The sampling rate, bit shift clock frequency could be set by the control register I2S_CON.
Page 554: Figure 5.20-6 Pcm Mode Interface Waveform
NUC970 Technical Reference Manual BCLK DI / DO SLOT position SLOT1 SLOT2 FS_PERIOD -1 SLOT1_x_START SLOT2_x_START SLOT1_O_START (ACTL_PCMS1ST[25:16]) = 1, SLOT2_O_START (ACTL_PCMS2ST[25:16]) = 16, BCLKP (ACTL_PCMCON[0]) = 0 Figure 5.20-6 PCM Mode Interface Waveform Publication Release Date: Dec. 15, 2015 - 554 - Revision V1.30...
Page 555: Register Map
NUC970 Technical Reference Manual 5.20.6 Register Map R: read only, W: write only, R/W: both read and write, C: Only value 1 can be written Register Offset Description Reset Value S Base Address: I2S_BA = 0xB000_9000 I2S_GLBCON I2S_BA+0x000 I2S Global Control Register 0x0000_0000 I2S_RESET I2S_BA+0x004...
Page 556: Register Description
NUC970 Technical Reference Manual 5.20.7 Register Description Publication Release Date: Dec. 15, 2015 - 556 - Revision V1.30...
Page 557 NUC970 Technical Reference Manual I2S Global Control Register (I2S_GLBCON) Register Offset Description Reset Value I2S_GLBCON I2S_BA+0x000 I2S Global Control Register 0x0000_0000 Reserved R_DMA_IRQ P_DMA_IRQ R_FIFO_FULL_IRQ_ R_FIFO_EMPTY_I P_FIFO_FULL_IR P_FIFO_EMPTY_I Reserved RQ_EN Q_EN RQ_EN R_DMA_IRQ_ P_DMA_IRQ_SEL R_DMA_IRQ P_DMA_IRQ BITS_SELECT IRQ_DMA_ IRQ_DMA_DATA_ZE FIFO_TH Reserved Reserved BLOCK_EN...
Page 558 NUC970 Technical Reference Manual Playback FIFO Empty Interrupt Request Enable Bit 0: not allowed to generation P_FIFO_EMPTY_IRQ [16] P_FIFO_EMPTY_IRQ_EN 1: allowed to generation P_FIFO_EMPTY_IRQ The P_FIFO_EMPTY_IRQ_EN bit is read/write Record DMA Interrupt Request Selection Bits 00: When record DMA address reach DMA record destination end address, the R_DMA_RIA_IRQ will be issued.
Page 559 NUC970 Technical Reference Manual IRQ_DMA Counter Function Enable Bit 0: not allowed to set P_DMA_IRQ (I2S_CON[10]) if I2S_PSR[4] is set to 1. IRQ_DMA_CNTER_EN 1: allowed to set P_DMA_IRQ (I2S_CON[10]) if (I2S_PSR[4]) is set to 1. The IRQ_DMA_CNTER_EN bit is read/write IRQ_DMA_DATA Zero and Sign Detect Enable Bit 0: not allowed to set P_DMA_IRQ (I2S_CON[10]) if I2S_PSR[3] is set to 1.
Page 560 NUC970 Technical Reference Manual I2S Sub Block Reset Control Register (I2S_RESET) Register Offset Description Reset Value I2S_RESET I2S_BA+0x004 I2S Sub Block Reset Control Register 0x0000_0000 Reserved Reserved SPLIT_DATA Reserved RESET RECORD_SINGLE PLAY_SINGLE Reserved DMA_CNTER Reserved RECORD PLAY DMA_DATA_ZERO_EN Reserved BLOCK_RESET Bits Description [31:17]...
Page 561 NUC970 Technical Reference Manual address at I2S_RDESB2 / I2S_PDESB2 R,R,R,R R,R,R,R R,R,R,R R,R,R,R If SPLIT=1, 16bit-data, L=16bit left/slot0 data, R=16bit right/slot1 data, address at I2S_RDESB / I2S_PDESB. address at I2S_RDESB2 / I2S_PDESB2 If SPLIT=1, 24bit-data, L=24bit left/slot0 data, R=24bit right/slot1 data, address at I2S_RDESB / I2S_PDESB.
Page 562 NUC970 Technical Reference Manual The PLAY_SINGLE[1:0] bits are read/write [11:7] Reserved Reserved. S/PCM Record Control Bit 0: The record path of I S/PCM is disabled. RECORD 1: The record path of I S/PCM is enabled. The RECORD bit is read/write S/PCM Playback Control Bit 0: The playback path of I S/PCM is disabled.
Page 563 NUC970 Technical Reference Manual I2S Record DMA Destination Base Address Register (I2S_RDESB) Register Offset Description Reset Value I2S_RDESB I2S_BA+0x008 I2S Record DMA Destination Base Address Register 0x0000_0000 AUDIO_RDESB AUDIO_RDESB AUDIO_RDESB AUDIO_RDESB Bits Description 32-bit Record Destination Base Address [31:0] AUDIO_RDESB This bit field indicates the record destination base address of DMA.
Page 564 NUC970 Technical Reference Manual I2S Record DMA Destination Length Register (I2S_RDES_LENGTH) Register Offset Description Reset Value I2S_RDES_LENGTH I2S_BA+0x00C I2S Record DMA Destination Length Register 0x0000_0000 AUDIO_RDES_L AUDIO_RDES_L AUDIO_RDES_L AUDIO_RDES_L Bits Description 32-bit Record Destination Address Length AUDIO_RDES_L [31:0] The AUDIO_RDES_L [31:0] bits are read/write. The minimum value for 16-bits mode is 0x20 and for 24-bits mode is 0x40.
Page 565 NUC970 Technical Reference Manual I2S Record DMA Destination Current Address Register (I2S_RDESC) Register Offset Description Reset Value I2S_RDESC I2S_BA+0x010 I2S Record DMA Destination Current Address Register 0x0000_0000 AUDIO_RDESC AUDIO_RDESC AUDIO_RDESC AUDIO_RDESC Bits Description 32-bit Record Destination Current Address [31:0] AUDIO_RDESC This bit field indicates the current address of DMA record destination.
Page 566 NUC970 Technical Reference Manual I2S Play DMA Destination Base Address Register (I2S_PDESB) Register Offset Description Reset Value I2S_PDESB I2S_BA+0x014 I2S Play DMA Destination Base Address Register 0x0000_0000 AUDIO_PDESB AUDIO_PDESB AUDIO_PDESB AUDIO_PDESB Bits Description 32-bit Play Destination Base Address [31:0] AUDIO_PDESB This bit field indicates the play destination base address of DMA.
Page 567 NUC970 Technical Reference Manual I2S Play DMA Destination Length Register (I2S_PDES_LENGTH) Register Offset Description Reset Value I2S_PDES_LENGTH I2S_BA+0x018 I2S Play DMA Destination Length Register 0x0000_0000 AUDIO_PDES_L AUDIO_PDES_L AUDIO_PDES_L AUDIO_PDES_L Bits Description 32-bit Play Destination Address Length [31:0] AUDIO_PDES_L The AUDIO_PDES_L [31:0] bits are read/write. The minimum value for 16-bits mode is 0x20 and for 24-bits mode is 0x40.
Page 568 NUC970 Technical Reference Manual I2S Play DMA Destination Current Address Register (I2S_PDESC) Register Offset Description Reset Value I2S_PDESC I2S_BA+0x01C I2S Play DMA Destination Current Address Register 0x0000_0000 AUDIO_PDESC AUDIO_PDESC AUDIO_PDESC AUDIO_PDESC Bits Description 32-bit Play Destination Current Address [31:0] AUDIO_PDESC This bit field indicates the current address of DMA play destination.
Page 569 NUC970 Technical Reference Manual I2S Record Status Register (I2S_RSR) Register Offset Description Reset Value I2S_RSR I2S_BA+0x020 I2S Record Status Register 0x0000_0000 Reserved Reserved Reserved R_DMA_RIA_SN Reserved R_FIFO_FULL R_FIFO_EMPTY R_DMA_RIA_IRQ Bits Description [31:8] Reserved Reserved. Record DMA Reach Indicative Address Section Number Bit R_DMA_IRQ_SEL (I2S_CON[15:14]) = 01, R_DMA_RIA_SN[2:0]= 1, 0.
Page 570 NUC970 Technical Reference Manual I2S Play Status Register (I2S_PSR) Register Offset Description Reset Value I2S_PSR I2S_BA+0x024 I2S Play Status Register 0x0000_0000 Reserved Reserved Reserved P_DMA_RIA_SN DMA_CNTER_IRQ DMA_DATA_ZERO_IRQ P_FIFO_FULL P_FIFO_EMPTY P_DMA_RIA_IRQ Bits Description [31:8] Reserved Reserved. Play DMA Reach Indicative Address Section Number Bit P_DMA_IRQ_SEL (I2S_CON[13:12]) = 01, P_DMA_RIA_SN[2:0]= 1, 0.
Page 571 NUC970 Technical Reference Manual Playback FIFO Full Indicator Bit When playback FIFO is full and the playback data is written into playback FIFO, the P_FIFO_FULL bit is set to 1. This bit indicates the full error of playback FIFO is happened.
Page 572 NUC970 Technical Reference Manual I2S Control Register (I2S_CON) Register Offset Description Reset Value I2S_CON I2S_BA+0x028 I2S Control Register 0x0000_0000 Reserved Reserved SLAVE Reserved BCLK_DIV MCLK_SEL FORMAT Reserved Bits Description [31:21] Reserved Reserved. S Slave Mode Selection Bit 0 = I S Master mode.
Page 573 NUC970 Technical Reference Manual [15:8] Reserved Reserved. S Serial Data Clock Frequency Selection Bit This bit field is used to decide the relationship of frequency between PLL and I S serial data clock. The frequency of I S serial data clock follows the formula below: [7:5] BCLK_DIV (PLL)
Page 574 NUC970 Technical Reference Manual I2S Play DMA Down Counter Register (I2S_COUNTER) Register Offset Description Reset Value I2S_COUNTER I2S_BA+0x02C I2S Play DMA Down Counter Register 0xFFFF_FFFF COUNTER COUNTER COUNTER COUNTER Bits Description Play DMA Down Counter This bit field is used to count playback data number for software monitoring. When one playback data is transferred to codec, the DMA counter subtracts 1.
Page 575 NUC970 Technical Reference Manual I2S PCM Mode Control Register (I2S_PCMCON) Register Offset Description Reset Value I2S_PCMCON I2S_BA+0x030 I2S PCM Mode Control Register 0x0000_0000 PCM_MCLK_PRS Reserved FS_PERIOD FS_PERIOD PCM_PRS Reserved BCLKP Bits Description PCM MCLK Frequency PRE_SCALER Selection Bits (FPLL Is the Input PLL Frequency, MCLK Is the Output Main Clock) 0000: PCM_MCLK=FPLL/1.
Page 576 NUC970 Technical Reference Manual PCM_BCLK Frequency PRE_SCALER Selection Bits [15:8] PCM_PRS BCLK = PCM_MCLK / (2*(PCM_PRS+1)). Reserved [7:1] Reserved. BCLK Polarity 0: send data at rising edge, latch data at falling edge BCLKP 1: send data at falling edge, latch data at rising edge The BCLKP bit is read/write Publication Release Date: Dec.
Page 577 NUC970 Technical Reference Manual I2S PCM Mode Slot 1 Start Register (I2S_PCMS1ST) Register Offset Description Reset Value I2S_PCMS1ST I2S_BA+0x034 I2S PCM Mode Slot 1 Start Register 0x0000_0000 Reserved SLOT1_O_START SLOT1_O_START Reserved SLOT1_I_START SLOT1_I_START Bits Description [31:26] Reserved Reserved. Slot 1 Data Out Start Position This bit field is used to set the start position of slot1 output data.
Page 578 NUC970 Technical Reference Manual I2S PCM Mode Slot 2 Start Register (I2S_PCMS2ST) Register Offset Description Reset Value I2S_PCMS2ST I2S_BA+0x038 I2S PCM Mode Slot 2 Start Register 0x0000_0000 Reserved SLOT2_O_START SLOT2_O_START Reserved SLOT2_I_START SLOT2_I_START Bits Description [31:26] Reserved Reserved. Slot 2 Data Out Start Position SLOT2_O_START [25:16] This bit field is used to set the start position of slot2 output data.
Page 579 NUC970 Technical Reference Manual I2S Record DMA Destination Base Address 2 Register (I2S_RDESB2) Register Offset Description Reset Value I2S_RDESB2 I2S_BA+0x040 I2S Record DMA Destination Base Address 2 Register 0x0000_0000 AUDIO_RDESB2 AUDIO_RDESB2 AUDIO_RDESB2 AUDIO_RDESB2 Bits Description 32-bit Record Destination Base Address for Right Channel [31:0] AUDIO_RDESB2 This bit field indicates the record destination base address of DMA.
Page 580 NUC970 Technical Reference Manual I2S Play DMA Destination Base Address 2 Register (I2S_PDESB2) Register Offset Description Reset Value I2S_PDESB2 I2S_BA+0x044 I2S Play DMA Destination Base Address 2 Register 0x0000_0000 AUDIO_PDESB2 AUDIO_PDESB2 AUDIO_PDESB2 AUDIO_PDESB2 Bits Description 32-bit Play Destination Base Address for Right Channel [31:0] AUDIO_PDESB2 This bit field indicates the play destination base address of DMA.
Page 581: Ethernet Mac Controller (Emac)
NUC970 Technical Reference Manual 5.21 Ethernet MAC Controller (EMAC) 5.21.1 Overview This chip provides 2 Ethernet MAC Controller (EMAC) for Network application. The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM function for recognizing Ethernet MAC addresses; Transmit-FIFO, Receive-FIFO, TX/RX state machine controller, time stamping engine for IEEE 1588, Magic Packet parsing engine and status controller.
Page 582: Block Diagram
NUC970 Technical Reference Manual 5.21.3 Block Diagram AHB Bus AHB Bus Master Slave Arbiter IEEE 1588 RXDMA TXDMA Register PTP Engine State Machine State Machine Files RXFIFO TXFIFO RXFIFO TXFIFO Control Control Address Register Flow Control Magic Packet CSMA/CD MII Management Engine (RXMAC, TXMAC) State Machine...
Page 583: Functional Description
NUC970 Technical Reference Manual 5.21.5 Functional Description 5.21.5.1 Arbiter In the EMAC, there are two different bus requests, RXREQ and TXREQ respectively. Arbiter does the arbitration between the RXREQ and TXREQ, and then decides which one can request the AHB bus. The arbitration results are shown below: RXREQ TXREQ Granted...
Page 584: Figure 5.21-2 Ethernet Frame Format
NUC970 Technical Reference Manual function will pause the transmission process after the current transmitting frame has been transmitted out. To transmit a control frame out, software must program the destination MAC address of control frame into the register pair {EMACn_CAM13M, EMACn_CAM13L}, source MAC address into the register pair {EMACn_CAM14M, EMACn_CAM14L}, and configure length/type, op-code and operand of control frame into the register pair {EMACn_CAM15M, EMACn_CAM15L}, and then set the bit SDPZ (EMACn_MCMDR[16]).
Page 585: Figure 5.21-3 64-Bit Reference Timing Counter
NUC970 Technical Reference Manual collision filtering. 5.21.5.7 Time Stamping Engine for IEEE 1588 The EMAC supports a time stamping engine for IEEE Std. 1588. In this time stamping engine, a 64-bit counter implemented to generate the reference timing, the registers EMACn_TSSEC and ETSLSR.
Page 586: Dma Descriptors Data Structure
NUC970 Technical Reference Manual 48-bit MAC address defined by registers EMACn_CAM0M and EMACn_CAM0L. The MGP_WAKE (EMACn_MCMDR[6]) controls if the Magic packet parsing engine enabled. If MGP_WAKE (EMACn_MCMDR[6]) is high, EMAC will set bit MGPR (EMACn_MISTA[15]) high to indicate Magic packet received. At the same time, EMAC generates an event to wake system up from power-down mode.
Page 587 NUC970 Technical Reference Manual RXDES 0: RXDMA Descriptor Word 0 The RXDMA descriptor word 0 contains a descriptor ownership indicator, receive frame status, and receive frame byte count. The detail description of RXDES 0 is shown below. Owner Reserved RTSAS ALIE RXGD PTLE...
Page 588 NUC970 Technical Reference Manual Frame Reception Complete The RXGD indicates the frame reception has completed and stored in the data buffer pointed by RX descriptor. RXGD [20] 0 = The frame reception does not complete yet. 1 = The frame reception completed. Packet Too Long The PTLE indicates the frame stored in the data buffer pointed by RX descriptor is a long frame (frame length is greater than 1518 bytes).
Page 589 NUC970 Technical Reference Manual RXDES 1: RXDMA Descriptor Word 1 The RXDMA descriptor word 1 contains the received frame buffer starting address or time stamp least significant 32-bit value. The detail description of RXDES 1 is shown below. RXBSA/TSLSB RXBSA/TSLSB RXBSA/TSLSB RXBSA/TSLSB Bits...
Page 590 NUC970 Technical Reference Manual RXDES 2: RXDMA Descriptor Word 2 The RXDMA descriptor word 2 is reserved. Reserved Reserved Reserved Reserved Bits Description [31:0] Reserved Reserved. Publication Release Date: Dec. 15, 2015 - 590 - Revision V1.30...
Page 591 NUC970 Technical Reference Manual RXDES 3: RXDMA Descriptor Word 3 The RXDMA descriptor word 3 contains the next RXDMA descriptor starting address or time stamp most significant 32-bit value. The detail description of RXDES 3 is shown below. NRXDSA/TSMSB NRXDSA/TSMSB NRXDSA/TSMSB NRXDSA/TSMSB Bits...
Page 592: Figure 5.21-5 Txdma Descriptor Data Structure
NUC970 Technical Reference Manual 5.21.6.2 TXDMA Descriptor Data Structure The TXDMA descriptor consists of four 32-bit words. The data structure of TXDMA descriptor shown in figure below. TXDES 0 Reserved TXDES 1 Transmit Frame Buffer Starting Address / Time Stamp Least Significant 32-Bit TXDES 2 Transmit Frame Status Transmit Frame Byte Count...
Page 593 NUC970 Technical Reference Manual TXDES 0: TXDMA Descriptor Word 0 The TXDMA descriptor word 0 contains a descriptor ownership indicator. In addition, it also contains control bits for transmit frame padding, CRC append, interrupt enable and time stamping control. The detail description of TXDES 0 is shown below. Owner Reserved Reserved...
Page 594 NUC970 Technical Reference Manual CRC Append The CRCAPP control the CRC append during frame transmission. If CRCAPP is enabled, the 4-bytes CRC checksum will be appended to frame at the end of frame CRCAPP transmission. 0 = 4-bytes CRC appending Disabled. 1 = 4-bytes CRC appending Enabled.
Page 595 NUC970 Technical Reference Manual TXDES 1: TXDMA Descriptor Word 1 The TXDMA descriptor word 1 contains the transmit frame buffer starting address or time stamp least significant 32-bit value. The detail description of TXDES 1 is shown below. TXBSA/TSLSB TXBSA/TSLSB TXBSA/TSLSB TXBSA/TSLSB Bits...
Page 596 NUC970 Technical Reference Manual TXDES 2: TXDMA Descriptor Word 2 The TXDMA descriptor word 2 contains transmit frame status, and transmit frame byte count. The detail description of TXDES 2 is shown below. CCNT TTSAS TXHA TXABT EXDEF TXCP Reserved TXINTR Bits Description...
Page 597 NUC970 Technical Reference Manual Late Collision The LC indicates the collision found in the outside of 64 bytes collision window. This means after the 64 bytes of a frame has been transmitted out to the network, the collision still found. The late collision check will only be done while EMAC is operating on half- [23] duplex mode.
Page 598 NUC970 Technical Reference Manual TXDES 3: TXDMA Descriptor Word 3 The TXDMA descriptor word 3 contains the next TXDMA descriptor starting address or time stamp most significant 32-bit value. The detail description of TXDES 3 is shown below. NTXDSA/TSMSB NTXDSA/TSMSB NTXDSA/TSMSB NTXDSA/TSMSB Bits...
Page 599: Register Map
NUC970 Technical Reference Manual 5.21.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value EMAC Base Address: EMAC0_BA = 0xB000_2000 EMAC1_BA = 0xB000_3000 EMACn_CAMCMR EMACn_BA+0x000 R/W EMAC n CAM Command Register 0x0000_0000 n=0,1 EMACn_CAMEN...
Page 600 NUC970 Technical Reference Manual EMACn_CAM7M EMACn_BA+0x040 R/W EMAC n CAM 7 Most Significant Word Register 0x0000_0000 n=0,1 EMACn_CAM7L EMACn_BA+0x044 R/W EMAC n CAM 7 Least Significant Word Register 0x0000_0000 n=0,1 EMACn_CAM8M EMACn_BA+0x048 R/W EMAC n CAM 8 Most Significant Word Register 0x0000_0000 n=0,1 EMACn_CAM8L...
Page 601 NUC970 Technical Reference Manual EMACn_MCMDR EMACn_BA+0x090 R/W EMAC n MAC Command Register 0x0040_0000 n=0,1 EMACn_MIID EMACn_BA+0x094 R/W EMAC n MII Management Data Register 0x0000_0000 n=0,1 EMACn_MIIDA EMACn_BA+0x098 R/W EMAC n MII Management Control and Address Register 0x0090_0000 n=0,1 EMACn_FFTCR EMACn_BA+0x09C R/W EMAC n FIFO Threshold Control Register 0x0000_0101 n=0,1 EMACn_TSDR...
Page 602 NUC970 Technical Reference Manual EMACn_TSINC EMACn_BA+0x118 R/W EMAC n Time Stamp Increment Register 0x0000_0000 n=0,1 EMACn_TSADDEND EMACn_BA+0x11C R/W EMAC n Time Stamp Addend Register 0x0000_0000 n=0,1 EMACn_UPDSEC EMACn_BA+0x120 R/W EMAC n Time Stamp Update Second Register 0x0000_0000 n=0,1 EMACn_UPDSUBSEC EMACn_BA+0x124 R/W EMAC n Time Stamp Update Sub Second Register 0x0000_0000 n=0,1...
Page 603: Register Description
NUC970 Technical Reference Manual 5.21.8 Register Description Publication Release Date: Dec. 15, 2015 - 603 - Revision V1.30...
Page 604 NUC970 Technical Reference Manual EMAC n CAM Command Register (EMACn_CAMCMR) The EMAC supports CAM function for destination MAC address recognition. The EMACn_CAMCMR control the CAM comparison function, and unicast, multicast, and broadcast packet reception. Register Offset Description Reset Value EMACn_CAMCM EMACn_BA+0x00 EMAC n CAM Command Register 0x0000_0000...
Page 605 NUC970 Technical Reference Manual Accept Multicast Packet The AMP controls the multicast packet reception. If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address. 0 = EMAC receives packet depends on the CAM comparison result. 1 = EMAC receives all multicast packets.
Page 606: Table 5.21-2 Different Camcmr Setting And Type Of Received Packet
NUC970 Technical Reference Manual Table 5.21-2 Different CAMCMR Setting and Type of Received Packet Publication Release Date: Dec. 15, 2015 - 606 - Revision V1.30...
Page 607 NUC970 Technical Reference Manual EMAC n CAM Enable Register (EMACn_CAMEN) The EMACn_CAMEN controls the validation of each CAM entry. Each CAM entry must be enabled first before it participates in the destination MAC address recognition. Register Offset Description Reset Value EMACn_CAMEN EMACn_BA+0x00 EMAC n CAM Enable Register...
Page 608 NUC970 Technical Reference Manual EMAC n CAM x Most Significant Word Register (EMACn_CAMxM) The EMAC is equipped with 16 CAM entries. In these 16 CAM entries, 13 entries (entry 0~12) are to keep destination MAC address for packet recognition, and the other 3 entries (entry 13~15) are for PAUSE control frame transmission.
Page 609 NUC970 Technical Reference Manual CAMxM CAMxM CAMxM CAMxM Bits Description CAMx Most Significant Word The CAMxM keeps the bit 47~16 of MAC address. The x can be the 0~12. The register pair {EMACn_CAMxM, EMACn_CAMxL} represents a CAM entry and keeps a MAC [31:0] CAMxM address.
Page 610 NUC970 Technical Reference Manual EMAC n CAM x Least Significant Word Register (EMACn_CAMxL) The EMAC is equipped with 16 CAM entries. In these 16 CAM entries, 13 entries (entry 0~12) are to keep destination MAC address for packet recognition, and the other 3 entries (entry 13~15) are for PAUSE control frame transmission.
Page 611 NUC970 Technical Reference Manual CAMxL CAMxL Reserved Reserved Bits Description CAMx Least Significant Word The CAMxL keeps the bit 15~0 of MAC address. The x can be the 0~14. The register pair {EMACn_CAMxM, EMACn_CAMxL} represents a CAM entry and keeps a MAC [31:16] CAMxL address.
Page 612 NUC970 Technical Reference Manual EMAC n CAM 15 Most Significant Word Register (EMACn_CAM15M) The EMAC is equipped with 16 CAM entries. In these 16 CAM entries, 13 entries (entry 0~12) are to keep destination MAC address for packet recognition, and the other 3 entries (entry 13~15) are for PAUSE control frame transmission.
Page 613 NUC970 Technical Reference Manual EMAC n CAM 15 Least Significant Word Register (EMACn_CAM15L) The EMAC is equipped with 16 CAM entries. In these 16 CAM entries, 13 entries (entry 0~12) are to keep destination MAC address for packet recognition, and the other 3 entries (entry 13~15) are for PAUSE control frame transmission.
Page 614 NUC970 Technical Reference Manual EMAC n Transmit Descriptor Link List Start Address Register (EMACn_TXDLSA) The TX descriptor defined in EMAC is a link-list data structure. The EMACn_TXDLSA keeps the starting address of this link-list. In other words, the EMACn_TXDLSA keeps the starting address of the 1st TX descriptor.
Page 615 NUC970 Technical Reference Manual EMAC n Receive Descriptor Link List Start Address Register (EMACn_RXDLSA) The RX descriptor defined in EMAC is a link-list data structure. The EMACn_RXDLSA keeps the starting address of this link-list. In other words, the EMACn_RXDLSA keeps the starting address of the 1st RX descriptor.
Page 616 NUC970 Technical Reference Manual EMAC n MAC Command Register (EMACn_MCMDR) The EMACn_MCMDR provides the control information for EMAC. Some command settings affect both frame transmission and reception, such as bit FDUP (EMACn_MCMDR[18]), the full/half duplex mode selection, or bit OPMOD (EMACn_MCMDR[20]), the 100/10M bps mode selection. Some command settings control frame transmission and reception separately, likes bit TXON (EMACn_MCMDR[8]) and RXON (EMACn_MCMDR[0]).
Page 617 NUC970 Technical Reference Manual [19] Reserved Reserved. Full Duplex Mode Selection The FDUP controls that if EMAC is operating on full or half duplex mode. [18] FDUP 0 = EMAC operates in half duplex mode. 1 = EMAC operates in full duplex mode. SQE Checking Enable Control The SQECHKEN controls the enable of SQE checking.
Page 618 NUC970 Technical Reference Manual Magic Packet Wake-up Enable Control The MGP_WAKE high enables the functionality that Ethernet MAC controller checked if the incoming packet is Magic Packet and wakeup system from Power-down mode. If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MGP_WAKE MAC controller would generate a wakeup event to wake system up from Power-down mode.
Page 619 NUC970 Technical Reference Manual EMAC n MII Management Data Register (EMACn_MIID) The EMAC provides MII management function to access the control and status registers of the external PHY. The EMACn_MIID register is used to store the data that will be written into the registers of external PHY for write command or the data that is read from the registers of external PHY for read command.
Page 620 NUC970 Technical Reference Manual EMAC n MII Management Control and Address Register (EMACn_MIIDA) The EMAC provides MII management function to access the control and status registers of the external PHY. The EMACn_MIIDA register is used to keep the MII management command information, like the register address, external PHY address, MDC clocking rate, read/write etc.
Page 621: Figure 5.21-6 Mii Management Frame Format
NUC970 Technical Reference Manual Write Command The WRITE defines the MII management command is a read or write. [16] WRITE 0 = MII management command is a read command. 1 = MII management command is a write command. Reserved [15:13] Reserved.
Page 622 NUC970 Technical Reference Manual EMAC n FIFO Threshold Control Register (EMACn_FFTCR) The EMACn_FFTCR defines the high and low threshold of internal FIFOs, including TXFIFO and RXFIFO. The threshold of internal FIFOs is related to EMAC request generation and when the frame transmission starts.
Page 623 NUC970 Technical Reference Manual TXFIFO Low Threshold The TXTHD controls when TXDMA requests internal arbiter for data transfer between system memory and TXFIFO. The TXTHD defines not only the low threshold of TXFIFO, but also the high threshold. The high threshold is the twice of low threshold always. During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops generate request to transfer frame data from system memory to TXFIFO.
Page 624 NUC970 Technical Reference Manual EMAC n Transmit Start Demand Register (EMACn_TSDR) S/W issues a write command to EMACn_TSDR register to make TXDMA to leave Halt state and continue the frame transmission. Register Offset Description Reset Value EMACn_TSDR EMACn_BA+0x0 EMAC n Transmit Start Demand Register Undefined n=0,1 Bits...
Page 625 NUC970 Technical Reference Manual EMAC n Receive Start Demand Register (EMACn_RSDR) S/W issues a write command to EMACn_RSDR register to make RXDMA to leave Halt state and continue the frame reception. Register Offset Description Reset Value EMACn_RSDR EMACn_BA+0x0 EMAC n Receive Start Demand Register Undefined n=0,1 Bits...
Page 626 NUC970 Technical Reference Manual EMAC n Maximum Receive Frame Control Register (EMACn_DMARFC) The EMACn_DMARFC defines the maximum frame length for a received frame that can be stored in the system memory. It is recommend that only use this register while S/W wants to receive a frame which length is greater than 1518 bytes.
Page 627 NUC970 Technical Reference Manual EMAC n MAC Interrupt Enable Register (EMACn_MIEN) The EMACn_MIEN controls the enable of EMAC interrupt status to generate interrupt. Two interrupts, RXINTR for frame reception and TXINTR for frame transmission, are generated from EMAC to CPU. Register Offset Description...
Page 628 NUC970 Technical Reference Manual Transmit Descriptor Unavailable Interrupt Enable Control The TDUIEN controls the TDU (EMACn_MISTA[23]) interrupt generation. If TDU (EMACn_MISTA[23]) is set, and both TDUIEN and TXIEN (EMACn_MIEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If TDUIEN or TXIEN [23] TDUIEN (EMACn_MIEN[16]) is disabled, no TX interrupt is generated to CPU even the TDU...
Page 629 NUC970 Technical Reference Manual Transmit FIFO Underflow Interrupt Enable Control The TXUDIEN controls the TXEMP (EMACn_MISTA[17]) interrupt generation. If TXEMP (EMACn_MISTA[17]) is set, and both TXUDIEN and TXIEN (EMACn_MIEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If TXUDIEN or TXIEN [17] TXUDIEN (EMACn_MIEN[16]) is disabled, no TX interrupt is generated to CPU even the TXEMP...
Page 630 NUC970 Technical Reference Manual DMA Early Notification Interrupt Enable Control The DENIEN controls the DENI (EMACn_MISTA[9]) interrupt generation. If DENI (EMACn_MISTA[9]) is set, and both DENIEN and RXIEN (EMACn_MIEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If DENIEN or RXIEN DENIEN (EMACn_MIEN[0]) is disabled, no RX interrupt is generated to CPU even the DENI (EMACn_MISTA[9]) is set.
Page 631 NUC970 Technical Reference Manual Long Packet Interrupt Enable Control The LPIEN controls the PTLE (EMACn_MISTA[3]) interrupt generation. If PTLE (EMACn_MISTA[3]) is set, and both LPIEN and RXIEN (EMACn_MIEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If LPIEN or RXIEN (EMACn_MIEN[0]) is LPIEN disabled, no RX interrupt is generated to CPU even the PTLE (EMACn_MISTA[3]) is set.
Page 632 NUC970 Technical Reference Manual EMAC n MAC Interrupt Status Register (EMACn_MISTA) The EMACn_MISTA keeps much EMAC statuses, such as frame transmission, reception status and internal FIFO status. The statuses kept in EMACn_MISTA will trigger the reception or transmission interrupt. The EMACn_MISTA is a write clear register and write 1 to corresponding bit clears the status and also clears the interrupt.
Page 633 NUC970 Technical Reference Manual Transmit Descriptor Unavailable Interrupt The TDU high indicates that there is no available TX descriptor for packet transmission and TXDMA will stay at Halt state. Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make TXDMA leave Halt state while new TX descriptor is available.
Page 634 NUC970 Technical Reference Manual Transmit FIFO Underflow Interrupt The TXEMP high indicates the TXFIFO underflow occurred during packet transmission. While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically without S/W intervention. If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control, the TXTHD of FFTCR register, to higher level.
Page 635 NUC970 Technical Reference Manual Receive Descriptor Unavailable Interrupt The RDU high indicates that there is no available RX descriptor for packet reception and RXDMA will stay at Halt state. Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to make RXDMA leave Halt state while new RX descriptor is available.
Page 636 NUC970 Technical Reference Manual Packet Too Long Interrupt The PTLE high indicates the length of the incoming packet is greater than 1518 bytes and the incoming packet is dropped. If the ALP (EMACn_MCMDR[1]) is set, the long packet will be regarded as a good packet and PTLE will not be set. PTLE If the PTLE is high and LPIEN(EMACn_MIEN[3]) is enabled, the RXINTR will be high.
Page 637 NUC970 Technical Reference Manual EMAC n MAC General Status Register (EMACn_MGSTA) The EMACn_MGSTA also keeps the statuses of EMAC. But the statuses in the EMACn_MGSTA will not trigger any interrupt. The EMACn_MGSTA is a write clear register and write 1 to corresponding bit clears the status.
Page 638 NUC970 Technical Reference Manual Transmission Paused The PAU high indicates the next normal packet transmission process will be paused temporally because EMAC received a PAUSE control frame. 0 = Next normal packet transmission process will go on. 1 = Next normal packet transmission process will be paused. Deferred Transmission The DEF high indicates the packet transmission has deferred once.
Page 639 NUC970 Technical Reference Manual EMAC n Missed Packet Count Register (EMACn_MPCNT) The EMACn_MPCNT keeps the number of packets that were dropped due to various types of receive errors. The EMACn_MPCNT is a read clear register. In addition, S/W also can write an initial value to EMACn_MPCNT and the missed packet counter will start counting from that initial value.
Page 640 NUC970 Technical Reference Manual EMAC n MAC Receive Pause Count Register (EMACn_MRPC) The EMAC supports the PAUSE control frame reception and recognition. If EMAC received a PAUSE control frame, the operand field of the PAUSE control frame will be extracted and stored in the EMACn_MRPC register.
Page 641 NUC970 Technical Reference Manual EMAC n DMA Receive Frame Status Register (EMACn_DMARFS) The EMACn_DMARFS is used to keep the Length/Type field of each incoming Ethernet packet. Register Offset Description Reset Value EMACn_DMARF EMACn_BA+0x0C EMAC n DMA Receive Frame Status Register 0x0000_0000 n=0,1 Reserved...
Page 642 NUC970 Technical Reference Manual EMAC n Current Transmit Descriptor Start Address Register (EMACn_CTXDSA) Register Offset R/W Description Reset Value EMACn_CTXDSA EMACn_BA+0x0CC R EMAC n Current Transmit Descriptor Start Address Register 0x0000_0000 n=0,1 CTXDSA CTXDSA CTXDSA CTXDSA Bits Description Current Transmit Descriptor Start Address [31:0] CTXDSA The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently.
Page 643 NUC970 Technical Reference Manual EMAC n Current Transmit Buffer Start Address Register (EMACn_CTXBSA) Register Offset R/W Description Reset Value EMACn_CTXBSA EMACn_BA+0x0D EMAC n Current Transmit Buffer Start Address Register 0x0000_0000 n=0,1 CTXBSA CTXBSA CTXBSA CTXBSA Bits Description Current Transmit Buffer Start Address [31:0] CTXBSA The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA...
Page 644 NUC970 Technical Reference Manual EMAC n Current Receive Descriptor Start Address Register (EMACn_CRXDSA) Register Offset R/W Description Reset Value EMACn_CRXDSA EMACn_BA+0x0D EMAC n Current Receive Descriptor Start Address Register 0x0000_0000 n=0,1 CRXDSA CRXDSA CRXDSA CRXDSA Bits Description Current Receive Descriptor Start Address [31:0] CRXDSA The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently.
Page 645 NUC970 Technical Reference Manual EMAC n Current Receive Buffer Start Address Register (EMACn_CRXBSA) Register Offset R/W Description Reset Value EMACn_CRXBSA EMACn_BA+0x0D8 R EMAC n Current Receive Buffer Start Address Register 0x0000_0000 n=0,1 CRXBSA CRXBSA CRXBSA CRXBSA Bits Description Current Receive Buffer Start Address [31:0] CRXBSA The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA...
Page 646 NUC970 Technical Reference Manual EMAC n Time Stamp Control Register (EMACn_TSCTL) Register Offset Description Reset Value EMACn_TSCT EMACn_BA+0x100 R/W EMAC n Time Stamp Control Register 0x0000_0000 n=0,1 Reserved Reserved Reserved Reserved TSALMEN Reserved TSUPDATE TSMODE TSIEN TSEN Bits Description [31:6] Reserved Reserved.
Page 647 NUC970 Technical Reference Manual Time Stamp Counter Initialization Enable Control Set this bit high enables Ethernet MAC controller to load value of register EMACn_UPDSEC and EMACn_UPDSUBSEC to PTP time stamp counter. TSIEN After the load operation finished, Ethernet MAC controller clear this bit to low automatically.
Page 648 NUC970 Technical Reference Manual EMAC n Time Stamp Counter Second Register (EMACn_TSSEC) Register Offset Description Reset Value EMACn_TSSEC EMACn_BA+0x110 R/W EMAC n Time Stamp Counter Second Register 0x0000_0000 n=0,1 Bits Description Time Stamp Counter Second [31:0] This register reflects the bit [63:32] value of 64-bit reference timing counter. This 32-bit value is used as the second part of time stamp when TSEN (EMACn_TSCTL[0]) is high.
Page 649 NUC970 Technical Reference Manual EMAC n Time Stamp Counter Sub Second Register (EMACn_TSSUBSEC) Register Offset Description Reset Value EMACn_TSSUB EMACn_BA+0x114 R/W EMAC n Time Stamp Counter Sub Second Register 0x0000_0000 n=0,1 SUBSEC SUBSEC SUBSEC SUBSEC Bits Description Time Stamp Counter Sub-second This register reflects the bit [31:0] value of 64-bit reference timing counter.
Page 650 NUC970 Technical Reference Manual EMAC n Time Stamp Increment Register (EMACn_TSINC) Register Offset Description Reset Value EMACn_TSINC EMACn_BA+0x118 R/W EMAC n Time Stamp Increment Register 0x0000_0000 n=0,1 Reserved Reserved Reserved CNTINC Bits Description [31:8] Reserved Reserved. Time Stamp Counter Increment Time stamp counter increment value.
Page 651 NUC970 Technical Reference Manual EMAC n Time Stamp Addend Register (EMACn_TSADDEND) Register Offset Description Reset Value EMACn_TSAD EMACn_BA+0x11 DEND EMAC n Time Stamp Addend Register 0x0000_0000 n=0,1 ADDEND ADDEND ADDEND ADDEND Bits Description Time Stamp Counter Addend This register keeps a 32-bit value for accumulator to enable increment of EMACn_TSSUBSEC.
Page 652 NUC970 Technical Reference Manual EMAC n Time Stamp Update Second Register (EMACn_UPDSEC) Register Offset Description Reset Value EMACn_UPDSE EMACn_BA+0x120 R/W EMAC n Time Stamp Update Second Register 0x0000_0000 n=0,1 Bits Description Time Stamp Counter Second Update When TSIEN (EMACn_TSCTL[1]) is high. EMAC loads this 32-bit value to [31:0] EMACn_TSSEC directly.
Page 653 NUC970 Technical Reference Manual EMAC n Time Stamp Update Sub Second Register (EMACn_UPDSUBSEC) Register Offset Description Reset Value EMACn_UPDSU EMACn_BA+0x12 BSEC EMAC n Time Stamp Update Sub Second Register 0x0000_0000 n=0,1 SUBSEC SUBSEC SUBSEC SUBSEC Bits Description Time Stamp Counter Sub-second Update When TSIEN (EMACn_TSCTL[1]) is high.
Page 654 NUC970 Technical Reference Manual EMAC n Time Stamp Alarm Second Register (EMACn_ALMSEC) Register Offset Description Reset Value EMACn_ALMSE EMACn_BA+0x128 R/W EMAC n Time Stamp Alarm Second Register 0x0000_0000 n=0,1 Bits Description Time Stamp Counter Second Alarm Time stamp counter second part alarm value. This value is only useful when TSALMEN (EMACn_TSCTL[5]) high.
Page 655 NUC970 Technical Reference Manual EMAC n Time Stamp Alarm Sub Second Register (EMACn_ALMSUBSEC) Register Offset Description Reset Value EMACn_ALMSU EMACn_BA+0x12 BSEC EMAC n Time Stamp Alarm Sub Second Register 0x0000_0000 n=0,1 SUBSEC SUBSEC SUBSEC SUBSEC Bits Description Time Stamp Counter Sub-second Alarm Time stamp counter sub-second part alarm value.
Page 656: Usb 2.0 Device Controller (Usbd)
NUC970 Technical Reference Manual 5.22 USB 2.0 Device Controller (USBD) 5.22.1 Overview The USB device controller interfaces the AHB bus and the UTMI bus. The USB controller contains both the AHB master interface and AHB slave interface. CPU programs the USB controller registers through the AHB slave interface.
Page 657: Block Diagram
NUC970 Technical Reference Manual 5.22.3 Block Diagram AHB Bus USB Device Controller Registers UTMI Control- interface USB 2.0 USB_DP Protocol transceiver USB_DM 12-EPs controller 4K Buffer registers Figure 5.22-1 USB Device Controller Block Diagram 5.22.4 Basic Configuration USB device clock source is derived from PLL and USB PHY. User has to set the PLL related configurations before USB device enabled.
Page 658 NUC970 Technical Reference Manual controller. The mode can be selected, when the data payload sent to host is always equal to MPS size. SHORTTXEN Data Availability In Buffer Data Sent/NAK Sent < Max. Packet Size NAK sent >= Max. Packet Size Data payload of max.
Page 659 NUC970 Technical Reference Manual DMA will be enabled to fetch the descriptor which describes the real memory address and length. The descriptor will be an 8-byte format, like the following: Format [31] [30] [29:0] Word0 MEM_ADDR[31:0] Word1 Reserved Count[19:0] MEM_ADDR: It specifies the memory address (AHB address). EOT: end of transfer.
Page 660: Registers Map
NUC970 Technical Reference Manual 5.22.6 Registers Map Register Offset Description Reset Value USBD Base Address: USBD_BA = 0x4001_9000 USBD_GINTSTS USBD_BA+0x000 Global Interrupt Status Register 0x0000_0000 USBD_GINTEN USBD_BA+0x008 Global Interrupt Enable Register 0x0000_0001 USBD_BUSINTSTS USBD_BA+0x010 USB Bus Interrupt Status Register 0x0000_0000 USBD_BUSINTEN USBD_BA+0x014 USB Bus Interrupt Enable Register...
Page 661 NUC970 Technical Reference Manual Endpoint A Maximum Packet Size USBD_EPAMPS USBD_BA+0x078 0x0000_0000 Register USBD_EPATXCNT USBD_BA+0x07C Endpoint A Transfer Count Register 0x0000_0000 USBD_EPACFG USBD_BA+0x080 Endpoint A Configuration Register 0x0000_0012 USBD_EPABUFSTART USBD_BA+0x084 Endpoint A RAM Start Address Register 0x0000_0000 USBD_EPABUFEND USBD_BA+0x088 Endpoint A RAM End Address Register 0x0000_0000 USBD_EPBDAT USBD_BA+0x08C Endpoint B Data Register...
Page 662 NUC970 Technical Reference Manual USBD_EPDTXCNT USBD_BA+0x0F4 Endpoint D Transfer Count Register 0x0000_0000 USBD_EPDCFG USBD_BA+0x0F8 Endpoint D Configuration Register 0x0000_0042 USBD_EPDBUFSTART USBD_BA+0x0FC Endpoint D RAM Start Address Register 0x0000_0000 USBD_EPDBUFEND USBD_BA+0x100 Endpoint D RAM End Address Register 0x0000_0000 USBD_EPEDAT USBD_BA+0x104 Endpoint E Data Register 0x0000_0000 USBD_EPEINTSTS USBD_BA+0x108...
Page 663 NUC970 Technical Reference Manual USBD_EPGCFG USBD_BA+0x170 Endpoint G Configuration Register 0x0000_0072 USBD_EPGBUFSTART USBD_BA+0x174 Endpoint G RAM Start Address Register 0x0000_0000 USBD_EPGBUFEND USBD_BA+0x178 Endpoint G RAM End Address Register 0x0000_0000 USBD_EPHDAT USBD_BA+0x17C Endpoint H Data Register 0x0000_0000 USBD_EPHINTSTS USBD_BA+0x180 Endpoint H Interrupt Status Register 0x0000_0003 USBD_EPHINTEN USBD_BA+0x184...
Page 664 NUC970 Technical Reference Manual USBD_EPJBUFSTART USBD_BA+0x1EC Endpoint J RAM Start Address Register 0x0000_0000 USBD_EPJBUFEND USBD_BA+0x1F0 Endpoint J RAM End Address Register 0x0000_0000 USBD_EPKDAT USBD_BA+0x1F4 Endpoint K Data Register 0x0000_0000 USBD_EPKINTSTS USBD_BA+0x1F8 Endpoint K Interrupt Status Register 0x0000_0003 USBD_EPKINTEN USBD_BA+0x1FC Endpoint K Interrupt Enable Register 0x0000_0000 Endpoint K Data Available Count USBD_EPKDATCNT...
Page 665: Register Description
NUC970 Technical Reference Manual 5.22.7 Register Description Publication Release Date: Dec. 15, 2015 - 665 - Revision V1.30...
Page 666 NUC970 Technical Reference Manual Global Interrupt Status Register (USBD_GINTSTS) Register Offset Description Reset Value USBD_GINTSTS USBD_BA+0x000 R Global Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved EPLIF EPKIF EPJIF EPIIF EPHIF EPGIF EPFIF EPEIF EPDIF EPCIF EPBIF EPAIF CEPIF USBIF Bits Description Reserved [31:14]...
Page 667 NUC970 Technical Reference Manual Endpoints G Interrupt When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. EPGIF 0 = No interrupt event occurred. 1 = The related interrupt event is occurred. Endpoints F Interrupt When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.
Page 668 NUC970 Technical Reference Manual Global Interrupt Enable Register (USBD_GINTEN) Register Offset Description Reset Value USBD_GINTEN USBD_BA+0x008 Global Interrupt Enable Register 0x0000_0001 Reserved Reserved Reserved EPLIEN EPKIEN EPJIEN EPIIEN EPHIEN EPGIENNN EPFIEN EPEIEN EPDIEN EPCIEN EPBIEN EPAIEN CEPIEN USBIEN Bits Description Reserved [31:14] Reserved.
Page 669 NUC970 Technical Reference Manual Interrupt Enable Control for Endpoint G When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G EPGIEN 0 = The related interrupt Disabled. 1 = The related interrupt Enabled. Interrupt Enable Control for Endpoint F When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F...
Page 670 NUC970 Technical Reference Manual USB Bus Interrupt Status Register (USBD_BUSINTSTS) Register Offset R/W Description Reset Value USBD_BUSINTSTS USBD_BA+0x010 R/W USB Bus Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved VBUSDETIF Reserved PHYCLKVLDIF DMADONEIF HISPDIF SUSPENDIF RESUMEIF RSTIF SOFIF Bits Description [31:9] Reserved Reserved.
Page 671 NUC970 Technical Reference Manual Resume When set, this bit indicates that a device resume has occurred. RESUMEIF 0 = No device resume has occurred. 1 = Device resume has occurred. Note: Write 1 to clear this bit to 0. Reset Status When set, this bit indicates that either the USB root port reset is end.
Page 672 NUC970 Technical Reference Manual USB Bus Interrupt Enable Register (USBD_BUSINTEN) Register Offset Description Reset Value USBD_BUSINTEN USBD_BA+0x014 R/W USB Bus Interrupt Enable Register 0x0000_0040 Reserved Reserved Reserved VBUSDETIEN Reserved PHYCLKVLDIEN DMADONEIEN HISPDIEN SUSPENDIEN RESUMEIEN RSTIEN SOFIEN Bits Description Reserved [31:9] Reserved.
Page 673 NUC970 Technical Reference Manual Resume This bit enables the Resume interrupt. RESUMEIEN 0 = Resume interrupt Disabled. 1 = Resume interrupt Enabled. Reset Status This bit enables the USB-Reset interrupt. RSTIEN 0 = USB-Reset interrupt Disabled. 1 = USB-Reset interrupt Enabled. SOF Interrupt This bit enables the SOF interrupt.
Page 674 NUC970 Technical Reference Manual USB Operational Register (USBD_OPER) Register Offset Description Reset Value USBD_OPER USBD_BA+0x018 USB Operational Register 0x0000_0002 Reserved Reserved Reserved Reserved CURSPD HISPDEN RESUMEEN Bits Description [31:3] Reserved Reserved. USB Current Speed CURSPD 0 = The device has settled in Full Speed. 1 = The USB device controller has settled in High-speed.
Page 675 NUC970 Technical Reference Manual USB Frame Count Register (USBD_FRAMECNT) Register Offset R/W Description Reset Value USBD_FRAMECNT USBD_BA+0x01C USB Frame Count Register 0x0000_0000 Reserved Reserved Reserved FRAMECNT FRAMECNT MFRAMECNT Bits Description [31:14] Reserved Reserved. Frame Counter FRAMECNT [13:3] This field contains the frame count from the most recent start-of-frame packet. Micro-frame Counter [2:0] MFRAMECNT...
Page 676 NUC970 Technical Reference Manual USB Function Address Register (USBD_FADDR) Register Offset Description Reset Value USBD_FADDR USBD_BA+0x020 R/W USB Function Address Register 0x0000_0000 Reserved Reserved Reserved Reserved FADDR Bits Description [31:7] Reserved Reserved. USB Function Address [6:0] FADDR This field contains the current USB address of the device. This field is cleared when a root port reset is detected.
Page 677 NUC970 Technical Reference Manual USB Test Mode Register (USBD_TEST) Register Offset Description Reset Value USBD_TEST USBD_BA+0x024 USB Test Mode Register 0x0000_0000 Reserved Reserved Reserved Reserved TESTMODE Bits Description [31:3] Reserved Reserved. Test Mode Selection 000 = Normal Operation. 001 = Test_J. 010 = Test_K.
Page 678 NUC970 Technical Reference Manual Control Endpoint Data Buffer (USBD_CEPDAT) Register Offset Description Reset Value USBD_CEPDAT USBD_BA+0x028 R/W Control Endpoint Data Buffer 0x0000_0000 Bits Description Control-endpoint Data Buffer [31:0] Control endpoint data buffer for the buffer transaction (read or write). Note: Only word or byte access are supported. Publication Release Date: Dec.
Page 679 NUC970 Technical Reference Manual Control Endpoint Control Register (USBD_CEPCTL) Register Offset R/W Description Reset Value USBD_CEPCTL USBD_BA+0x02C R/W Control Endpoint Control Register 0x0000_0000 Reserved Reserved Reserved Reserved FLUSH ZEROLEN STALLEN NAKCLR Bits Description [31:4] Reserved Reserved. CEP-fLUSH Bit 0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be FLUSH cleared.
Page 680 NUC970 Technical Reference Manual No Acknowledge Control This bit plays a crucial role in any control transfer. 0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase. This mechanism holds the host from moving to the next request, until the local CPU is also ready to process NAKCLR the next request.
Page 681 NUC970 Technical Reference Manual Control Endpoint Interrupt Enable(USBD_CEPINTEN) Register Offset R/W Description Reset Value USBD_CEPINTEN USBD_BA+0x030 R/W Control Endpoint Interrupt Enable 0x0000_0000 Reserved Reserved Reserved BUFEMPTYIEN BUFFULLIEN STSDONEIEN ERRIEN STALLIEN NAKIEN RXPKIEN TXPKIEN PINGIEN INTKIEN OUTTKIEN SETUPPKIEN SETUPTKIEN Bits Description [31:13] Reserved Reserved.
Page 682 NUC970 Technical Reference Manual Data Packet Transmitted Interrupt TXPKIEN 0 = The data packet transmitted interrupt in Control Endpoint Disabled. 1 = The data packet transmitted interrupt in Control Endpoint Enabled. Ping Token Interrupt PINGIEN 0 = The ping token interrupt in Control Endpoint Disabled. 1 = The ping token interrupt Control Endpoint Enabled.
Page 683 NUC970 Technical Reference Manual Control Endpoint Interrupt Status (USBD_CEPINTSTS) Register Offset R/W Description Reset Value USBD_CEPINTSTS USBD_BA+0x034 R/W Control Endpoint Interrupt Status 0x0000_1800 Reserved Reserved Reserved BUFEMPTYIF BUFFULLIF STSDONEIF ERRIF STALLIF NAKIF RXPKIF TXPKIF PINGIF INTKIF OUTTKIF SETUPPKIF SETUPTKIF Bits Description [31:13] Reserved...
Page 684 NUC970 Technical Reference Manual Data Packet Received Interrupt 0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. RXPKIF 1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
Page 685 NUC970 Technical Reference Manual Control Endpoint In Transfer Data Count (USBD_CEPTXCNT) Register Offset R/W Description Reset Value USBD_CEPTXCNT USBD_BA+0x038 R/W Control Endpoint In Transfer Data Count 0x0000_0000 Reserved Reserved Reserved TXCNT Bits Description [31:8] Reserved Reserved. In-transfer Data Count There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for [7:0] TXCNT...
Page 686 NUC970 Technical Reference Manual Control Endpoint Out Transfer Data Count (USBD_CEPRXCNT) Register Offset R/W Description Reset Value USBD_CEPRXCNT USBD_BA+0x03C Control Endpoint Out Transfer Data Count 0x0000_0000 Reserved Reserved Reserved RXCNT Bits Description [31:8] Reserved Reserved. Out-transfer Data Count [7:0] RXCNT The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer.
Page 687 NUC970 Technical Reference Manual Control Endpoint Data Count (USBD_CEPDATCNT) Register Offset R/W Description Reset Value USBD_CEPDATCNT USBD_BA+0x040 Control Endpoint Data Count 0x0000_0000 Reserved Reserved DATCNT DATCNT Bits Description [31:16] Reserved Reserved. Control-endpoint Data Count DATCNT [15:0] The USB device controller maintains the count of the data of control-endpoint. Publication Release Date: Dec.
Page 688 NUC970 Technical Reference Manual Setup1 & Setup0 bytes (USBD_SETUP1_0) Register Offset R/W Description Reset Value USBD_SETUP1_0 USBD_BA+0x044 Setup1 & Setup0 bytes 0x0000_0000 Reserved Reserved SETUP1 SETUP0 Bits Description [31:16] Reserved Reserved. Setup Byte 1[15:8] This register provides byte 1 of the last setup packet received. For a Standard Device Request, the following bRequest Code information is returned.
Page 689 NUC970 Technical Reference Manual Setup Byte 0[7:0] This register provides byte 0 of the last setup packet received. For a Standard Device Request, the following bmRequestType information is returned. Bit 7(Direction): 0: Host to device 1: Device to host Bit 6-5 (Type): 00: Standard 01: Class [7:0]...
Page 690 NUC970 Technical Reference Manual Setup3 & Setup2 Bytes (USBD_SETUP3_2) Register Offset R/W Description Reset Value USBD_SETUP3_2 USBD_BA+0x048 Setup3 & Setup2 Bytes 0x0000_0000 Reserved Reserved SETUP3 SETUP2 Bits Description Reserved [31:16] Reserved. Setup Byte 3 [15:8] [15:8] SETUP3 This register provides byte 3 of the last setup packet received. For a Standard Device Request, the most significant byte of the wValue field is returned.
Page 691 NUC970 Technical Reference Manual Setup5 & Setup4 Bytes (USBD_SETUP5_4) Register Offset R/W Description Reset Value USBD_SETUP5_4 USBD_BA+0x04C Setup5 & Setup4 Bytes 0x0000_0000 Reserved Reserved SETUP5 SETUP4 Bits Description [31:16] Reserved Reserved. Setup Byte 5[15:8] [15:8] SETUP5 This register provides byte 5 of the last setup packet received. For a Standard Device Request, the most significant byte of the wIndex field is returned.
Page 692 NUC970 Technical Reference Manual Setup7 & Setup6 bytes (USBD_SETUP7_6) Register Offset R/W Description Reset Value USBD_SETUP7_6 USBD_BA+0x050 Setup7 & Setup6 Bytes 0x0000_0000 Reserved Reserved SETUP7 SETUP6 Bits Description [31:16] Reserved Reserved. Setup Byte 7[15:8] [15:8] SETUP7 This register provides byte 7 of the last setup packet received. For a Standard Device Request, the most significant byte of the wLength field is returned.
Page 693 NUC970 Technical Reference Manual Control Endpoint RAM Start Address Register (USBD_CEPBUFSTART) Register Offset R/W Description Reset Value USBD_CEPBUFSTART USBD_BA+0x054 R/W Control Endpoint RAM Start Address Register 0x0000_0000 Reserved Reserved Reserved SADDR SADDR Bits Description [31:12] Reserved Reserved. Control-endpoint Start Address SADDR [11:0] This is the start-address of the RAM space allocated for the control-endpoint.
Page 694 NUC970 Technical Reference Manual Control Endpoint RAM End Address Register (USBD_CEPBUFEND) Register Offset R/W Description Reset Value USBD_CEPBUFEND USBD_BA+0x058 R/W Control Endpoint RAM End Address Register 0x0000_0000 Reserved Reserved Reserved EADDR EADDR Bits Description [31:12] Reserved Reserved. Control-endpoint End Address EADDR [11:0] This is the end-address of the RAM space allocated for the control-endpoint.
Page 695 NUC970 Technical Reference Manual DMA Control Status Register (USBD_DMACTL) Register Offset R/W Description Reset Value USBD_DMACTL USBD_BA+0x05C R/W DMA Control Status Register 0x0000_0000 Reserved Reserved Reserved DMARST SGEN DMAEN DMARD EPNUM Bits Description [31:8] Reserved Reserved. Reset DMA State Machine DMARST 0 = No reset the DMA state machine.
Page 696 NUC970 Technical Reference Manual DMA Count Register (USBD_DMACNT) Register Offset R/W Description Reset Value USBD_DMACNT USBD_BA+0x060 R/W DMA Count Register 0x0000_0000 Reserved Reserved DMACNT DMACNT DMACNT Bits Description [31:20] Reserved Reserved. DMA Transfer Count DMACNT [19:0] The transfer count of the DMA operation to be performed is written to this register. Publication Release Date: Dec.
Page 697 NUC970 Technical Reference Manual Endpoint A~L Data Register (USBD_EPADAT~ USBD_EPLDAT) Register Offset Description Reset Value USBD_EPADAT USBD_BA+0x064 Endpoint A Data Register 0x0000_0000 USBD_EPBDAT USBD_BA+0x08C Endpoint B Data Register 0x0000_0000 USBD_EPCDAT USBD_BA+0x0B4 Endpoint C Data Register 0x0000_0000 USBD_EPDDAT USBD_BA+0x0DC Endpoint D Data Register 0x0000_0000 USBD_EPEDAT USBD_BA+0x104...
Page 698 NUC970 Technical Reference Manual Endpoint A~L Interrupt Status Register (USBD_EPAINTSTS~ USBD_EPLINTSTS) Register Offset Description Reset Value USBD_EPAINTSTS USBD_BA+0x068 Endpoint A Interrupt Status Register 0x0000_0003 USBD_EPBINTSTS USBD_BA+0x090 Endpoint B Interrupt Status Register 0x0000_0003 USBD_EPCINTSTS USBD_BA+0x0B8 Endpoint C Interrupt Status Register 0x0000_0003 USBD_EPDINTSTS USBD_BA+0x0E0 Endpoint D Interrupt Status Register 0x0000_0003...
Page 699 NUC970 Technical Reference Manual NYET Sent 0 = The space available in the RAM is sufficient to accommodate the next on coming data packet. [10] NYETIF 1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
Page 700 NUC970 Technical Reference Manual Buffer Empty For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes. 0 = The endpoint buffer is not empty. 1 = The endpoint buffer is empty. BUFEMPTYIF For an OUT endpoint: 0 = The currently selected buffer has not a count of 0.
Page 701 NUC970 Technical Reference Manual Endpoint A~L Interrupt Enable Control Register (USBD_EPAINTEN~ USBD_EPLINTEN) Register Offset Description Reset Value USBD_EPAINTEN USBD_BA+0x06C Endpoint A Interrupt Enable Register 0x0000_0000 USBD_EPBINTEN USBD_BA+0x094 Endpoint B Interrupt Enable Register 0x0000_0000 USBD_EPCINTEN USBD_BA+0x0BC Endpoint C Interrupt Enable Register 0x0000_0000 USBD_EPDINTEN USBD_BA+0x0E4...
Page 702 NUC970 Technical Reference Manual ERR Interrupt Enable Control When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint. ERRIEN [11] 0 = Error event interrupt Disabled. 1 = Error event interrupt Enabled. NYET Interrupt Enable Control When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
Page 703 NUC970 Technical Reference Manual Short Packet Transferred Interrupt Enable Control When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host. SHORTTXIEN 0 = Short data packet interrupt Disabled. 1 = Short data packet interrupt Enabled.
Page 704 NUC970 Technical Reference Manual Endpoint A~L Data Available Count Register (USBD_EPADATCNT~ USBD_EPLDATCNT) Register Offset Description Reset Value USBD_EPADATCN USBD_BA+0x070 Endpoint A Data Available Count Register 0x0000_0000 USBD_EPBDATCN USBD_BA+0x098 Endpoint B Data Available Count Register 0x0000_0000 USBD_EPCDATCN USBD_BA+0x0C0 Endpoint C Data Available Count Register 0x0000_0000 USBD_EPDDATCN USBD_BA+0x0E8...
Page 705 NUC970 Technical Reference Manual Data Count For an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the DATCNT number of valid bytes in the IN endpoint packet buffer. [15:0] For an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer.
Page 706 NUC970 Technical Reference Manual Endpoint A~L Response Control Register (USBD_EPARSPCTL~ USBD_EPLRSPCTL) Register Offset Description Reset Value USBD_EPARSPCT USBD_BA+0x074 Endpoint A Response Control Register 0x0000_0000 USBD_EPBRSPCT USBD_BA+0x09C Endpoint B Response Control Register 0x0000_0000 USBD_EPCRSPCT USBD_BA+0x0C4 Endpoint C Response Control Register 0x0000_0000 USBD_EPDRSPCT USBD_BA+0x0EC Endpoint D Response Control Register...
Page 707 NUC970 Technical Reference Manual Buffer Disable Control This bit is used to receive unknown size OUT short packet. The received packet size is reference USBD_EPxDATCNT register. DISBUF 0 = Buffer Not Disabled when Bulk-OUT short packet is received. 1 = Buffer Disabled when Bulk-OUT short packet is received. Short Packet Transfer Enable This bit is applicable only in case of Auto-Validate Method.
Page 708 NUC970 Technical Reference Manual Endpoint A~L Maximum Packet Size Register (USBD_EPAMPS~ USBD_EPLMPS) Register Offset Description Reset Value USBD_EPAMPS USBD_BA+0x078 Endpoint A Maximum Packet Size Register 0x0000_0000 USBD_EPBMPS USBD_BA+0x0A0 Endpoint B Maximum Packet Size Register 0x0000_0000 USBD_EPCMPS USBD_BA+0x0C8 Endpoint C Maximum Packet Size Register 0x0000_0000 USBD_EPDMPS USBD_BA+0x0F0 Endpoint D Maximum Packet Size Register...
Page 709 NUC970 Technical Reference Manual Endpoint A~L Transfer Count Register (USBD_EPATXCNT~ USBD_EPLTXCNT) Register Offset Description Reset Value USBD_EPATXCN USBD_BA+0x07C Endpoint A Transfer Count Register 0x0000_0000 USBD_EPBTXCN USBD_BA+0x0A4 Endpoint B Transfer Count Register 0x0000_0000 USBD_EPCTXCN USBD_BA+0x0CC Endpoint C Transfer Count Register 0x0000_0000 USBD_EPDTXCN USBD_BA+0x0F4 Endpoint D Transfer Count Register...
Page 710 NUC970 Technical Reference Manual Endpoint Transfer Count For IN endpoints, this field determines the total number of bytes to be sent to the host [10:0] TXCNT in case of manual validation method. For OUT endpoints, this field has no effect. Publication Release Date: Dec.
Page 711 NUC970 Technical Reference Manual Endpoint A~L Configuration Register (USBD_EPACFG~ USBD_EPLCFG) Register Offset Description Reset Value USBD_EPACF USBD_BA+0x080 Endpoint A Configuration Register 0x0000_0012 USBD_EPBCF USBD_BA+0x0A8 Endpoint B Configuration Register 0x0000_0022 USBD_EPCCF USBD_BA+0x0D0 Endpoint C Configuration Register 0x0000_0032 USBD_EPDCF USBD_BA+0x0F8 Endpoint D Configuration Register 0x0000_0042 USBD_EPECF USBD_BA+0x120...
Page 712 NUC970 Technical Reference Manual Endpoint Number [7:4] EPNUM This field selects the number of the endpoint. Valid numbers 1 to 15. Note: Do not support two endpoints have same endpoint number. Endpoint Direction 0 = out-endpoint (Host OUT to Device). EPDIR 1 = in-endpoint (Host IN to Device).
Page 713 NUC970 Technical Reference Manual Endpoint A~L RAM Start Address Register (USBD_EPABUFSTART~ USBD_EPLBUFSTART) Register Offset Description Reset Value USBD_EPABUFSTAR USBD_BA+0x084 Endpoint A RAM Start Address Register 0x0000_0000 USBD_EPBBUFSTAR USBD_BA+0x0AC Endpoint B RAM Start Address Register 0x0000_0000 USBD_EPCBUFSTAR USBD_BA+0x0D4 Endpoint C RAM Start Address Register 0x0000_0000 USBD_EPDBUFSTAR USBD_BA+0x0FC...
Page 714 NUC970 Technical Reference Manual Endpoint A~L RAM End Address Register (USBD_EPABUFEND~ USBD_EPLBUFEND) Register Offset Description Reset Value USBD_EPABUFEND USBD_BA+0x088 Endpoint A RAM End Address Register 0x0000_0000 USBD_EPBBUFEND USBD_BA+0x0B0 Endpoint B RAM End Address Register 0x0000_0000 USBD_EPCBUFEND USBD_BA+0x0D8 Endpoint C RAM End Address Register 0x0000_0000 USBD_EPDBUFEND USBD_BA+0x100...
Page 715 NUC970 Technical Reference Manual AHB Address Register (USBD_DMAADDR) Register Offset Description Reset Value USBD_DMAADDR USBD_BA+0x700 AHB DMA Address Register 0x0000_0000 DMAADDR DMAADDR DMAADDR DMAADDR Bits Description DMAADDR [31:0] DMAADDR The register specifies the address from which the DMA has to read / write. The address must WORD (32-bit) aligned.
Page 716 NUC970 Technical Reference Manual USB PHY Control Register (USBD_PHYCTL) Register Offset Description Reset Value USBD_PHYCTL USBD_BA+0x704 USB PHY Control Register 0x0000_0420 VBUSDET Reserved WKEN Reserved Reserved PHYEN DPPUEN Reserved Bits Description VBUS Status [31] VBUSDET 0 = The VBUS is not detected yet. 1 = The VBUS is detected.
Page 717: Usb Host Controller (Usbh)
NUC970 Technical Reference Manual 5.23 USB Host Controller (USBH) 5.23.1 Overview The Universal Serial Bus (USB) is a fast, bi-directional, isochronous, low-cost, dynamically attachable serial interface standard intended for modem, scanners, PDAs, keyboards, mice, and digital imaging devices. The USB is a 4-wire serial cable bus that supports serial data exchange between a Host Controller and a network of peripheral devices.
Page 718: Block Diagram
NUC970 Technical Reference Manual 5.23.3 Block Diagram AHB-2 (System Memory Access) AHB1 (Register Access) USB 2.0 Host controller USB 1.1 Host Controller EHCI Host Controller (OHCI) Port 1 Port 2 Port 1 Port 2 Port Routing Logic Port 1 Port 2 USB Bus Figure 5.23-1 USB Host Controller Block Diagram 5.23.4 Basic Configuration...
Page 719 NUC970 Technical Reference Manual data through the memory interfacing signals. EHCI accepts the data and moves them to the downstream device. 5.23.5.2 OHCI Controller  AHB Interface The OpenHCI Host Controller is connected to the system by the AHB bus. The design requires both master and slave bus operations.
Page 720 NUC970 Technical Reference Manual  Data Buffer The Data Buffer serves as the data interface between the Bus Master and the SIE. It is a combination of a 64-byte latched based bi-directional asynchronous FIFO and a single Dword AHB Holding Register.
Page 721: Register Map
NUC970 Technical Reference Manual 5.23.6 Register Map Register Offset Description Reset Value EHCI Base Address: EHCI_BA = 0xB000_5000 OHCI_BA = 0xB000_7000 EHCVNR EHCI_BA+0x000 EHCI Version Number Register 0x0095_0020 EHCSPR EHCI_BA+0x004 EHCI Structural Parameters Register 0x0000_0012 EHCCPR EHCI_BA+0x008 EHCI Capability Parameters Register 0x0000_0000 UCMDR EHCI_BA+0x020...
Page 722 NUC970 Technical Reference Manual HcFmRem OHCI_BA+0x038 Host Controller Frame Remaining Register 0x0000_0000 HcFNum OHCI_BA+0x03C Host Controller Frame Number Register 0x0000_0000 HcPerSt OHCI_BA+0x040 Host Controller Periodic Start Register 0x0000_0000 HcLSTH OHCI_BA+0x044 Host Controller Low Speed Threshold Register 0x0000_0628 HcRhDeA OHCI_BA+0x048 Host Controller Root Hub Descriptor A Register 0x0100_0002 HcRhDeB OHCI_BA+0x04C...
Page 723: Register Description
NUC970 Technical Reference Manual 5.23.7 Register Description Publication Release Date: Dec. 15, 2015 - 723 - Revision V1.30...
Page 724 NUC970 Technical Reference Manual EHCI Version Number Register (EHCVNR) Register Offset Description Reset Value EHCVNR EHCI_BA+0x000 EHCI Version Number Register 0x0095_0020 VERSION VERSION Reserved CRLEN Bits Description Host Controller Interface Version Number This is a two-byte register containing a BCD encoding of the EHCI revision number VERSION [31:16] supported by this host controller.
Page 725 NUC970 Technical Reference Manual EHCI Structural Parameters Register (EHCSPR) Register Offset Description Reset Value EHCSPR EHCI_BA+0x004 EHCI Structural Parameters Register 0x0000_0012 Reserved Reserved N_CC N_PCC Reserved N_PORTS Bits Description Reserved [31:16] Reserved. Number of Companion Controller This field indicates the number of companion controllers associated with this USB 2.0 host controller.
Page 726 NUC970 Technical Reference Manual EHCI Capability Parameters Register (EHCCPR) Register Offset Description Reset Value EHCCPR EHCI_BA+0x008 EHCI Capability Parameters Register 0x0000_0000 Reserved Reserved EECP Reserved ASPC PFLF AC64 Bits Description [31:16] Reserved Reserved. EHCI Extended Capabilities Pointer (EECP) [15:8] EECP 0 = No extended capabilities are implemented.
Page 727 NUC970 Technical Reference Manual USB Command Register (UCMDR) Register Offset Description Reset Value UCMDR EHCI_BA+0x020 USB Command Register 0x0008_0000 Reserved Reserved Reserved IAAD ASEN PSEN FLSZ HCRST Bits Description Reserved [31:24] Reserved. Interrupt Threshold Control (R/W) This field is used by system software to select the maximum rate at which the host controller will issue interrupts.
Page 728 NUC970 Technical Reference Manual Interrupt on Async Advance Doorbell (R/W) This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell.
Page 729 NUC970 Technical Reference Manual Run/Stop (R/W) When set to a 1, the Host Controller proceeds with execution of the schedule. The Host Controller continues execution as long as this bit is set to a 1. When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts.
Page 730 NUC970 Technical Reference Manual USB Status Register (USTSR) Register Offset Description Reset Value USTSR EHCI_BA+0x024 USB Status Register 0x0000_1000 Reserved Reserved RECLA HCHalted Reserved Reserved HSERR UERRINT USBINT Bits Description Reserved [31:16] Reserved. Asynchronous Schedule Status (RO) The bit reports the current real status of the Asynchronous Schedule. If this bit is a zero then the status of them Asynchronous Schedule is disabled.
Page 731 NUC970 Technical Reference Manual Host System Error (R/WC) HSERR The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. Frame List Rollover (R/WC) The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero.
Page 732 NUC970 Technical Reference Manual USB Interrupt Enable Register (UIENR) Register Offset Description Reset Value UIENR EHCI_BA+0x028 USB Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved IAAEN HSERREN FLREN PCIEN UERRIEN USBIEN Bits Description Reserved [31:6] Reserved. Interrupt on Async Advance Enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a IAAEN one, the host controller will issue an interrupt at the next interrupt threshold.
Page 733 NUC970 Technical Reference Manual USB Frame Index Register (UFINDR) Register Offset Description Reset Value UFINDR EHCI_BA+0x02C USB Frame Index Register 0x0000_0000 Reserved Reserved Reserved Bits Description Reserved [31:14] Reserved. Frame Index The value in this register increment at the end of each time frame (e.g. micro-frame). Bits [N:3] are used for the Frame List current index.
Page 734 NUC970 Technical Reference Manual USB Periodic Frame List Base Address Register (UPFLBAR) Register Offset Description Reset Value UPFLBAR EHCI_BA+0x034 USB Periodic Frame List Base Address Register 0x0000_0000 BADDR BADDR BADDR Reserved Reserved Bits Description Base Address [31:12] BADDR These bits correspond to memory address signals [31:12], respectively. [11:0] Reserved Reserved.
Page 735 NUC970 Technical Reference Manual USB Current Asynchronous List Address Register (UCALAR) Register Offset Description Reset Value UCALAR EHCI_BA+0x038 USB Current Asynchronous List Address Register 0x0000_0000 Reserved Bits Description Link Pointer Low (LPL) [31:5] These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH).
Page 736 NUC970 Technical Reference Manual USB Asynchronous Schedule Sleep Timer Register (UASSTR) Register Offset Description Reset Value UASSTR EHCI_BA+0x03C R/W USB Asynchronous Schedule Sleep Timer Register 0x0000_0BD6 Reserved Reserved Reserved ASTMR ASTMR Bits Description Reserved [31:11] Reserved. Asynchronous Schedule Sleep Timer This field defines the AsyncSchedSleepTime of EHCI spec.
Page 737 NUC970 Technical Reference Manual USB Configure Flag Register (UCFGR) Register Offset Description Reset Value UCFGR EHCI_BA+0x060 USB Configure Flag Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description Reserved [31:1] Reserved. Configure Flag (CF) Host software sets this bit as the last action in its process of configuring the Host Controller.
Page 738 NUC970 Technical Reference Manual USB Port Status and Control Register (UPSCR) Register Offset Description Reset Value UPSCR0 EHCI_BA+0x064 USB Port 0 Status and Control Register 0x0000_2000 UPSCR1 EHCI_BA+0x068 USB Port 1 Status and Control Register 0x0000_2000 Reserved Reserved Reserved LSTS Reserved PRST SUSPEND...
Page 739 NUC970 Technical Reference Manual Line Status (RO) These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence.
Page 740 NUC970 Technical Reference Manual Suspend (R/W) Port Enabled Bit and Suspend bit of this register define the port states as follows:. 00 = Disable. 01 = Disable. 10 = Enable. 11 = Suspend. When in suspend state, downstream propagation of data is blocked on this port, except for port reset.
Page 741 NUC970 Technical Reference Manual Port Enable/Disable Change (R/WC) For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specifica- tion for the definition of a Port Error).
Page 742 NUC970 Technical Reference Manual USB PHY 0 Control Register (USBPCR0) Register Offset Description Reset Value USBPCR0 EHCI_BA+0x0C4 USB PHY 0 Control Register 0x0000_0060 Reserved Reserved Reserved CLKVALID Reserved SUSPEND Reserved Bits Description Reserved [31:12] Reserved. UTMI Clock Valid This bit is a flag to indicate if the UTMI clock from USB 2.0 PHY is ready. S/W program must prevent to write other control registers before this UTMI clock valid flag is active.
Page 743 NUC970 Technical Reference Manual USB PHY 1 Control Register (USBPCR1) Register Offset Description Reset Value USBPCR1 EHCI_BA+0x0C8 USB PHY 1 Control Register 0x0000_0020 Reserved Reserved Reserved SUSPEND Reserved Bits Description Reserved [31:9] Reserved. Suspend Assertion This bit controls the suspend mode of USB PHY 1. While PHY was suspended, all circuits of PHY were powered down and outputs are tristated.
Page 744 NUC970 Technical Reference Manual Host Controller Revision Register (HcRev) Register Offset Description Reset Value HcRev OHCI_BA+0x000 Host Controller Revision Register 0x0000_0010 Reserved Reserved Reserved Bits Description Reserved [31:8] Reserved. Revision Indicates the Open HCI Specification revision number implemented by the Hardware. Host [7:0] Controller supports 1.0 specification.
Page 745 NUC970 Technical Reference Manual Host Controller Control Register (HcControl) Register Offset Description Reset Value HcControl OHCI_BA+0x004 Host Controller Control Register 0x0000_0000 Reserved Reserved Reserved HCFS CBSR Bits Description Reserved [31:11] Reserved. Remote Wakeup Connected Enable [10] If a remote wakeup signal is supported, this bit enables that operation. Since there is no remote wakeup signal supported, this bit is ignored.
Page 746 NUC970 Technical Reference Manual Isochronous List Enable When clear, this bit disables the Isochronous List when the Periodic List is enabled (so Interrupt EDs may be serviced). While processing the Periodic List, the Host Controller will check this bit when it finds an isochronous ED. Periodic List Enable When set, this bit enables processing of the Periodic (interrupt and isochronous) list.
Page 747 NUC970 Technical Reference Manual Host Controller Command Status Register (HcComSts) Register Offset Description Reset Value HcComSts OHCI_BA+0x008 Host Controller Command Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description Reserved [31:18] Reserved. Schedule Overrun Count [17:16] This field is increment every time the SchedulingOverrun bit in HcInterruptStatus is set. The count wraps from ‘11’...
Page 748 NUC970 Technical Reference Manual Host Controller Interrupt Status Register (HcIntSts) Register Offset Description Reset Value HcIntSts OHCI_BA+0x00C Host Controller Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Reserved RHSC Bits Description Reserved [31] Reserved. Ownership Change [30] This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set. Reserved [29:7] Reserved.
Page 749 NUC970 Technical Reference Manual Host Controller Interrupt Enable Register (HcIntEn) Register Offset Description Reset Value HcIntEn OHCI_BA+0x010 Host Controller Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved RHSC Bits Description Master Interrupt Enable [31] This bit is a global interrupt enable. A write of ‘1’ allows interrupts to be enabled via the specific enable bits listed above.
Page 750 NUC970 Technical Reference Manual Scheduling Overrun Enable 0 = Ignore. 1 = Enables interrupt generation due to Scheduling Overrun. Publication Release Date: Dec. 15, 2015 - 750 - Revision V1.30...
Page 751 NUC970 Technical Reference Manual Host Controller Interrupt Disable Register (HcIntDis) Register Offset Description Reset Value HcIntDis OHCI_BA+0x014 Host Controller Interrupt Disable Register 0x0000_0000 Reserved Reserved Reserved Reserved RHSC Bits Description Master Interrupt Disable [31] Global interrupt disable. A write of ‘1’ disables all interrupts. Ownership Change Disable [30] 0 = Ignore.
Page 752 NUC970 Technical Reference Manual Scheduling Overrun Disable 0 = Ignore. 1 = Disables interrupt generation due to Scheduling Overrun. Publication Release Date: Dec. 15, 2015 - 752 - Revision V1.30...
Page 753 NUC970 Technical Reference Manual Host Controller Communication Area Register (HcHCCA) Register Offset Description Reset Value HcHCCA OHCI_BA+0x018 Host Controller Communication Area Register 0x0000_0000 HCCA HCCA HCCA Reserved Bits Description Host Controller Communication Area [31:7] HCCA Pointer to HCCA base address. [7:0] Reserved Reserved.
Page 754 NUC970 Technical Reference Manual Host Controller Period Current ED Register (HcPerCED) Register Offset Description Reset Value HcPerCED OHCI_BA+0x01C Host Controller Period Current ED Register 0x0000_0000 PCED PCED PCED PCED Reserved Bits Description Periodic Current ED [31:4] PCED Pointer to the current Periodic List ED. [3:0] Reserved Reserved.
Page 755 NUC970 Technical Reference Manual Host Controller Control Head ED Register (HcCtrHED) Register Offset Description Reset Value HcCtrHED OHCI_BA+0x020 Host Controller Control Head ED Register 0x0000_0000 CHED CHED CHED CHED Reserved Bits Description Control Head ED [31:4] CHED Pointer to the Control List Head ED. [3:0] Reserved Reserved.
Page 756 NUC970 Technical Reference Manual Host Controller Control Current ED Register (HcCtrCED) Register Offset Description Reset Value HcCtrCED OHCI_BA+0x024 Host Controller Control Current ED Register 0x0000_0000 CCED CCED CCED CCED Reserved Bits Description Control Current Head ED [31:4] CCED Pointer to the current Control List Head ED. [3:0] Reserved Reserved.
Page 757 NUC970 Technical Reference Manual Host Controller Bulk Head ED Register (HcBlkHED) Register Offset Description Reset Value HcBlkHED OHCI_BA+0x028 Host Controller Bulk Head ED Register 0x0000_0000 BHED BHED BHED BHED Reserved Bits Description Bulk Head ED [31:4] BHED Pointer to the Bulk List Head ED. [3:0] Reserved Reserved.
Page 758 NUC970 Technical Reference Manual Host Controller Bulk Current Head ED Register (HcBlkCED) Register Offset Description Reset Value HcBlkCED OHCI_BA+0x02C Host Controller Bulk Current ED Register 0x0000_0000 BCED BCED BCED BCED Reserved Bits Description Bulk Current Head ED [31:4] BCED Pointer to the current Bulk List Head ED. [3:0] Reserved Reserved.
Page 759 NUC970 Technical Reference Manual Host Controller Done Head Register (HcDoneH) Register Offset Description Reset Value HcDoneH OHCI_BA+0x030 Host Controller Done Head Register 0x0000_0000 Reserved Bits Description Done Head [31:4] Pointer to the current Done List Head ED. [3:0] Reserved Reserved. Publication Release Date: Dec.
Page 760 NUC970 Technical Reference Manual Host Controller Frame Interval Register (HcFmIntv) Register Offset Description Reset Value HcFmIntv OHCI_BA+0x034 Host Controller Frame Interval Register 0x0000_2EDF FSMPS FSMPS Reserved Bits Description Frame Interval Toggle [31] This bit is toggled by HCD when it loads a new value into FrameInterval. FS Largest Data Packet [30: 16] FSMPS...
Page 761 NUC970 Technical Reference Manual Host Controller Frame Remaining Register (HcFmRem) Register Offset Description Reset Value HcFmRem OHCI_BA+0x038 Host Controller Frame Remaining Register 0x0000_0000 Reserved Reserved Reserved Bits Description Frame Remaining Toggle [31] Loaded with FrameIntervalToggle when FrameRemaining is loaded. [30:14] Reserved Reserved.
Page 762 NUC970 Technical Reference Manual Host Controller Frame Number Register (HcFNum) Register Offset Description Reset Value HcFNum OHCI_BA+0x03C Host Controller Frame Number Register 0x0000_0000 Reserved Reserved Bits Description Reserved [31:16] Reserved. Frame Number [15:0] This 16-bit incrementing counter field is incremented coincident with the loading of FrameRemaining.
Page 763 NUC970 Technical Reference Manual Host Controller Periodic Start Register (HcPerSt) Register Offset Description Reset Value HcPerSt OHCI_BA+0x040 Host Controller Periodic Start Register 0x0000_0000 Reserved Reserved Reserved Bits Description Reserved [31:14] Reserved. Periodic Start [13:0] This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
Page 764 NUC970 Technical Reference Manual Host Controller Root Hub Descriptor A Register (HcRhDeA) Register Offset Description Reset Value HcRhDeA OHCI_BA+0x048 Host Controller Root Hub Descriptor A Register 0x0100_0002 POTPGT Reserved Reserved NOCP OCPM Bits Description Power on to Power Good Time This field value is represented as the number of 2 ms intervals, which ensuring that the power switching is effective within 2 ms.
Page 765 NUC970 Technical Reference Manual Power Switching Mode Global power switching mode implemented in HYDRA-2. This bit is only valid when NoPowerSwitching is cleared. This bit should be written '0'. 0 = Global Switching. 1 = Individual Switching. Number Downstream Ports [7:0] NUC970 supports two downstream ports.
Page 766 NUC970 Technical Reference Manual Host Controller Root Hub Descriptor B Register (HcRhDeB) Register Offset Description Reset Value HcRhDeB OHCI_BA+0x04C Host Controller Root Hub Descriptor B Register 0x0000_0000 PPCM PPCM DevRemove Bits Description Port Power Control Mask Global-power switching. This field is only valid if NoPowerSwitching is cleared and PowerSwitchingMode is set (individual port switching).
Page 767 NUC970 Technical Reference Manual Host Controller Root Hub Status Register (HcRhSts) Register Offset Description Reset Value HcRhSts OHCI_BA+0x050 Host Controller Root Hub Status Register 0x0000_0000 CRWE Reserved Reserved OCIC LPSC DRWE Reserved Reserved Bits Description Clear Remote Wakeup Enable [31] CRWE Writing a '1' to this bit clears DeviceRemoteWakeupEnable.
Page 768 NUC970 Technical Reference Manual Host Controller Root Hub Port Status (HcRhPrt [1: 2]) Register Offset Description Reset Value HcRhPrt1 OHCI_BA+0x054 Host Controller Root Hub Port Status [1] 0x0000_0000 HcRhPrt2 OHCI_BA+0x058 Host Controller Root Hub Port Status [2] 0x0000_0000 Reserved Reserved PRSC OCIC PSSC...
Page 769 NUC970 Technical Reference Manual (Read) LowSpeedDeviceAttached This bit defines the speed (and bud idle) of the attached device. It is only valid when CurrentConnectStatus is set. 0 = Full Speed device. LSDA 1 = Low Speed device. (Write) ClearPortPower Writing a '1' clears PortPowerStatus. Writing a '0' has no effect (Read) PortPowerStatus This bit reflects the power state of the port regardless of the power switching mode.
Page 770 NUC970 Technical Reference Manual USB Operational Mode Enable Register (OpModEn) Register Offset Description Reset Value OpModEn OHCI_BA+0x204 USB Operational Mode Enable Register 0X0000_0000 Reserved Reserved Reserved SIEPD Reserved OCAL Reserved ABORT DBR16 Bits Description Reserved [31:9] Reserved. SIE Pipeline Disable When set, waits for all USB bus activity to complete prior to returning completion status to SIEPD the List Processor.
Page 771: Controller Area Network (Can)
NUC970 Technical Reference Manual 5.24 Controller Area Network (CAN) 5.24.1 Overview The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and Module Interface (Refer to Figure 5.24-1) The CAN Core performs communication according to the CAN protocol version 2.0 part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to the physical layer, additional transceiver hardware is required.
Page 772: Block Diagram
NUC970 Technical Reference Manual 5.24.3 Block Diagram The C_CAN interfaces with the AMBA APB bus. The following figure shows the block diagram of the C_CAN.  CAN Core CAN Protocol Controller and Rx/Tx Shift Register for serial/parallel conversion of messages. ...
Page 773: Basic Configuration
NUC970 Technical Reference Manual 5.24.4 Basic Configuration Before using CAN functionality, it’s necessary to configure I/O pins as the CAN function and enable CAN’s clock. Write 0xC to MFP_GPB10 (SYS_GPB_MFPH[11:8]) and MFP_GPB11 (SYS_GPB_MFPH[15:12]) configures pin PB.10 and PB.11 to be CAN0_RX and CAN0_TX respectively. Write 0xC to MFP_GPH2 (SYS_GPH_MFPL[11:8]) and MFP_GPH3 (SYS_GPH_MFPL[15:12]) configures pin PH.2 and PH.3 to be CAN0_RX and CAN0_TX respectively.
Page 774: Test Mode
NUC970 Technical Reference Manual masked to “don’t care” may be overwritten in the Message Object. Software can read or write each message any time through the Interface Registers and the Message Handler guarantees data consistency in case of concurrent accesses. Messages to be transmitted are updated by the application software.
Page 775: Figure 5.24-2 Can Core In Silent Mode
NUC970 Technical Reference Manual monitors this dominant bit, although the CAN bus may remain in recessive state. The Silent Mode can be used to analysis the traffic on a CAN bus without affecting it by the transmission of dominant bits. The following figure shows the connection of signals CAN_TX and CAN_RX to the CAN Core in Silent Mode.
Page 776: Figure 5.24-4 Can Core In Loop Back Mode Combined With Silent Mode
NUC970 Technical Reference Manual of the combination of Loop Back Mode with Silent Mode. CAN_TX CAN_RX C_CAN CAN_Core Figure 5.24-4 CAN Core in Loop Back Mode Combined with Silent Mode 5.24.6.4 Basic Mode The CAN Core can be set in Basic Mode by programming the Test Register bit Basic to one. In this mode, the C_CAN runs without the Message RAM.
Page 777: Can Communications
NUC970 Technical Reference Manual Silent Mode, or Basic Mode) are selected. 5.24.7 CAN Communications 5.24.7.1 Managing Message Objects The configuration of the Message Objects in the Message RAM (with the exception of the bits MsgVal, NewDat, IntPnd, and TxRqst) will not be affected by resetting the chip. All the Message Objects must be initialized by the application software or they must be “not valid”...
Page 778 NUC970 Technical Reference Manual Message RAM. Therefore, the data transfer from the IFn Registers to the Message RAM requires a read-modify-write cycle. First, those parts of the Message Object that are not to be changed are read from the Message RAM and then the complete contents of the Message Buffer Registers are written into the Message Object.
Page 779: Figure 5.24-5 Data Transfer Between Ifn Registers And Message
NUC970 Technical Reference Manual START Write Command Request Register Busy = 1 WR/RD = 1 Read Message Object to IFn Read Message Object to IFn Write IFn to Message RAM Busy = 0 Figure 5.24-5 Data transfer between IFn Registers and Message After a partial write of a Message Object, the Message Buffer Registers that are not selected in the Command Mask Register will set the actual contents of the selected Message Object.
Page 780 NUC970 Technical Reference Manual After a successful transmission and also if no new data was written to the Message Object (NewDat = ‘0’) since the start of the transmission, the TxRqst bit of the Message Control register (CAN_IFn_MCR) will be reset. If TxIE bit of the Message Control register (CAN_IFn_MCR) is set, IntPnd bit of the Interrupt Identifier register will be set after a successful transmission.
Page 781: Table 5.24-1 Initialization Of A Transmit Object
NUC970 Technical Reference Manual arbitration and control field (Identifier + IDE + RTR + DLC) from the shift register is stored in the Message Object of the Message RAM and the NewDat bit of this Message Object is set. The data field of the Message Object remains unchanged;...
Page 782: Table 5.24-2 Initialization Of A Receive Object
NUC970 Technical Reference Manual To prevent the reset of TxRqst at the end of a transmission that may already be in progress while the data is updated, NewDat has to be set together with TxRqst. When NewDat is set together with TxRqst, NewDat will be reset as soon as the new transmission has started.
Page 783 NUC970 Technical Reference Manual receive object. Setting the TxRqst bit of a receive object will cause the transmission of a Remote Frame with the receive object’s identifier. This Remote Frame triggers the other CAN node to start the transmission of the matching Data Frame. If the matching Data Frame is received before the Remote Frame could be transmitted, the TxRqst bit is automatically reset.
Page 784: Figure 5.24-6 Application Software Handling Of A Fifo Buffer
NUC970 Technical Reference Manual START Read Interrupt Pointer Case Interrupt Pointer 0x8000 else 0x0000 Status Change Interrupt Handing Message Num = Interrupt Pointer Write Message Num to IFn Command Register (Read Message to IFn Registers, Reset NewDat = 0, Reset IntPnd = 0) Read IFn to Message Control NewDat = 1 Read Data from IFn Data A, B...
Page 785 NUC970 Technical Reference Manual application software has cleared it. The Status Interrupt has the highest priority. Among the message interrupts, interrupt priority of the Message Object decreases with increasing message number. A message interrupt is cleared by clearing the IntPnd bit of the Message Object. The Status Interrupt is cleared by reading the Status Register.
Page 786: Figure 5.24-7 Bit Timing
NUC970 Technical Reference Manual According to the CAN specification, the bit time is divided into four segments (see the following figure). The Synchronization Segment, the Propagation Time Segment, the Phase Buffer Segment 1 and the Phase Buffer Segment 2. Each segment consists of a specific, programmable number of time quanta (see Table 5.24-3).
Page 787: Figure 5.24-8 Propagation Time Segment
NUC970 Technical Reference Manual messages requires that a CAN node transmitting a bit stream must also be able to receive dominant bits transmitted by other CAN nodes that are synchronized to that bit stream. The example in the following figure shows the phase shift and propagation times between two CAN nodes. Prop_Seg Sync_Seg Prop_Seg...
Page 788 NUC970 Technical Reference Manual Synchronizations occur on edges from recessive to dominant, their purpose is to control the distance between edges and Sample Points. Edges are detected by sampling the actual bus level in each time quantum and comparing it with the bus level at the previous Sample Point.
Page 789: Figure 5.24-9 Synchronization On "Late" And "Early" Edges
NUC970 Technical Reference Manual shows the synchronization on a “late” edge, the lower drawing shows the synchronization on an “early” edge, and the middle drawing is the reference without synchronization. recessive dominant Rx-Input Sample-Point Sample-Point Sample-Point Sample-Point Sample-Point Sample-Point recessive “early Edge Rx-Input dominant...
Page 790: Figure 5.24-10 Filtering Of Short Dominant Spikes
NUC970 Technical Reference Manual enough; the dominant spike is sampled as actual bus level. recessive dominant Rx-Input Spike Sample-Point Sample-Point SJW >= Phase Error recessive dominant Rx-Input Spike Sample-Point Sample-Point SJW < Phase Error Sync_Seg Prop_Seg Phase_Seg Prop_Seg Figure 5.24-10 Filtering of Short Dominant Spikes 5.24.7.19 Oscillator Tolerance Range The oscillator tolerance range was increased when the CAN protocol was developed from version 1.1...
Page 791: Figure 5.24-11 Structure Of The Can Core's Can Protocol Controller
NUC970 Technical Reference Manual and that the Propagation Time Segment limits that part of the bit time that may be used for the Phase Buffer Segments. The combination Prop_Seg = 1 and Phase_Seg1 = Phase_Seg2 = SJW = 4 allows the largest possible oscillator tolerance of 1.58%.
Page 792 NUC970 Technical Reference Manual each time quantum. The rest of the CAN protocol controller, the BSP (Bit Stream Processor) state machine is evaluated once each bit time, at the Sample Point. The Shift Register sends the messages serially and parallelizes received messages. It’s loading and shifting is controlled by the BSP.
Page 793 NUC970 Technical Reference Manual Example for Bit Timing at High Baud Rate In this example, the frequency of APB_CLK is 10 MHz, BRP is 0, the bit rate is 1 MBit/s. 100 ns APB_CLK delay of bus driver delay of receiver circuit delay of bus line (40m) = 6 •...
Page 794 NUC970 Technical Reference Manual Example for Bit Timing at Low Baud Rate In this example, the frequency of APB_CLK is 2 MHz, BRP is 1, the bit rate is 100 Kbit/s. s = 2 •t APB_CLK delay of bus driver 200 ns delay of receiver circuit 80 ns...
Page 795: Register Map
NUC970 Technical Reference Manual 5.24.8 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CAN Base Address: CAN0_BA = 0xB800_0000 CAN1_BA = 0xB800_4000 CAN_CON CANx_BA+0x00 Control Register 0x0000_0001 CAN_STATUS CANx_BA+0x04 Status Register 0x0000_0000 CAN_ERR CANx_BA+0x08...
Page 796 NUC970 Technical Reference Manual CAN_MVLD1 CANx_BA+0x160 Message Valid Registers 1 & 2 0x0000_0000 CAN_MVLD2 CANx_BA+0x164 CAN_WU_EN CANx_BA+0x168 Wake-up Function Enable 0x0000_0000 CAN_WU_STATUS CANx_BA+0x16C Wake-up Function Status 0x0000_0000 Note: 1. 0x00 & 0br0000000, where r signifies the actual value of the CAN_RX 2.
Page 797 NUC970 Technical Reference Manual Register Map. Additionally the busoff state is reset and the output CAN_TX is set to recessive (HIGH). The value 0x0001 (Init = ‘1’) in the CAN Control Register enables the software initialization. The C_CAN does not influence the CAN bus until the application software resets the Init bit to ‘0’.
Page 798 NUC970 Technical Reference Manual CAN Register Map for Each Bit Function Addr Register Offset Name CAN_CON Reserved Init CAN_STATUS Reserved CAN_ERR REC6-0 TEC7-0 CAN_BTIME Res TSeg2 TSeg1 CAN_IIDR IntId15-8 IntId7-0 CAN_TEST Reserved Reserved CAN_BRPE Reserved BRPE CAN_IF1_CRE Busy Reserved Message Number CAN_IF1_CMA Reserved CAN_IF1_MAS...
Page 799 NUC970 Technical Reference Manual Addr Register Name Offset CAN_IF1_MCO Reserved DLC3-0 CAN_IF1_DAT_ Data(1) Data(0) CAN_IF1_DAT_ Data(3) Data(2) CAN_IF1_DAT_ Data(5) Data(4) CAN_IF1_DAT_ Data(7) Data(6) CAN_IF2_CREQ Busy Reserved Message Number CAN_IF2_CMAS Reserved CAN_IF2_MASK Msk15-0 CAN_IF2_MASK MXtd MDir Res. Msk28-16 CAN_IF2_ARB1 ID15-0 CAN_IF2_ARB2 ID28-16 CAN_IF2_MCO Reserved...
Page 800: Table 5.24-4 Can Register Map For Each Bit Function
NUC970 Technical Reference Manual Addr Register Name 15 Offset CAN_IF2_DAT_ Data(3) Data(2) CAN_IF2_DAT_ Data(5) Data(4) CAN_IF2_DAT_ Data(7) Data(6) 100h CAN_TXREQ1 TxRqst16-1 104h CAN_TXREQ2 TxRqst32-17 120h CAN_NDAT1 NewDat16-1 124h CAN_NDAT2 NewDat32-17 140h CAN_IPND1 IntPnd16-1 144h CAN_IPND2 IntPnd32-17 160h CAN_MVLD1 MsgVal16-1 164h CAN_MVLD2 MsgVal32-17 WAKUP...
Page 801: Register Description
NUC970 Technical Reference Manual 5.24.9 Register Description The C_CAN allocates an address space of 256 bytes. The registers are organized as 16-bit registers. The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM. They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission.
Page 802 NUC970 Technical Reference Manual CAN Control Register (CAN_CON) Register Offset Description Reset Value CAN_CON CANx_BA+0x00 CAN Control Register 0x0000_0000 Reserved Reserved Reserved Test Reserved Init Bits Description Reserved [31:8] Reserved. Test Mode Enable Control Test 0 = Normal Operation. 1 = Test Mode. Configuration Change Enable Control 0 = No write access to the Bit Timing Register.
Page 803 NUC970 Technical Reference Manual 1 = Initialization is started. Note: The busoff recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or resetting the Init bit. If the device goes in the busoff state, it will set Init of its own accord, stopping all bus activities.
Page 804 NUC970 Technical Reference Manual CAN Status Register (CAN_STATUS) Register Offset Description Reset Value CAN_STATUS CANx_BA+0x04 CAN Status Register 0x0000_0000 Reserved Reserved Reserved BOFF EWarn EPass RxOK TxOK Bits Description Reserved [31:8] Reserved. Bus-off Status (Read Only) BOff 0 = The CAN module is not in bus-off state. 1 = The CAN module is in bus-off state.
Page 805: Table 5.24-5 Error Code
NUC970 Technical Reference Manual Error Code Meanings No Error Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. Form Error: A fixed format part of a received frame has the wrong format. AckError: The message this CAN Core transmitted was not acknowledged by another node.
Page 806 NUC970 Technical Reference Manual CAN Error Counter Register (CAN_ERR) Register Offset Description Reset Value CAN_ERR CANx_BA+0x08 Error Counter Register 0x0000_0000 Reserved Reserved REC[6:0] TEC[7:0] Bits Description Reserved [31:16] Reserved. Receive Error Passive 0 = The Receive Error Counter is below the error passive level. [15] 1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
Page 807 NUC970 Technical Reference Manual Bit Timing Register (CAN_BTIME) Register Offset Description Reset Value CAN_BTIME CANx_BA+0x0C Bit Timing Register 0x0000_2301 Reserved Reserved Reserved TSeg2 TSeg1 Bits Description Reserved [31:15] Reserved. Time Segment After Sample Point [14:12] TSeg2 0x0-0x7: Valid values for TSeg2 are [0 … 7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
Page 808: Table 5.24-6 Source Of Interrupts
NUC970 Technical Reference Manual Interrupt Identify Register (CAN_IIDR) Register Offset Description Reset Value CAN_IIDR CANx_BA+0x10 Interrupt Identifier Registers 0x0000_0000 Reserved Reserved IntId[15:8] IntId[7:0] Bits Description Interrupt Identifier (Indicates the Source of the Interrupt) If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
Page 809 NUC970 Technical Reference Manual Test Register (CAN_TEST) Register Offset Description Reset Value CAN_TEST CANx_BA+0x14 Test Register 0x0000_00x0 Reserved Reserved Reserved Tx[1:0] LBack Silent Basic Bits Description Reserved [31:8] Reserved. Monitors the Actual Value of CAN_RX Pin (Read Only) 0 = The CAN bus is dominant (CAN_RX = ‘0’). 1 = The CAN bus is recessive (CAN_RX = ‘1’).
Page 810 NUC970 Technical Reference Manual Baud Rate Prescaler Extension REGISTER (CAN_BRPE) Register Offset Description Reset Value CAN_BRPE CANx_BA+0x18 Baud Rate Prescaler Extension Register 0x0000_0000 Reserved Reserved Reserved Reserved BRPE Bits Description Reserved [31:4] Reserved. BRPE: Baud Rate Prescaler Extension 0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to [3:0] BRPE 1023.
Page 811: Table 5.24-7 If1 And If2 Message Interface Register
NUC970 Technical Reference Manual Message Interface Register Sets There are two sets of Interface Registers, which are used to control the CPU access to the Message RAM. The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception and transmission by buffering the data to be transferred.
Page 812 NUC970 Technical Reference Manual IFn Command Request Register (CAN_IFn_CREQ) Register Offset Description Reset Value CAN_IFn_CREQ CANx_BA+0x20/0x80 R/W IFn Command Request Register 0x0000_0001 Reserved Reserved Busy Message Number Bits Description Busy Flag 0 = Read/write action has finished. [15] Busy 1 = Writing to the IFn Command Request Register is in progress. This bit can only be read by the software.
Page 813 NUC970 Technical Reference Manual IFn Command Mask Register (CAN_IFn_CMASK) The control bits of the IFn Command Mask Register specify the transfer direction and select which of the IFn Message Buffer Registers are source or target of the data transfer. Register Offset Description Reset Value...
Page 814 NUC970 Technical Reference Manual 1 = Transfer Control Bits to Message Object. Direction = Read. 0 = Control Bits unchanged. 1 = Transfer Control Bits to IFn Message Buffer Register. Clear Interrupt Pending Bit Direction = Write. When writing to a Message Object, this bit is ignored. ClrIntPnd Direction = Read.
Page 815 NUC970 Technical Reference Manual IFn Mask 1 Register (CAN_IFn_MASK1) Register Offset Description Reset Value CAN_IFn_MASK1 CANx_BA+0x28/0x88 R/W IFn Mask 1 Registers 0x0000_FFFF Reserved Reserved Msk[15:8] Msk[7:0] Bits Description Reserved [31:16] Reserved. Identifier Mask 15-0 0 = The corresponding bit in the identifier of the message object cannot inhibit the match in Msk[15:0] [15:0] the acceptance filtering.
Page 816 NUC970 Technical Reference Manual IFn Mask 2 Register (CAN_IFn_MASK2) Register Offset Description Reset Value CAN_IFn_MASK2 CANx_BA+0x2C/0x8C R/W IFn Mask 2 Registers 0x0000_FFFF Reserved Reserved MXtd MDir Reserved Msk[28:24] Msk[23:16] Bits Description Reserved [31:16] Reserved. Mask Extended Identifier 0 = The extended identifier bit (IDE) has no effect on the acceptance filtering. 1 = The extended identifier bit (IDE) is used for acceptance filtering.
Page 817 NUC970 Technical Reference Manual IFn Arbitration 1 Register (CAN_IFn_ARB1) Register Offset Description Reset Value CAN_IFn_ARB1 CANx_BA+0x30/0x90 R/W IFn Arbitration 1 Register 0x0000_0000 Reserved Reserved ID[15:8] ID[7:0] Bits Description Reserved [31:16] Reserved. Message Identifier 15-0 ID28 - ID0, 29-bit Identifier (“Extended Frame”). [15:0] ID[15:0] ID28 - ID18, 11-bit Identifier (“Standard Frame”)
Page 818 NUC970 Technical Reference Manual IFn Arbitration 2 Register (CAN_IFn_ARB2) Register Offset Description Reset Value CAN_IFn_ARB2 CANx_BA+0x34/0x94 R/W IFn Arbitration Register 0x0000_0000 Reserved Reserved MsgVal ID[28:24] ID[23:16] Bits Description Reserved [31:16] Reserved. Message Valid 0 = The Message Object is ignored by the Message Handler. 1 = The Message Object is configured and should be considered by the Message Handler.
Page 819 NUC970 Technical Reference Manual IFn Message Control Register (CAN_IFn_MCON) Register Offset Description Reset Value CAN_IFn_MCON CANx_BA+0x38/0x98 R/W IFn Message Control Register 0x0000_0000 Reserved Reserved NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst Reserved DLC[3:0] Bits Description [31:16] Reserved Reserved. New Data 0 = No new data has been written into the data portion of this Message Object by the Message [15] NewDat...
Page 820 NUC970 Technical Reference Manual 0 = At the reception of a Remote Frame, TxRqst is left unchanged. 1 = At the reception of a Remote Frame, TxRqst is set. Transmit Request TxRqst 0 = This Message Object is not waiting for transmission. 1 = The transmission of this Message Object is requested and is not yet done.
Page 821 NUC970 Technical Reference Manual IFn Data A1 Register (CAN_IFn_DAT_A1) Register Offset Description Reset Value CAN_IFn_DAT_A1 CANx_BA+0x3C/0x9C R/W IFn Data A1 Registers 0x0000_0000 Reserved Reserved Data(1) Data(0) Bits Description [31:16] Reserved Reserved. Data Byte 1 [15:8] Data (1) 2nd data byte of a CAN Data Frame Data Byte 0 [7:0] Data (0)
Page 822 NUC970 Technical Reference Manual IFn Data A2 Register (CAN_IFn_DAT_A2) Register Offset Description Reset Value CAN_IFn_DAT_A2 CANx_BA+0x40/0xA0 R/W IFn Data A2 Registers 0x0000_0000 Reserved Reserved Data(3) Data(2) Bits Description Reserved [31:16] Reserved. Data Byte 3 [15:8] Data (3) 4th data byte of CAN Data Frame Data Byte 2 [7:0] Data (2)
Page 823 NUC970 Technical Reference Manual IFn Data B1 Register (CAN_IFn_DAT_B1) Register Offset Description Reset Value CAN_IFn_DAT_B1 CANx_BA+0x44/0xA4 R/W IFn Data B1 Registers 0x0000_0000 Reserved Reserved Data(5) Data(4) Bits Description Reserved [31:16] Reserved. Data Byte 5 [15:8] Data (5) 6th data byte of CAN Data Frame Data Byte 4 [7:0] Data (4)
Page 824 NUC970 Technical Reference Manual IFn Data B2 Register (CAN_IFn_DAT_B2) Register Offset Description Reset Value CAN_IFn_DAT_B2 CANx_BA+0x48/0xA8 R/W IFn Data B2 Registers 0x0000_0000 Reserved Reserved Data(7) Data(6) Bits Description Reserved [31:16] Reserved. Data Byte 7 [15:8] Data (7) 8th data byte of CAN Data Frame. Data Byte 6 [7:0] Data (6)
Page 825: Table 5.24-8 Structure Of A Message Object In The Message Memory
NUC970 Technical Reference Manual Message Object in the Message Memory There are 32 Message Objects in the Message RAM. To avoid conflicts between application software access to the Message RAM and CAN message reception and transmission, the CPU cannot directly access the Message Objects, these accesses are handled through the IFn Interface Registers.
Page 826 NUC970 Technical Reference Manual Transmission Request Register 1 (CAN_TXREQ1) These registers hold the TxRqst bits of the 32 Message Objects. By reading the TxRqst bits, the software can check which Message Object in a Transmission Request is pending. The TxRqst bit of a specific Message Object can be set/reset by the application software through the IFn Message Interface Registers or by the Message Handler after reception of a Remote Frame or after a successful transmission.
Page 827 NUC970 Technical Reference Manual Transmission Request Register 2 (CAN_TXREQ2) Register Offset Description Reset Value CAN_TXREQ2 CANx_BA+0x104 R Transmission Request Register 2 0x0000_0000 Reserved Reserved TxRqst32-25 TxRqst24-17 Bits Description Reserved [31:16] Reserved. Transmission Request Bits 32-17 (of All Message Objects) 0 = This Message Object is not waiting for transmission. TxRqst 32-17 [15:0] 1 = The transmission of this Message Object is requested and is not yet done.
Page 828 NUC970 Technical Reference Manual New Data Register 1 (CAN_NDAT1) These registers hold the NewDat bits of the 32 Message Objects. By reading out the NewDat bits, the software can check for which Message Object the data portion was updated. The NewDat bit of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers or by the Message Handler after reception of a Data Frame or after a successful transmission.
Page 829 NUC970 Technical Reference Manual New Data Register 2 (CAN_NDAT2) Register Offset Description Reset Value CAN_NDAT2 CANx_BA+0x124 R New Data Register 2 0x0000_0000 Reserved Reserved NewData 32-25 NewData 24-17 Bits Description Reserved [31:16] Reserved. New Data Bits 32-17 (of All Message Objects) 0 = No new data has been written into the data portion of this Message Object by the NewData 32-17 [15:0]...
Page 830 NUC970 Technical Reference Manual Interrupt Pending Register 1 (CAN_IPND1) These registers contain the IntPnd bits of the 32 Message Objects. By reading the IntPnd bits, the software can check for which Message Object an interrupt is pending. The IntPnd bit of a specific Message Object can be set/reset by the application software through the IFn Message Interface Registers or by the Message Handler after reception or after a successful transmission of a frame.
Page 831 NUC970 Technical Reference Manual Interrupt Pending Register 2 (CAN_IPND2) Register Offset Description Reset Value CAN_IPND2 CANx_BA+0x144 R Interrupt Pending Register 2 0x0000_0000 Reserved Reserved IntPnd 32-25 IntPnd 24-17 Bits Description Reserved [31:16] Reserved. Interrupt Pending Bits 32-17(of All Message Objects) [15:0] IntPnd 32-17 0 = This message object is not the source of an interrupt.
Page 832 NUC970 Technical Reference Manual Message Valid Register 1 (CAN_MVLD1) These registers hold the MsgVal bits of the 32 Message Objects. By reading the MsgVal bits, the application software can check which Message Object is valid. The MsgVal bit of a specific Message Object can be set/reset by the application software via the IFn Message Interface Registers.
Page 833 NUC970 Technical Reference Manual Message Valid Register 2 (CAN_MVLD2) Register Offset Description Reset Value CAN_MVLD2 CANx_BA+0x164 R Message Valid Register 2 0x0000_0000 Reserved Reserved MsgVal 32-25 MsgVal 24-17 Bits Description Reserved [31:16] Reserved. Message Valid Bits 32-17 (of All Message Objects) (Read Only) 0 = This Message Object is ignored by the Message Handler.
Page 834 NUC970 Technical Reference Manual Wake-up Enable Control Register (CAN_WU_EN) Register Offset Description Reset Value CAN_WU_EN CANx_BA+0x168 R/W Wake-up Enable Control Register 0x0000_0000 Reserved Reserved Reserved Reserved WAKUP_EN Bits Description Reserved [31:1] Reserved. Wake-up Enable Control 0 = The wake-up function is disable. WAKUP_EN 1 = The wake-up function is enable.
Page 835 NUC970 Technical Reference Manual Wake-up Status Register (CAN_WU_STATUS) Register Offset Description Reset Value CAN_WU_STATUS CANx_BA+0x16C R/W Wake-up Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WAKUP_STS Bits Description Reserved [31:1] Reserved. Wake-up Status 0 = No wake-up event is occurred. WAKUP_STS 1 = Wake-up event is occurred.
Page 836: Flash Memory Interface (Fmi)
NUC970 Technical Reference Manual 5.25 Flash Memory Interface (FMI) 5.25.1 Overview The Flash Memory Interface (FMI) of this Chip has DMA unit and FMI unit. The DMA unit provides a DMA (Direct Memory Access) function for FMI to exchange data between system memory (ex. SDRAM) and shared buffer (128 bytes), and the FMI unit control the interface of eMMC or NAND flash.
Page 837: Block Diagram
NUC970 Technical Reference Manual 5.25.3 Block Diagram NAND_nCS0 Control, Status Register NAND_nWP NAND_ALE NAND_CLE NAND Flash Controller NAND_nWE NAND_nRE Interface NAND_RDY Unit NAND_DATA[7:0] FIFO Controller eMMC_CLK eMMC eMMC_CMD Controller eMMC_DATA[7:0] Figure 5.25-1 FMI Block Diagram 5.25.4 Basic Configuration Before using Flash Memory Interface, it’s necessary to configure related pins as the NAND/eMMC function and enable FMI’s clock.
Page 838: Functional Description
NUC970 Technical Reference Manual Set DMACEN (FMI_DMACTL[0]) to enable DMAC and SG_EN (FMI_DMACTL[3]) to enable Scatter-Gather function. Fill corresponding starting address of Physical Address Descriptor (PAD) table in FMI_DMASA for FMI. When bit-0 of FMI_DMASA is 1, the PAD will fetch in out of order, otherwise, it’s fetched in order from PAD.
Page 839 NUC970 Technical Reference Manual This eMMC controller is composed of two state machines – command/response part and data part. command/response part, trigger bits CO_EN (FMI_EMMCCTL[0]), RI_EN (FMI_EMMCCTL[1]), R2_EN (FMI_EMMCCTL[4]), CLK74_OE (FMI_EMMCCTL[5]) and CLK8_OE (FMI_EMMCCTL[6]). If all of these bits enabled by software, the execution priority will be CLK74_OE (FMI_EMMCCTL[5]), CO_EN (FMI_EMMCCTL[0]),...
Page 840: Table 5.25-1 Number Of Parity (Byte) For Each Bch Algorithm
NUC970 Technical Reference Manual address port without setting EOA (FMI_NANDADDR[31])] high, and then write the last one address to address port with setting EOA (FMI_NANDADDR[31])] high. NAND flash controller also provides a status and an interrupt flag of NAND_RDY pin. The interrupt flag will be set only when rising edge encountered on NAND_RDY pin.
Page 841: Figure 5.25-2 Data Arrangement For 2 Kb Page Size Nand Flash
NUC970 Technical Reference Manual Redundant Area FMI_NANDRA0 Data Area (2048 Bytes) Redundant Data Redundant Area (64 Bytes) Parity Data FMI_NANDRA15 Figure 5.25-2 Data Arrangement for 2 kB Page Size NAND Flash Redundant Area FMI_NANDRA0 Data Area (4096 Bytes) Redundant Data Redundant Area (Defined by FMI_NANDRACTL)
Page 842: Figure 5.25-4 Data Arrangement For 8 Kb Page Size Nand Flash
NUC970 Technical Reference Manual Redundant Area FMI_NANDRA0 Data Area (8192 Bytes) Redundant Data Redundant Area (Defined by FMI_NANDRACTL) Parity Data FMI_NANDRAx Figure 5.25-4 Data Arrangement for 8 kB Page Size NAND Flash Publication Release Date: Dec. 15, 2015 - 842 - Revision V1.30...
Page 843: Register Map
NUC970 Technical Reference Manual 5.25.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value FMI Base Address: FMI_BA = 0xB000_D000 FMI_BUFFERn FMI Embedded Buffer Word n FMI_BA+0x000+0x4*n R/W 0x0000_0000 n = 0, 1..31 N = 0, 1..31 FMI_DMACTL FMI_BA+0x400...
Page 844 NUC970 Technical Reference Manual FMI_NANDECCE FMI_BA+0x8D0 NAND Flash ECC Error Status 0 Register 0x0000_0000 FMI_NANDECCE FMI_BA+0x8D4 NAND Flash ECC Error Status 1 Register 0x0000_0000 FMI_NANDECCE FMI_BA+0x8D8 NAND Flash ECC Error Status 2 Register 0x0000_0000 FMI_NANDECCE FMI_BA+0x8DC NAND Flash ECC Error Status 3 Register 0x0000_0000 FMI_NANDPROT FMI_BA+0x8E0...
Page 845 NUC970 Technical Reference Manual FMI_NANDECCE FMI_BA+0x974 NAND Flash ECC Error Data Register 5 0x8080_8080 FMI_NANDRAn NAND Flash Redundant Area Word n FMI_BA+0xA00+0x4* Undefined n = 0, 1..117 n = 0, 1..117 Publication Release Date: Dec. 15, 2015 - 845 - Revision V1.30...
Page 846: Register Description
NUC970 Technical Reference Manual 5.25.7 Register Description Publication Release Date: Dec. 15, 2015 - 846 - Revision V1.30...
Page 847 NUC970 Technical Reference Manual FMI DMA Control Register (FMI_DMACTL) Register Offset Description Reset Value FMI_DMACTL FMI_BA+0x400 FMI DMA Control Register 0x0000_0000 Reserved Reserved Reserved FMI_BUSY Reserved Reserved SG_EN Reserved SW_RST DMACEN Bits Description [31:10] Reserved Reserved. FMI DMA Transfer Is in Progress This bit indicates if FMI is granted and doing DMA transfer or not.
Page 848: Figure 5.25-5 Pad (Physical Address Descriptor) Table Format
NUC970 Technical Reference Manual FMI DMA Transfer Starting Address Register (FMI_DMASA) Register Offset Description Reset Value FMI_DMASA FMI_BA+0x408 FMI DMA Transfer Starting Address Register 0x0000_0000 ADDR ADDR ADDR ADDR ADDR/ORDER Bits Description DMA Transfer Starting Address This field indicates a 32-bit starting address of system memory (SRAM/SDRAM) for DMAC [31:0] ADDR to retrieve or fill in data (for FMI engine).
Page 849: Figure 5.25-6 Pad (Physical Address Descriptor) Table Fetch Modes
NUC970 Technical Reference Manual The diagram shown below indicates how FMI feteched the PAD tables. FMI feteched next PAD tables sequentially if ORDER (FMI_DMASA[0]) set as low. FMI fetehced next PAD tables based on the Next Descriptor Physical Base Address of PAD table if ORDER (FMI_DMASA[0]) set as high. System Memory (ORDER = 0) System Memory (ORDER = 1) PAD Table #1...
Page 850 NUC970 Technical Reference Manual FMI DMA Transfer Byte Count Register (FMI_DMABCNT) Register Offset Description Reset Value FMI_DMABCNT FMI_BA+0x40C FMI DMA Transfer Byte Count Register 0x0000_0000 Reserved BCNT BCNT BCNT BCNT Bits Description Reserved [31:26] Reserved. DMA Transfer Byte Count (Read Only) [25:0] BCNT This field indicates the remained byte count of DMAC transfer.
Page 851 NUC970 Technical Reference Manual FMI DMA Interrupt Enable Register (FMI_DMAINTEN) Register Offset Description Reset Value FMI_DMAINTEN FMI_BA+0x410 FMI DMA Interrupt Enable Register 0x0000_0001 Reserved Reserved Reserved Reserved WEOT_IE TABORT_IE Bits Description Reserved [31:2] Reserved. Wrong EOT Encountered Interrupt Enable WEOT_IE 0 = Disable interrupt generation when wrong EOT is encountered.
Page 852 NUC970 Technical Reference Manual FMI DMA Interrupt Status Register (FMI_DMAINTSTS) Register Offset Description Reset Value FMI_DMAINTSTS FMI_BA+0x414 FMI DMA Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WEOT_IF TABORT_IF Bits Description Reserved [31:2] Reserved. Wrong EOT Encountered Interrupt Flag When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of FMI), this bit will be set.
Page 853 NUC970 Technical Reference Manual FMI Control Register (FMI_CTL) Register Offset Description Reset Value FMI_CTL FMI_BA+0x800 FMI Control Register 0x0000_0000 Reserved Reserved Reserved Reserved NAND_EN Reserved eMMC_EN SW_RST Bits Description Reserved [31:4] Reserved. NAND Flash Functionality Enable NAND_EN 0 = Disable NAND flash functionality of FMI. 1 = Enable NAND flash functionality of FMI.
Page 854 NUC970 Technical Reference Manual FMI Interrupt Enable Register (FMI_INTEN) Register Offset Description Reset Value FMI_INTEN FMI_BA+0x804 FMI Interrupt Enable Register 0x0000_0001 Reserved Reserved Reserved Reserved DTA_IE Bits Description Reserved [31:1] Reserved. DMAC READ/WRITE Target Abort Interrupt Enable DTA_IE 0 = Disable DMAC READ/WRITE target abort interrupt generation. 1 = Enable DMAC READ/WRITE target abort interrupt generation.
Page 855 NUC970 Technical Reference Manual FMI Interrupt Status Register (FMI_INTSTS) Register Offset Description Reset Value FMI_INTSTS FMI_BA+0x808 FMI Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved DTA_IF Bits Description Reserved [31:1] Reserved. DMAC READ/WRITE Target Abort Interrupt Flag (Read Only) This bit indicates DMAC received an ERROR response from internal AHB bus during DMA read/write operation.
Page 856 NUC970 Technical Reference Manual eMMC Control Register (FMI_EMMCCTL) Register Offset Description Reset Value FMI_EMMCCTL FMI_BA+0x820 eMMC Control Register 0x0101_0000 Reserved BLK_CNT SW_RST CMD_CODE Reserved CLK8_OE CLK74_OE R2_EN DO_EN DI_EN RI_EN CO_EN Bits Description [31] Reserved Reserved. Reserved [30:29] Reserved. [28] Reserved Reserved.
Page 857 NUC970 Technical Reference Manual Generating 8 Clock Cycles Output Enable 0 = No effect. (Please use SW_RST(FMI_EMMCCTL[14]) to clear this bit.) CLK8_OE 1 = Enable, eMMC host will output 8 clock cycles. NOTE: When operation is finished, this bit will be cleared automatically, so don’t write 0 to this bit (the controller will be abnormal).
Page 858 NUC970 Technical Reference Manual eMMC Command Argument Register (FMI_EMMCCMD) Register Offset Description Reset Value FMI_EMMCC FMI_BA+0x824 eMMC Command Argument Register 0x0000_0000 CMDARG CMDARG CMDARG CMDARG Bits Description eMMC Command Argument This register contains a 32-bit value specifies the argument of eMMC command from host [31:0] CMDARG controller to eMMC device.
Page 859 NUC970 Technical Reference Manual eMMC Interrupt Enable Register (FMI_EMMCINTEN) Register Offset Description Reset Value FMI_EMMCIN FMI_BA+0x828 eMMC Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved DITO_IE RITO_IE Reserved Reserved CRC_IE BLKD_IE Bits Description [31:14] Reserved Reserved. Data Input Time-out Interrupt Enable Enable/Disable interrupts generation of eMMC controller when data input time-out.
Page 860 NUC970 Technical Reference Manual eMMC Interrupt Status Register (FMI_EMMCINTSTS) Register Offset Description Reset Value FMI_EMMCIN FMI_BA+0x82C eMMC Interrupt Status Register 0x00XX_008C TSTS Reserved Reserved Reserved DITO_IF RITO_IF Reserved DAT0 CRCSTAT CRC16 CRC7 CRC_IF BLKD_IF Bits Description [31:14] Reserved Reserved. Data Input Time-out Interrupt Flag (Read Only) This bit indicates that eMMC host counts to time-out value when receiving data (waiting start bit).
Page 861 NUC970 Technical Reference Manual CRC-16 Check Status of Data-in Transfer (Read Only) eMMC host will check CRC-16 correctness after data-in transfer. CRC16 0 = Fault. 1 = OK. CRC-7 Check Status (Read Only) eMMC host will check CRC-7 correctness during each response in. If that response does not contain CRC-7 information (ex.
Page 862 NUC970 Technical Reference Manual eMMC Receiving Response Token Register 0 (FMI_EMMCRESP0) Register Offset Description Reset Value FMI_EMMCRE FMI_BA+0x830 eMMC Receiving Response Token Register 0 0x0000_0000 RESPONSE RESPONSE RESPONSE RESPONSE Bits Description eMMC Receiving Response Token 0 eMMC host controller will receive a response token for getting a reply from eMMC device RESPONSE [31:0] when RI_EN (FMI_EMMCCTL[1]) is set.
Page 863 NUC970 Technical Reference Manual eMMC Receiving Response Token Register 1 (FMI_EMMCRESP1) Register Offset Description Reset Value FMI_EMMCRE FMI_BA+0x834 eMMC Receiving Response Token Register 1 0x0000_0000 Reserved Reserved Reserved RESPONSE Bits Description [31:8] Reserved Reserved. eMMC Receiving Response Token 1 eMMC host controller will receive a response token for getting a reply from eMMC device RESPONSE [7:0] when RI_EN (FMI_EMMCCTL[1]) is set.
Page 864 NUC970 Technical Reference Manual eMMC Block Length Register (FMI_EMMCBLEN) Register Offset Description Reset Value FMI_EMMCBL FMI_BA+0x838 eMMC Block Length Register 0x0000_01FF Reserved Reserved Reserved BLK_LENGTH BLK_LENGTH Bits Description [31:11] Reserved Reserved. eMMC Block Length in Byte Unit An 11-bit value specifies the eMMC transfer byte count of a block. The actual byte count is [10:0] BLK_LENGTH equal to BLK_LENGTH+1.
Page 865 NUC970 Technical Reference Manual eMMC Response/Data-in Time-out Register (FMI_EMMCTOUT) Register Offset Description Reset Value FMI_EMMCTO FMI_BA+0x83C eMMC Response/Data-in Time-out Register 0x0000_0000 Reserved TIMEOUT TIMEOUT TIMEOUT Bits Description [31:24] Reserved Reserved. eMMC Response/Data-in Time-out Value A 24-bit value specifies the time-out counts of response and data input. eMMC host controller will wait start bit of response or data-in until this value reached.
Page 866 NUC970 Technical Reference Manual NAND Flash Control Register (FMI_NANDCTL) Register Offset Description Reset Value FMI_NANDCT FMI_BA+0x8A0 NAND Flash Control Register 0x1E88_0090 Reserved Reserved ECC_EN BCH_TSEL PSIZE Reserved SRAM_INT PROT_3BEN ECC_CHK Reserved PROT_REGION_EN REDUN_AUTO_WEN REDUN_REN DWR_EN DRD_EN SW_RST Bits Description [31:27] Reserved Reserved.
Page 867 NUC970 Technical Reference Manual BCH Correct Bit Selection This field is used to select BCH correct bits for data protecting. For BCH algorithm, T can be 4 or 8 or 12 or 15 or 24 for choosing (correct 4 or 8 or 12 or 15 or 24 bits). 00001 = Using BCH T24 to encode/decode (T24).(1024 Bytes per block) [22:18] BCH_TSEL...
Page 868 NUC970 Technical Reference Manual Redundant Area Read Enable This bit enables NAND controller to transfer redundant data from NAND Flash into FMI_NANDRA, the data size is dependent on FMI_NANDRACTL register. REDUN_REN 0 = No effect. 1 = Enable read redundant data transfer. NOTE: When transfer completed, this bit will be cleared automatically.
Page 869 NUC970 Technical Reference Manual NAND Flash Timing Control Register (FMI_NANDTMCTL) Register Offset Description Reset Value FMI_NANDTMC FMI_BA+0x8A4 NAND Flash Timing Control Register 0x0001_0105 Reserved Reserved CALE_SH HI_WID LO_WID Bits Description [31:23] Reserved Reserved. CLE/ALE Setup/Hold Time This field controls the CLE/ALE setup/hold time to –WE. The setup/hold time can be calculated using following equation: CALE_SH [22:16]...
Page 870 NUC970 Technical Reference Manual Timing Controlled by FMI_NANDTMCTL Register Publication Release Date: Dec. 15, 2015 - 870 - Revision V1.30...
Page 871 NUC970 Technical Reference Manual NAND Flash Interrupt Enable Register (FMI_NANDINTEN) Register Offset Description Reset Value FMI_NANDINT FMI_BA+0x8A8 NAND Flash Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved RB1_IE RB0_IE Reserved Reserved PROT_REGION_WR_IE ECC_FLD_IE Reserved DMA_IE Bits Description [31:12] Reserved Reserved. Ready/-Busy 1 Rising Edge Detect Interrupt Enable RB1_IE [11] 0 = Disable R/-B rising edge detect interrupt generation.
Page 872 NUC970 Technical Reference Manual NAND Flash Interrupt Status Register (FMI_NANDINTSTS) Register Offset Description Reset Value FMI_NANDINT FMI_BA+0x8AC NAND Flash Interrupt Status Register 0x00XX_0000 Reserved Reserved RB1_Status RB0_Status Reserved Reserved RB1_IF RB0_IF Reserved Reserved PROT_REGION_WR_IF ECC_FLD_IF Reserved DMA_IF Bits Description [31:20] Reserved Reserved.
Page 873 NUC970 Technical Reference Manual ECC Field Check Error Interrupt Flag (Read Only) This bit can check the ECC error on each field (512bytes) of data transfer. Read this bit to check if the error occurred. ECC_FLD_IF 0 = No occurrence of ECC error. 1 = Occurrence of ECC error.
Page 874 NUC970 Technical Reference Manual NAND Flash Command Port Register (FMI_NANDCMD) Register Offset Description Reset Value FMI_NANDCM FMI_BA+0x8B0 NAND Flash Command Port Register 0xXXXX_XXXX Reserved Reserved Reserved COMMAND Bits Description [31:8] Reserved Reserved. NAND Flash Command Port [7:0] COMMAND When CPU writes to this port, FMI will send a command to NAND Flash. Publication Release Date: Dec.
Page 875 NUC970 Technical Reference Manual NAND Flash Address Port Register (FMI_NANDADDR) Register Offset Description Reset Value FMI_NANDAD FMI_BA+0x8B4 NAND Flash Address Port Register 0xXXXX_XXXX Reserved Reserved Reserved ADDRESS Bits Description End of Address Writing this bit to indicate if this address is the last one or not. By writing address port with this bit low, NAND flash controller will set ALE pin to active (HIGH).
Page 876 NUC970 Technical Reference Manual NAND Flash Data Port Register (FMI_NANDDATA) Register Offset Description Reset Value FMI_NANDDA FMI_BA+0x8B8 NAND Flash Data Port Register 0xXXXX_XXXX Reserved Reserved Reserved DATA Bits Description [31:8] Reserved Reserved. NAND Flash Data Port CPU can access NAND’s memory array through this data port. When CPU WRITE, the lower 8- DATA [7:0] bit data from CPU will appear on the data bus of NAND controller.
Page 877 NUC970 Technical Reference Manual NAND Flash Redundant Area Control Register (FMI_NANDRACTL) Register Offset Description Reset Value FMI_NANDRACTL FMI_BA+0x8BC NAND Flash Redundant Area Control 0x0000_0000 Register MECC MECC Reserved RA128EN RA128EN Bits Description Mask ECC During Write Page Data These 16 bits registers indicate NAND controller to write out ECC parity or just 0xFF for each field (every 512 bytes) the real parity data will be write out to FMI_NANDRAx.
Page 878 NUC970 Technical Reference Manual NAND Flash Extend Control Regsiter (FMI_NANDECTL) Register Offset Description Reset Value FMI_NANDECTL FMI_BA+0x8C0 NAND Flash Extend Control Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description Reserved [31:1] Reserved. NAND Flash Write Protect Control (Low Active) Set this bit low to make NAND_nWP functional pin low to prevent the write to NAND flash device.
Page 879 NUC970 Technical Reference Manual NAND Flash ECC Error Status 0 Register (FMI_NANDECCES0) Register Offset Description Reset Value FMI_NANDECCES0 FMI_BA+0x8D0 NAND Flash ECC Error Status 0 Register 0x0000_0000 Reserved F4_ECNT F4_STAT Reserved F3_ECNT F3_STAT Reserved F2_ECNT F2_STAT Reserved F1_ECNT F1_STAT Bits Description Reserved [31]...
Page 880 NUC970 Technical Reference Manual Error Count of ECC Field 2 This field contains the error counts after ECC correct calculation of Field 2. For this ECC core [14:10] F2_ECNT (BCH algorithm), only when F2_STAT equals to 0x01, the value in this field is meaningful. F2_ECNT means how many errors depending on which ECC is used.
Page 881 NUC970 Technical Reference Manual NAND Flash ECC Error Status 1 Register (FMI_NANDECCES1) Register Offset Description Reset Value FMI_NANDECCES1 FMI_BA+0x8D4 NAND Flash ECC Error Status 1 Register 0x0000_0000 Reserved F8_ECNT F8_STAT Reserved F7_ECNT F7_STAT Reserved F6_ECNT F6_STAT Reserved F5_ECNT F5_STAT Bits Description Reserved [31]...
Page 882 NUC970 Technical Reference Manual Error Count of ECC Field 6 This field contains the error counts after ECC correct calculation of Field 6. For this ECC core [14:10] F6_ECNT (BCH algorithm), only when F6_STAT equals to 0x01, the value in this field is meaningful. F6_ECNT means how many errors depending on which ECC is used.
Page 883 NUC970 Technical Reference Manual NAND Flash ECC Error Status 2 Register (FMI_NANDECCES2) Register Offset Description Reset Value FMI_NANDECCES2 FMI_BA+0x8D8 NAND Flash ECC Error Status 2 Register 0x0000_0000 Reserved F12_ECNT F12_STAT Reserved F11_ECNT F11_STAT Reserved F10_ECNT F10_STAT Reserved F9_ECNT F9_STAT Bits Description Reserved [31]...
Page 884 NUC970 Technical Reference Manual Error Count of ECC Field 10 This field contains the error counts after ECC correct calculation of Field 10. For this ECC core [14:10] F10_ECNT (BCH algorithm), only when F10_STAT equals to 0x01, the value in this field is meaningful. F10_ECNT means how many errors depending on which ECC is used.
Page 885 NUC970 Technical Reference Manual NAND Flash ECC Error Status 3 Register (FMI_NANDECCES3) Register Offset Description Reset Value FMI_NANDECCES3 FMI_BA+0x8DC NAND Flash ECC Error Status 3 Register 0x0000_0000 Reserved F16_ECNT F16_STAT Reserved F15_ECNT F15_STAT Reserved F14_ECNT F14_STAT Reserved F13_ECNT F13_STAT Bits Description Reserved [31]...
Page 886 NUC970 Technical Reference Manual Error Count of ECC Field 14 This field contains the error counts after ECC correct calculation of Field 14. For this ECC core [14:10] F14_ECNT (BCH algorithm), only when F14_STAT equals to 0x01, the value in this field is meaningful. F14_ECNT means how many errors depending on which ECC is used.
Page 887 NUC970 Technical Reference Manual NAND Flash Protect Region End Address 0 Register (FMI_NANDPROTA0) Register Offset Description Reset Value FMI_NANDPROTA0 FMI_BA+0x8E0 NAND Flash Protect Region End Address 0 0x0000_0000 Register ADDR ADDR ADDR ADDR Bits Description NAND Flash Protect End Address Register 0 By setting register FMI_NANDPROTA0, FMI_NANDPROTA1 and enable PROT_REGION_EN [31:0] ADDR...
Page 888 NUC970 Technical Reference Manual NAND Flash Protect Region End Address 1 Register (FMI_NANDPROTA1) Register Offset Description Reset Value FMI_NANDPROTA1 FMI_BA+0x8E4 NAND Flash Protect Region End Address 1 0x0000_0000 Register Reserved Reserved Reserved ADDR Bits Description [31:8] Reserved Reserved. NAND Flash Protect End Address Register 1 By setting register FMI_NANDPRTOA0, FMI_NANDPROTA1 and enable PROT_REGION_EN ADDR [7:0]...
Page 889 NUC970 Technical Reference Manual NAND Flash ECC Error Byte Address 0 Register (FMI_NANDECCEA0) Register Offset Description Reset Value FMI_NANDECCEA0 FMI_BA+0x900 NAND Flash ECC Error Byte Address 0 0x0000_0000 Register Reserved ERR_ADDR1 ERR_ADDR1 Reserved ERR_ADDR0 ERR_ADDR0 Bits Description [31:27] Reserved Reserved. ECC Error Address First Field of Error 1 ERR_ADDR1 [26:16]...
Page 890 NUC970 Technical Reference Manual NAND Flash ECC Error Byte Address 1 Register (FMI_NANDECCEA1) Register Offset Description Reset Value FMI_NANDECCEA1 FMI_BA+0x904 NAND Flash ECC Error Byte Address 1 0x0000_0000 Register Reserved ERR_ADDR3 ERR_ADDR3 Reserved ERR_ADDR2 ERR_ADDR2 Bits Description [31:27] Reserved Reserved. ECC Error Address First Field of Error 3 ERR_ADDR3 [26:16]...
Page 891 NUC970 Technical Reference Manual NAND Flash ECC Error Byte Address 2 Register (FMI_NANDECCEA2) Register Offset Description Reset Value FMI_NANDECCEA2 FMI_BA+0x908 NAND Flash ECC Error Byte Address 2 0x0000_0000 Register Reserved ERR_ADDR5 ERR_ADDR5 Reserved ERR_ADDR4 ERR_ADDR4 Bits Description [31:27] Reserved Reserved. ECC Error Address First Field of Error 5 ERR_ADDR5 [26:16]...
Page 892 NUC970 Technical Reference Manual NAND Flash ECC Error Byte Address 3 Register (FMI_NANDECCEA3) Register Offset Description Reset Value FMI_NANDECCEA3 FMI_BA+0x90C NAND Flash ECC Error Byte Address 3 0x0000_0000 Register Reserved ERR_ADD7 ERR_ADDR7 Reserved ERR_ADDR6 ERR_ADDR6 Bits Description [31:27] Reserved Reserved. ECC Error Address First Field of Error 7 ERR_ADDR7 [26:16]...
Page 893 NUC970 Technical Reference Manual NAND Flash ECC Error Byte Address 4 Register (FMI_NANDECCEA4) Register Offset Description Reset Value FMI_NANDECCEA4 FMI_BA+0x910 NAND Flash ECC Error Byte Address 4 0x0000_0000 Register Reserved ERR_ADDR9 ERR_ADDR9 Reserved ERR_ADDR8 ERR_ADDR8 Bits Description [31:27] Reserved Reserved. ECC Error Address First Field of Error 9 ERR_ADDR9 [26:16]...
Page 894 NUC970 Technical Reference Manual NAND Flash ECC Error Byte Address 5 Register (FMI_NANDECCEA5) Register Offset Description Reset Value FMI_NANDECCEA5 FMI_BA+0x914 NAND Flash ECC Error Byte Address 5 0x0000_0000 Register Reserved ERR_ADDR11 ERR_ADDR11 Reserved ERR_ADDR10 ERR_ADDR10 Bits Description [31:27] Reserved Reserved. ECC Error Address First Field of Error 11 ERR_ADDR11 [26:16]...
Page 895 NUC970 Technical Reference Manual NAND Flash ECC Error Byte Address 6 Register (FMI_NANDECCEA6) Register Offset Description Reset Value FMI_NANDECCEA6 FMI_BA+0x918 NAND Flash ECC Error Byte Address 6 0x0000_0000 Register Reserved ERR_ADDR13 ERR_ADDR13 Reserved ERR_ADDR12 ERR_ADDR12 Bits Description [31:27] Reserved Reserved. ECC Error Address First Field of Error 13 ERR_ADDR13 [26:16]...
Page 896 NUC970 Technical Reference Manual NAND Flash ECC Error Byte Address 7 Register (FMI_NANDECCEA7) Register Offset Description Reset Value FMI_NANDECCEA7 FMI_BA+0x91C NAND Flash ECC Error Byte Address 7 0x0000_0000 Register Reserved ERR_ADDR15 ERR_ADDR15 Reserved ERR_ADDR14 ERR_ADDR14 Bits Description [31:27] Reserved Reserved. ECC Error Address First Field of Error 15 ERR_ADDR15 [26:16]...
Page 897 NUC970 Technical Reference Manual NAND Flash ECC Error Byte Address 8 Register (FMI_NANDECCEA8) Register Offset Description Reset Value FMI_NANDECCEA8 FMI_BA+0x920 NAND Flash ECC Error Byte Address 8 0x0000_0000 Register Reserved ERR_ADDR17 ERR_ADDR17 Reserved ERR_ADDR16 ERR_ADDR16 Bits Description [31:27] Reserved Reserved. ECC Error Address First Field of Error 17 [26:16] ERR_ADDR17...
Page 898 NUC970 Technical Reference Manual NAND Flash ECC Error Byte Address 9 Register (FMI_NANDECCEA9) Register Offset Description Reset Value FMI_NANDECCEA9 FMI_BA+0x924 NAND Flash ECC Error Byte Address 9 0x0000_0000 Register Reserved ERR_ADDR19 ERR_ADDR19 Reserved ERR_ADDR18 ERR_ADDR18 Bits Description [31:27] Reserved Reserved. ECC Error Address First Field of Error 19 ERR_ADDR19 [26:16]...
Page 899 NUC970 Technical Reference Manual NAND Flash ECC Error Byte Address 10 Register (FMI_NANDECCEA10) Register Offset Description Reset Value FMI_NANDECCEA10 FMI_BA+0x928 NAND Flash ECC Error Byte Address 10 0x0000_0000 Register Reserved ERR_ADDR21 ERR_ADDR21 Reserved ERR_ADDR20 ERR_ADDR20 Bits Description [31:27] Reserved Reserved. ECC Error Address First Field of Error 21 ERR_ADDR21 [26:16]...
Page 900 NUC970 Technical Reference Manual NAND Flash ECC Error Byte Address 11 Register (FMI_NANDECCEA11) Register Offset Description Reset Value FMI_NANDECCEA11 FMI_BA+0x92C NAND Flash ECC Error Byte Address 11 0x0000_0000 Register Reserved ERR_ADDR23 ERR_ADDR23 Reserved ERR_ADDR22 ERR_ADDR22 Bits Description [31:27] Reserved Reserved. ECC Error Address First Field of Error 23 ERR_ADDR23 [26:16]...
Page 901 NUC970 Technical Reference Manual NAND Flash ECC Error Data Register 0 (FMI_NANDECCED0) Register Offset Description Reset Value FMI_NANDECCED0 FMI_BA+0x960 NAND Flash ECC Error Data Register 0 0x8080_8080 ERR_DATA3 ERR_DATA2 ERR_DATA1 ERR_DATA0 Bits Description ECC Error Data of First Field 3 This field contains an 8-bit BCH ECC error data 3 of first field.
Page 902 NUC970 Technical Reference Manual NAND Flash ECC Error Data Register 1 (FMI_NANDECCED1) Register Offset Description Reset Value FMI_NANDECCED1 FMI_BA+0x964 NAND Flash ECC Error Data Register 1 0x8080_8080 ERR_DATA7 ERR_DATA6 ERR_DATA5 ERR_DATA4 Bits Description ECC Error Data of First Field 7 This field contains an 8-bit BCH ECC error data 7 of first field.
Page 903 NUC970 Technical Reference Manual NAND Flash ECC Error Data Register 2 (FMI_NANDECCED2) Register Offset Description Reset Value FMI_NANDECCED2 FMI_BA+0x968 NAND Flash ECC Error Data 0x8080_8080 Register 2 ERR_DATA11 ERR_DATA10 ERR_DATA9 ERR_DATA8 Bits Description ECC Error Data of First Field 11 This field contains an 8-bit BCH ECC error data 11 of first field.
Page 904 NUC970 Technical Reference Manual NAND Flash ECC Error Data Register 3 (FMI_NANDECCED3) Register Offset Description Reset Value FMI_NANDECCED3 FMI_BA+0x96C NAND Flash ECC Error Data Register 3 0x8080_8080 ERR_DATA15 ERR_DATA14 ERR_DATA13 ERR_DATA12 Bits Description ECC Error Data of First Field 15 This field contains an 8-bit BCH ECC error data 15 of first field.
Page 905 NUC970 Technical Reference Manual NAND Flash ECC Error Data Register 4 (FMI_NANDECCED4) Register Offset Description Reset Value FMI_NANDECCED4 FMI_BA+0x970 NAND Flash ECC Error Data Register 4 0x8080_8080 ERR_DATA19 ERR_DATA18 ERR_DATA17 ERR_DATA16 Bits Description ECC Error Data of First Field 19 This field contains an 8-bit BCH ECC error data 19 of first field.
Page 906 NUC970 Technical Reference Manual NAND Flash ECC Error Data Register 5 (FMI_NANDECCED5) Register Offset Description Reset Value FMI_NANDECCED5 FMI_BA+0x974 NAND Flash ECC Error Data Register 5 0x8080_8080 ERR_DATA23 ERR_DATA22 ERR_DATA21 ERR_DATA20 Bits Description ECC Error Data of First Field 23 This field contains an 8-bit BCH ECC error data 23 of first field.
Page 907: Secure Digital Host Controller (Sdh)
NUC970 Technical Reference Manual 5.26 Secure Digital Host Controller (SDH) 5.26.1 Overview The Secure-Digital Card Host Controller (SDH) equips DMAC unit and SD unit. The DMAC unit provides a DMA (Direct Memory Access) function for SD to exchange data between system memory and shared buffer (128 bytes), and the SD unit controls the interface of SD/SDHC/SDIO.
Page 908: Basic Configuration
NUC970 Technical Reference Manual 5.26.4 Basic Configuration Before using SD host controller, it’s necessary to configure related pins as the SDH function and enable SDH’s clock. For SD host related pin configuration, please refer to the register SYS_MFP_GPDL, SYS_MFP_GPEL, SYS_MFP_GPEH, SYS_MFP_GPHL and SYS_MFP_GPHH to know how to configure related pins as the SD host function.
Page 909 NUC970 Technical Reference Manual SDH controller uses an independent clock source named SDCLK as engine clock. SDCLK can be completely asynchronous with system clock HCLK, SDCLK is changeable. However the HCLK should be faster than SDCLK. This SDH controller can generate all types of 48-bit command to SD card and retrieve all types of response from SD card.
Page 910: Registers Map
NUC970 Technical Reference Manual 5.26.6 Registers Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SDH Base Address: SDH_BA = 0xB000_C000 SDH_FB_n SD Host Embedded Buffer Word n SDH_BA+0x000 + 0x0000_0000 0x4 * n n = 0,1…31 n = 0,1…31 SDH_DMACTL...
Page 911 NUC970 Technical Reference Manual SD Host DMA Control and Status Register (SDH_DMACTL) Register Offset Description Reset Value SDH_DMACTL SDH_BA+0x400 R/W SD Host DMA Control and Status Register 0x0000_0000 Reserved Reserved Reserved DMABUSY Reserved Reserved SGEN Reserved DMARST DMAEN Bits Description [31:10] Reserved Reserved.
Page 912: Figure 5.26-1 Pad (Physical Address Descriptor) Table Format
NUC970 Technical Reference Manual SD Host DMA Transfer Starting Address Register (SDH_DMASA) Register Offset Description Reset Value SDH_DMASA SDH_BA+0x408 R/W SD Host DMA Transfer Starting Address Register 0x0000_0000 ADDR ADDR ADDR ADDR ADDR/ORDER Bits Description DMA Transfer Starting Address This field indicates a 32-bit starting address of system memory (SRAM/SDRAM) for DMA to [31:0] ADDR retrieve or fill in data.
Page 913: Figure 5.26-2 Pad (Physical Address Descriptor) Table Fetch Modes
NUC970 Technical Reference Manual tables sequentially if ORDER (SDH_DMASA[0]) set as low. SDH fetehced next PAD tables based on the Next Descriptor Physical Base Address of PAD table if ORDER (SDH_DMASA[0]) set as high. System Memory (ORDER = 0) System Memory (ORDER = 1) PAD Table #1 PAD Table #1 PAD Table #2...
Page 914 NUC970 Technical Reference Manual SD Host DMA Transfer Byte Count Register (SDH_DMABCNT) Register Offset Description Reset Value SDH_DMABCNT SDH_BA+0x40C R SD Host DMA Transfer Byte Count Register 0x0000_0000 Reserved BCNT BCNT BCNT BCNT Bits Description Reserved [31:26] Reserved. DMA Transfer Byte Count (Read Only) [25:0] BCNT This field indicates the remained byte count of DMA transfer.
Page 915 NUC970 Technical Reference Manual SD Host DMA Interrupt Enable Register (SDH_DMAINTEN) Register Offset Description Reset Value SDH_DMAINTEN SDH_BA+0x410 SD Host DMA Interrupt Enable Register 0x0000_0001 Reserved Reserved Reserved Reserved WEOT_IE TABORT_IE Bits Description Reserved [31:2] Reserved. Wrong EOT (End of Transfer) Encountered Interrupt Enable WEOT_IE 0 = Interrupt generation Disabled when wrong EOT (End of Transfer) is encountered.
Page 916 NUC970 Technical Reference Manual SD Host DMA Interrupt Status Register (SDH_DMAINTSTS) Register Offset Description Reset Value SDH_DMAINTSTS SDH_BA+0x414 R/W SD Host DMA Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WEOT_IF TABORT_IF Bits Description Reserved [31:2] Reserved. Wrong EOT Encountered Interrupt Flag When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of FMI), this bit will be set.
Page 917 NUC970 Technical Reference Manual SD Host Global Control and Status Register (SDH_GCTL) Register Offset Description Reset Value SDH_GCTL SDH_BA+0x800 R/W SD Host Global Control and Status Register 0x0000_0000 Reserved Reserved Reserved Reserved SDEN GCTLRST Bits Description Reserved [31:2] Reserved. Secure-digital Functionality Enable SDEN 0 = SD host functionality Disabled.
Page 918 NUC970 Technical Reference Manual SD Host Global Interrupt Control Register (SDH_GINTEN) Register Offset Description Reset Value SDH_GINTEN SDH_BA+0x804 R/W SD Host Global Interrupt Control Register 0x0000_0001 Reserved Reserved Reserved Reserved DTA_IE Bits Description [31:1] Reserved Reserved. DMA READ/WRITE Target Abort Interrupt Enable DTA_IE 0 = DMAC READ/WRITE target abort interrupt generation Disabled.
Page 919 NUC970 Technical Reference Manual SD Host Global Interrupt Status Register (SDH_GINTSTS) Register Offset Description Reset Value SDH_GINTSTS SDH_BA+0x808 R/W SD Host Global Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved DTA_IF Bits Description Reserved [31:1] Reserved. DMAC READ/WRITE Target Abort Interrupt Flag (Read Only) This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation.
Page 920 NUC970 Technical Reference Manual SD Host Control and Status Register (SDH_CTL) Register Offset Description Reset Value SDH_CTL SDH_BA+0x820 SD Host Control and Status Register 0x0101_0000 CLK_KEEP1 SDPORT Reserved SDNWR BLK_CNT SW_RST CMD_CODE CLK_KEEP0 CLK8_OE CLK74_OE R2_EN DO_EN DI_EN RI_EN CO_EN Bits Description SD Host Port 1 Clock Keep Running Enable...
Page 921 NUC970 Technical Reference Manual SD Command Code [13:8] CMD_CODE This register contains the SD command code (0x00 – 0x3F). SD Host Port 0 Clock Keep Running Enable CLK_KEEP0 0 = SD host port 0 clock generation controlled by SD host automatically. 1 = SD host port 0 clock always keeps free running.
Page 922 NUC970 Technical Reference Manual SD Host Command Argument Register (SDH_CMD) Register Offset Description Reset Value SDH_CMD SDH_BA+0x824 SD Host Command Argument Register 0x0000_0000 SD_CMD_ARG SD_CMD_ARG SD_CMD_ARG SD_CMD_ARG Bits Description SD Command Argument This register contains a 32-bit value specifies the argument of SD command from host [31:0] SD_CMD_ARG controller to SD card.
Page 923 NUC970 Technical Reference Manual SD Host Interrupt Enable Register (SDH_INTEN) Register Offset Description Reset Value SDH_INTEN SDH_BA+0x828 SD Host Interrupt Enable Register 0x0000_0A00 CD1SRC CD0SRC Reserved Reserved Reserved DITO_IE RITO_IE SDIO1_IE SDIO0_IE CD1_IE CD0_IE Reserved CRC_IE BLKD_IE Bits Description SD Port 1 Card Detect Source Selection 0 = From SD port 1 data bit 3, the pin SD1_DAT3.
Page 924 NUC970 Technical Reference Manual SDIO Interrupt Enable for Port 0 Enable/Disable interrupts generation of SD host when SDIO card 0 issue an interrupt via pin SD0_DAT1 to host. SDIO0_IE [10] 0 = Disable. 1 = Enable. SD1 Card Detection Interrupt Enable Enable/Disable interrupts generation of SD controller when card 1 is inserted or removed.
Page 925 NUC970 Technical Reference Manual SD Host Interrupt Status Register (SDH_INTSTS) Register Offset Description Reset Value SDH_INTSTS SDH_BA+0x82C SD Host Interrupt Status Register 0x000X_008C Reserved Reserved SD1DAT1 SD0DAT1 CDPS1 CDPS0 Reserved DITO_IF RITO_IF SDIO1_IF SDIO0_IF CD1_IF CD0_IF SDDAT0 CRCSTAT CRC16 CRC7 CRC_IF BLKD_IF Bits...
Page 926 NUC970 Technical Reference Manual Data Input Time-out Interrupt Flag (Read Only) This bit indicates that SD host counts to time-out value when receiving data (waiting start bit). [13] DITO_IF 0 = Not time-out. 1 = Data input time-out. NOTE: This bit is read only, but can be cleared by writing ‘1’ to it. Response Time-out Interrupt Flag (Read Only) This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).
Page 927 NUC970 Technical Reference Manual CRC-16 Check Status of Data-in Transfer (Read Only) SD host will check CRC-16 correctness after data-in transfer. CRC16 0 = Fault. 1 = OK. CRC-7 Check Status (Read Only) SD host will check CRC-7 correctness during each response in. If that response does not contain CRC-7 information (ex.
Page 928 NUC970 Technical Reference Manual SD Host Receiving Response Token Register 0 (SDH_RESP0) Register Offset Description Reset Value SDH_RESP0 SDH_BA+0x830 SD Host Receiving Response Token Register 0 0x0000_0000 SD_RSP_TK0 SD_RSP_TK0 SD_RSP_TK0 SD_RSP_TK0 Bits Description SD Receiving Response Token 0 [31:0] SD_RSP_TK0 SD host controller will receive a response token for getting a reply from SD card when RI_EN (SDH_CTL[1]) is set.
Page 929 NUC970 Technical Reference Manual SD Host Receiving Response Token Register 1 (SDH_RESP1) Register Offset Description Reset Value SDH_RESP1 SDH_BA+0x834 SD Host Receiving Response Token Register 1 0x0000_0000 Reserved Reserved Reserved SD_RSP_TK1 Bits Description SD Receiving Response Token 1 [7:0] SD_RSP_TK1 SD host controller will receive a response token for getting a reply from SD card when RI_EN (SDH_CTL[1]) is set.
Page 930 NUC970 Technical Reference Manual SD Host Block Length Register (SDH_BLEN) Register Offset Description Reset Value SDH_BLEN SDH_BA+0x838 SD Host Block Length Register 0x0000_01FF Reserved Reserved Reserved BLKLEN BLKLEN Bits Description Reserved [31:11] Reserved. SD Block Length in Byte Unit An 11-bit value specifies the SD transfer byte count of a block. The actual byte count is equal BLKLEN [10:0] to BLKLEN+1.
Page 931 NUC970 Technical Reference Manual SD Host Response/Data-in Time-out Register (SDH_TMOUT) Register Offset Description Reset Value SDH_TMOUT SDH_BA+0x83C SD Host Response/Data-in Time-out Register 0x0000_0000 Reserved TMOUT TMOUT TMOUT Bits Description Reserved [31:24] Reserved. SD Response/Data-in Time-out Value A 24-bit value specifies the time-out counts of response and data input. SD host controller will wait start bit of response or data-in until this value reached.
Page 932 NUC970 Technical Reference Manual SD Host Extend Control Register (SDH_ECTL) Register Offset Description Reset Value SDH_ECTL SDH_BA+0x840 SD Host Extend Control Register 0x0000_0003 Reserved Reserved Reserved Reserved PWROFF1 PWROFF0 Bits Description Reserved [31:2] Reserved. SD Port 1 Power Disable Set this bit low to make the SD1_nPWR functional pin low to turn on the power of SD port 1. PWROFF1 0 = SD port 1 power Enabled.
Page 933: Cryptographic Accelerator (Crypto)
NUC970 Technical Reference Manual 5.27 Cryptographic Accelerator (CRYPTO) 5.27.1 Overview The Crypto (Cryptographic Accelerator) includes a secure pseudo random number generator (PRNG) core and supports AES, DES/TDES, SHA and HMAC algorithms. The PRNG core supports 64 bits, 128 bits, 192 bits, and 256 bits random number generation. The AES accelerator is an implementation fully compliant with the AES (Advance Encryption Standard) encryption and decryption algorithm.
Page 934: Block Diagram
NUC970 Technical Reference Manual  HMAC  Supports FIPS NIST 180, 180-2  Supports HMAC-SHA-160, HMAC-SHA-224, HMAC-SHA-256, HMAC-SHA-384, and HMAC-SHA-512 5.27.3 Block Diagram Figure 5.27-1 Cryptographic Accelerator Block Diagram 5.27.4 Basic Configuration Before using cryptographic engine, it’s necessary to enable clock of cryptographic engine. Set CRYPTO (CLK_HCLKEN[23]) high to enable clock for cryptographic engine operation.
Page 935: Functional Description
NUC970 Technical Reference Manual 5.27.5 Functional description The cryptographic accelerator includes a secure pseudo random number generator (PRNG) core and supports AES, DES/TDES, SHA, and HMAC algorithms. The accelerator can be used in different data security applications, such as secure communications that need cryptographic protection and integrity. The PRNG core supports 64 bits, 128 bits, 192 bits, and 256 bits random number generation configured by KEYSZ.
Page 936: Figure 5.27-2 Prng Function Diagram
NUC970 Technical Reference Manual 5.27.5.1 PRNG (Pseudo Random number Generator) The PRNG block diagram is depicted below. The core supports 64 bits, 128 bits, 192 bits, and 256 bits random number generation configured by KEYSZ(CRPT_PRNG_CTL[3:2] ). PRNG_BUSY PRNG0 PRNG PRNG_SEED PRNG7 PRNG_KEY_SIZE PRNG_SEED_RELOAD...
Page 937: Figure 5.27-3 Electronic Codebook Mode
NUC970 Technical Reference Manual Figure 5.27-3 Electronic Codebook Mode In ECB mode, any given plaintext block always gets encrypted to the same ciphertext block under a given key. If this property is undesirable in a particular application, the ECB mode should not be used. Cipher Block Chaining Mode: The Cipher Block Chaining (CBC) mode is a confidentiality mode whose encryption process features the combining chaining of the plaintext blocks with the previous ciphertext blocks.
Page 938: Figure 5.27-4 Cipher Block Chaining Mode
NUC970 Technical Reference Manual Figure 5.27-4 Cipher Block Chaining Mode Cipher Feedback Mode (CFB): The Cipher Feedback (CFB) mode is a confidentiality mode that features the feedback of successive ciphertext segments into the input blocks of the forward cipher to generate output blocks that are exclusive-ORed with the plaintext to produce the ciphertext, and vice versa.
Page 939: Figure 5.27-5 Cipher Feedback Mode
NUC970 Technical Reference Manual Figure 5.27-5 Cipher Feedback Mode Output Feedback Mode: The Output Feedback (OFB) mode is a confidentiality mode that features the iteration of the forward cipher on an IV to generate a sequence of output blocks that are exclusive-ORed with the plaintext to produce the ciphertext, and vice versa.
Page 940: Figure 5.27-6 Output Feedback Mode
NUC970 Technical Reference Manual Figure 5.27-6 Output Feedback Mode Counter Mode (CTR): The Counter (CTR) mode is a confidentiality mode that features the application of the forward cipher to a set of input blocks, called counters, to produce a sequence of output blocks that are exclusive- ORed with the plaintext to produce the ciphertext, and vice versa.
Page 941: Figure 5.27-7 Counter Mode
NUC970 Technical Reference Manual Figure 5.27-7 Counter Mode CBC Ciphertext-Stealing 1 Mode (CBC-CS1): The figure below illustrates the CBC-CS1-Encrypt algorithm for the case that P is a partial block. The with ‘0’ to form a complete block P cryptographic accelerator would append P Publication Release Date: Dec.
Page 942: Figure 5.27-8 Cbc-Cs1 Encryption
NUC970 Technical Reference Manual Figure 5.27-8 CBC-CS1 Encryption The figure below illustrates the CBC-CS1-Decrypt algorithm for the case that C is a partial block. Figure 5.27-9 CBC-CS1 Decryption CBC Ciphertext-Stealing 2 Mode (CBC-CS2): When P is a partial block, then CBC-CS2-Encrypt and CBC-CS1-Encrypt differ only in the ordering of and C Publication Release Date: Dec.
Page 943 NUC970 Technical Reference Manual CBC Ciphertext-Stealing 3 Mode (CBC-CS3): and C are unconditionally swapped, i.e., even when C is a complete block; therefore, CBC- CS3 is not strictly an extension of CBC mode. In the other case, i.e., when C is a nonempty partial block, CBC-CS3-Encrypt is equivalent to CBC-CS2-Encrypt.
Page 944 NUC970 Technical Reference Manual is 0. Check the TDES engine is in idle state, i.e., BUSY(CRPT_TDES_STS [0]) Program TDES key to registers CRPT_TDESn_KEY1H, CRPT_TDESn_KEY1L, CRPT_TDESn_KEY2H, CRPT_TDESn_KEY2L, CRPT_TDESn_KEY3H, and CRPT_TDESn_KEY3L. (where n is the selected channel number) Program initial vector to registers CRPT_TDESn_IVH and CRPT_TDESn_IVL. CRPT_TDESn_SADDR.
Page 945 NUC970 Technical Reference Manual Read output digest (SHA160: CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4, SHA224: CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6, SHA256: CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7, SHA384: CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11, SHA512: CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15). SHA Non-DMA mode programming flow: Configure SHA/HMAC control register CRPT_HMAC_CTL for SHA/HMAC engine input/output and SHA mode.
Page 946 NUC970 Technical Reference Manual If it’s the last input word, set DMALAST(CRPT_HMAC_CTL[5]). start HMAC encryption. Write 1 to START(CRPT_HMAC_CTL[0]) to Waits for the HMAC data input request DATINREQ(CRPT_HMAC_STS[16]) be set. Write one word of input data to CRPT_HMAC_DATIN. Repeat step 2 to 5 until all inut words are written into SHA engine. Waits for the BUSY (CRPT_HMAC_STS[0]) be cleared.
Page 947: Register Map
NUC970 Technical Reference Manual 5.27.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CRYP Base Address: CRYP_BA = 0xB000_C000 CRPT_INTEN CRYP_BA+0x000 Crypto Interrupt Enable Control Register 0x0000_0000 CRPT_INTSTS CRYP_BA+0x004 Crypto Interrupt Flag 0x0000_0000 CRPT_PRNG_CTL CRYP_BA+0x008...
Page 948 NUC970 Technical Reference Manual CRPT_AES0_KEY4 CRYP_BA+0x120 AES Key Word 4 Register for Channel 0 0x0000_0000 CRPT_AES0_KEY5 CRYP_BA+0x124 AES Key Word 5 Register for Channel 0 0x0000_0000 CRPT_AES0_KEY6 CRYP_BA+0x128 AES Key Word 6 Register for Channel 0 0x0000_0000 CRPT_AES0_KEY7 CRYP_BA+0x12C AES Key Word 7 Register for Channel 0 0x0000_0000 CRPT_AES0_IV0 CRYP_BA+0x130...
Page 949 NUC970 Technical Reference Manual CRPT_AES2_KEY7 CRYP_BA+0x1A4 AES Key Word 7 Register for Channel 2 0x0000_0000 CRPT_AES2_IV0 CRYP_BA+0x1A8 AES Initial Vector Word 0 Register for Channel 2 0x0000_0000 CRPT_AES2_IV1 CRYP_BA+0x1AC AES Initial Vector Word 1 Register for Channel 2 0x0000_0000 CRPT_AES2_IV2 CRYP_BA+0x1B0 AES Initial Vector Word 2 Register for Channel 2 0x0000_0000...
Page 950 NUC970 Technical Reference Manual CRPT_TDES0_IVL TDES/DES Initial Vector Low Word Register for 0x0000_0000 CRYP_BA+0x224 Channel 0 CRPT_TDES0_SADDR TDES/DES DMA Source Address Register for 0x0000_0000 CRYP_BA+0x228 Channel 0 CRPT_TDES0_DADDR TDES/DES DMA Destination Address Register for 0x0000_0000 CRYP_BA+0x22C Channel 0 CRPT_TDES0_CNT CRYP_BA+0x230 TDES/DES Byte Count Register for Channel 0 0x0000_0000 CRPT_TDES_DATIN...
Page 951 NUC970 Technical Reference Manual CRPT_TDES2_CNT CRYP_BA+0x2B0 TDES/DES Byte Count Register for Channel 2 0x0000_0000 CRPT_TDES3_KEY1H TDES/DES Key 1 High Word Register for Channel 0x0000_0000 CRYP_BA+0x2C8 CRPT_TDES3_KEY1L TDES/DES Key 1 Low Word Register for Channel 0x0000_0000 CRYP_BA+0x2CC CRPT_TDES3_KEY2H CRYP_BA+0x2D0 TDES Key 2 High Word Register for Channel 3 0x0000_0000 CRPT_TDES3_KEY2L CRYP_BA+0x2D4...
Page 952 NUC970 Technical Reference Manual CRPT_HMAC_SADDR CRYP_BA+0x34C SHA/HMAC DMA Source Address Register 0x0000_0000 CRPT_HMAC_DMACNT CRYP_BA+0x350 SHA/HMAC Byte Count Register 0x0000_0000 CRPT_HMAC_DATIN SHA/HMAC Engine Non-DMA Mode Data Input 0x0000_0000 CRYP_BA+0x354 Port Register Publication Release Date: Dec. 15, 2015 - 952 - Revision V1.30...
Page 953: Register Description
NUC970 Technical Reference Manual 5.27.7 Register Description 5.27.7.1 Crypto Register Publication Release Date: Dec. 15, 2015 - 953 - Revision V1.30...
Page 954 NUC970 Technical Reference Manual CRYPTO Interrupt Enable Control Register (CRPT_INTEN) Register Offset Description Reset Value CRPT_INTEN CRYP_BA+0x000 Crypto Interrupt Enable Control Register 0x0000_0000 Reserved HMACEIEN HMACIEN Reserved PRNGIEN Reserved TDESEIEN TDESIEN Reserved AESEIEN AESIEN Bits Description [31:26] Reserved Reserved. SHA/HMAC Error Interrupt Enable Control [25] HMACEIEN 0 = SHA/HMAC error interrupt flag Disabled.
Page 955 NUC970 Technical Reference Manual AES Error Flag Enable Control AESEIEN 0 = AES error interrupt flag Disabled. 1 = AES error interrupt flag Enabled. AES Interrupt Enable Control 0 = AES interrupt Disabled. 1 = AES interrupt Enabled. AESIEN In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.
Page 956 NUC970 Technical Reference Manual CRYPTO Interrupt Flag Register (CRPT_INTSTS) Register Offset Description Reset Value CRPT_INTSTS CRYP_BA+0x004 Crypto Interrupt Flag 0x0000_0000 Reserved HMACEIF HMACIF Reserved PRNGIF Reserved TDESEIF TDESIF Reserved AESEIF AESIF Bits Description Reserved [31:26] Reserved. SHA/HMAC Error Flag This register includes operating and setting error. The detail flag is shown in SHA _FLAG register.
Page 957 NUC970 Technical Reference Manual TDES/DES Finish Interrupt Flag This bit is cleared by writing 1, and it has no effect by writing 0. TDESIF 0 = No TDES/DES interrupt. 1 = TDES/DES encryption/decryption done interrupt. Reserved [7:2] Reserved. AES Error Flag This bit is cleared by writing 1, and it has no effect by writing 0.
Page 958 NUC970 Technical Reference Manual 5.27.7.2 PRNG Register Publication Release Date: Dec. 15, 2015 - 958 - Revision V1.30...
Page 959 NUC970 Technical Reference Manual PRNG Control Register (CRPT_PRNG_CTL) Register Offset Description Reset Value CRPT_PRNG_CTL CRYP_BA+0x008 PRNG Control Register 0x0000_0000 Reserved Reserved Reserved BUSY Reserved KEYSZ SEEDRLD START Bits Description Reserved [31:9] Reserved. PRNG Busy (Read Only) BUSY 0 = PRNG engine is idle. 1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx.
Page 960 NUC970 Technical Reference Manual PRNG Seed Register (CRPT_PRNG_SEED) Register Offset Description Reset Value CRPT_PRNG_SEED CRYP_BA+0x00C Seed for PRNG Undefined SEED SEED SEED SEED Bits Description Seed for PRNG (Write Only) [31:0] SEED The bits store the seed for PRNG engine. Publication Release Date: Dec.
Page 961 NUC970 Technical Reference Manual PRNG Key x Register (CRPT_PRNG_KEYx) Register Offset R/W Description Reset Value CRPT_PRNG_KEY0 CRYP_BA+0x010 PRNG Generated Key0 Undefined CRPT_PRNG_KEY1 CRYP_BA+0x014 PRNG Generated Key1 Undefined CRPT_PRNG_KEY2 CRYP_BA+0x018 PRNG Generated Key2 Undefined CRPT_PRNG_KEY3 CRYP_BA+0x01C PRNG Generated Key3 Undefined CRPT_PRNG_KEY4 CRYP_BA+0x020 PRNG Generated Key4 Undefined CRPT_PRNG_KEY5 CRYP_BA+0x024...
Page 962 NUC970 Technical Reference Manual 5.27.7.3 AES Register Publication Release Date: Dec. 15, 2015 - 962 - Revision V1.30...
Page 963 NUC970 Technical Reference Manual AES Control Register (CRPT_AES_CTL) Register Offset R/W Description Reset Value CRPT_AES_CTL CRYP_BA+0x100 R/W AES Control Register 0x0000_0000 KEYPRT KEYUNPRT CHANNEL INSWAP OUTSWAP Reserved ENCRPT OPMODE DMAEN DMACSCAD DMALAST EXTKEY KEYSZ STOP START Bits Description Protect Key Read as a flag to reflect KEYPRT.
Page 964 NUC970 Technical Reference Manual AES Encryption/Decryption [16] ENCRPT 0 = AES engine executes decryption operation. 1 = AES engine executes encryption operation. AES Engine Operation Modes 0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). 0x02 = CFB (Cipher Feedback Mode). 0x03 = OFB (Output Feedback Mode).
Page 965 NUC970 Technical Reference Manual AES Engine Stop 0 = No effect. STOP 1 = Stop AES engine. Note: This bit is always 0 when it’s read back. AES Engine Start 0 = No effect. START 1 = Start AES engine. BUSY flag will be set. Note: This bit is always 0 when it’s read back.
Page 966 NUC970 Technical Reference Manual AES Status Flag Register (CRPT_AES_STS) Register Offset Description Reset Value CRPT_AES_STS CRYP_BA+0x104 R AES Engine Flag 0x0001_0100 Reserved Reserved BUSERR Reserved OUTBUFERR OUTBUFFULL OUTBUFEMPTY Reserved CNTERR Reserved INBUFERR INBUFFULL INBUFEMPTY Reserved BUSY Bits Description Reserved [31:21] Reserved.
Page 967 NUC970 Technical Reference Manual AES Input Buffer Error Flag [10] INBUFERR 0 = No error. 1 = Error happens during feeding data to the AES engine. AES Input Buffer Full Flag 0 = AES input buffer is not full. Software can feed the data into the AES INBUFFULL engine.
Page 968 NUC970 Technical Reference Manual AES Data Input Port Register (CRPT_AES_DATIN) Register Offset Description Reset Value CRPT_AES_DATIN CRYP_BA+0x108 R/W AES Engine Data Input Port Register 0x0000_0000 DATIN DATIN DATIN DATIN Bits Description AES Engine Input Port [31:0] DATIN CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
Page 969 NUC970 Technical Reference Manual AES Data Output Port Register (CRPT_AES_DATOUT) Register Offset Description Reset Value CRPT_AES_DATOUT CRYP_BA+0x10C R AES Engine Data Output Port Register 0x0000_0000 DATOUT DATOUT DATOUT DATOUT Bits Description AES Engine Output Port [31:0] DATOUT CPU gets results from the AES engine through this port by checking CRPT_AES_STS. Get data as OUTBUFEMPTY is 0.
Page 970 NUC970 Technical Reference Manual AES Key Word x Register (CRPT_AES0_KEYx, CRPT_AES1_KEYx, CRPT_AES2_KEYx, CRPT_AES3_KEYx) Register Offset Description Reset Value CRPT_AES0_KEY0 CRYP_BA+0x110 R/W AES Key Word 0 Register for Channel 0 0x0000_0000 CRPT_AES0_KEY1 CRYP_BA+0x114 R/W AES Key Word 1 Register for Channel 0 0x0000_0000 CRPT_AES0_KEY2 CRYP_BA+0x118 R/W...
Page 971 NUC970 Technical Reference Manual Bits Description CRPT_AESn_KEYx The KEY keeps the security key for AES operation. n = 0, 1..3. x = 0, 1..7. The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit [31:0] registers are to store each security key.
Page 972 NUC970 Technical Reference Manual AES Initial Vector Word x Register (CRPT_AES0_IVx, CRPT_AES1_IVx, CRPT_AES2_IVx, CRPT_AES3_IVx) Register Offset R/W Description Reset Value CRPT_AES0_IV0 CRYP_BA+0x130 R/W AES Initial Vector Word 0 Register for Channel 0 0x0000_0000 CRPT_AES0_IV1 CRYP_BA+0x134 R/W AES Initial Vector Word 1 Register for Channel 0 0x0000_0000 CRPT_AES0_IV2 CRYP_BA+0x138...
Page 973 NUC970 Technical Reference Manual AES DMA Source Address Register (CRPT_AES0_SADDR, CRPT_AES1_SADDR, CRPT_AES2_SADDR, CRPT_AES3_SADDR) Register Offset R/W Description Reset Value CRPT_AES0_SADDR CRYP_BA+0x140 R/W AES DMA Source Address Register for Channel 0 0x0000_0000 CRPT_AES1_SADDR CRYP_BA+0x17C R/W AES DMA Source Address Register for Channel 1 0x0000_0000 CRPT_AES2_SADDR CRYP_BA+0x1B8 R/W AES DMA Source Address Register for Channel 2...
Page 974 NUC970 Technical Reference Manual AES DMA Destination Address Register (CRPT_AES0_DADDR, CRPT_AES1_DADDR, CRPT_AES2_DADDR, CRPT_AES3_DADDR) Register Offset R/W Description Reset Value CRPT_AES0_DADDR CRYP_BA+0x144 R/W AES DMA Destination Address Register for Channel 0 0x0000_0000 CRPT_AES1_DADDR CRYP_BA+0x180 R/W AES DMA Destination Address Register for Channel 1 0x0000_0000 CRPT_AES2_DADDR CRYP_BA+0x1BC R/W AES DMA Destination Address Register for Channel 2...
Page 975 NUC970 Technical Reference Manual AES Byte Count Register (CRPT_AES0_CNT, CRPT_AES1_CNT, CRPT_AES2_CNT, CRPT_AES3_CNT) Register Offset Description Reset Value CRPT_AES0_CNT CRYP_BA+0x148 R/W AES Byte Count Register for Channel 0 0x0000_0000 CRPT_AES1_CNT CRYP_BA+0x184 R/W AES Byte Count Register for Channel 1 0x0000_0000 CRPT_AES2_CNT CRYP_BA+0x1C0 R/W AES Byte Count Register for Channel 2 0x0000_0000...
Page 976 NUC970 Technical Reference Manual AES Feedback x Register (CRPT_AES_FDBCKx) Register Offset Description Reset Value CRPT_AES_FDBCK0 CRYP_BA+0x050 AES Engine Output Feedback Data after 0x0000_0000 Cryptographic Operation CRPT_AES_FDBCK1 CRYP_BA+0x054 AES Engine Output Feedback Data after 0x0000_0000 Cryptographic Operation CRPT_AES_FDBCK2 CRYP_BA+0x058 AES Engine Output Feedback Data after 0x0000_0000 Cryptographic Operation CRPT_AES_FDBCK3...
Page 977 NUC970 Technical Reference Manual 5.27.7.4 TDES/DES Register Publication Release Date: Dec. 15, 2015 - 977 - Revision V1.30...
Page 978 NUC970 Technical Reference Manual TDES/DES Control Register (CRPT_TDES_CTL) Register Offset Description Reset Value CRPT_TDES_CTL CRYP_BA+0x200 R/W TDES/DES Control Register 0x0000_0000 KEYPRT KEYUNPRT CHANNEL INSWAP OUTSWAP BLKSWAP Reserved ENCRPT Reserved OPMODE DMAEN DMACSCAD DMALAST Reserved 3KEYS TMODE STOP START Bits Description Protect Key Read as a flag to reflect KEYPRT.
Page 979 NUC970 Technical Reference Manual TDES/DES Engine Block Double Word Endian Swap 0 = Keep the original order, e.g. {WORD_H, WORD_L}. BLKSWAP [21] 1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}. [20:17] Reserved Reserved.
Page 980 NUC970 Technical Reference Manual TDES/DES Engine Start 0 = No effect. START 1 = Start TDES/DES engine. The flag BUSY would be set. Note: The bit is always 0 when it’s read back. Publication Release Date: Dec. 15, 2015 - 980 - Revision V1.30...
Page 981 NUC970 Technical Reference Manual TDES/DES Status Flag Register (CRPT_TDES0_STS) Register Offset Description Reset Value CRPT_TDES_STS CRYP_BA+0x204 R TDES/DES Engine Flag 0x0001_0100 Reserved Reserved BUSERR Reserved OUTBUFERR OUTBUFFULL OUTBUFEMPTY Reserved INBUFERR INBUFFULL INBUFEMPTY Reserved BUSY Bits Description Reserved [31:21] Reserved. TDES/DES DMA Access Bus Error Flag [20] BUSERR 0 = No error.
Page 982 NUC970 Technical Reference Manual TDES/DES in Buffer Full Flag 0 = TDES/DES input buffer is not full. Software can feed the data into the INBUFFULL TDES/DES engine. 1 = TDES input buffer is full. Software cannot feed data to the TDES/DES engine.
Page 983 NUC970 Technical Reference Manual TDES/DES Key 1, 2, 3 High/Low Word Register (TDES_KEY1H/L, TDES_KEY2H/L, TDES_KEY3H/L) Register Offset R/W Description Reset Value CRPT_TDES0_KEY1H CRYP_BA+0x208 R/W TDES/DES Key 1 High Word Register for Channel 0 0x0000_0000 CRPT_TDES0_KEY1L CRYP_BA+0x20C R/W TDES/DES Key 1 Low Word Register for Channel 0 0x0000_0000 CRPT_TDES0_KEY2H CRYP_BA+0x210 R/W TDES Key 2 High Word Register for Channel 0...
Page 984 NUC970 Technical Reference Manual KEYH/KEYL Bits Description TDES/DES Key High/Low Word The key registers for TDES/DES algorithm calculation The security key for the TDES/DES accelerator is 64 bits. Thus, it needs two 32-bit [31:0] KEYH/KEYL registers to store a security key. The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
Page 985 NUC970 Technical Reference Manual TDES/DES IV High/Low Word Register (CRPT_TDES0_IVH/L, CRPT_TDES1_IVH/L, CRPT_TDES2_IVH/L, CRPT_TDES3_IVH/L) Register Offset Description Reset Value CRPT_TDES0_IVH CRYP_BA+0x220 TDES/DES Initial Vector High Word Register for 0x0000_0000 Channel 0 CRPT_TDES0_IVL TDES/DES Initial Vector Low Word Register for CRYP_BA+0x224 0x0000_0000 Channel 0 CRPT_TDES1_IVH CRYP_BA+0x260...
Page 986 NUC970 Technical Reference Manual TDES/DES DMA Source Address Register (CRPT_TDES0_SADDR, CRPT_TDES1_SADDR, CRPT_TDES2_SADDR, CRPT_TDES3_SADDR) Register Offset Description Reset Value CRPT_TDES0_SADDR CRYP_BA+0x228 R/W TDES/DES DMA Source Address Register for 0x0000_0000 Channel 0 CRPT_TDES1_SADDR TDES/DES DMA Source Address Register for CRYP_BA+0x268 R/W 0x0000_0000 Channel 1 CRPT_TDES2_SADDR CRYP_BA+0x2A8 R/W...
Page 987 NUC970 Technical Reference Manual TDES/DES DMA Destination Address Register (CRPT_TDES0_DADDR, CRPT_TDES1_DADDR, CRPT_TDES2_DADDR, CRPT_TDES3_DADDR) Register Offset Description Reset Value CRPT_TDES0_DADDR CRYP_BA+0x22C TDES/DES DMA Destination Address Register for 0x0000_0000 Channel 0 CRPT_TDES1_DADDR CRYP_BA+0x26C TDES/DES DMA Destination Address Register for 0x0000_0000 Channel 1 CRPT_TDES2_DADDR CRYP_BA+0x2AC TDES/DES DMA Destination Address Register for 0x0000_0000...
Page 988 NUC970 Technical Reference Manual TDES/DES Block Count Register (CRPT_TDES0_CNT, CRPT_TDES1_CNT, CRPT_TDES2_CNT, CRPT_TDES3_CNT) Register Offset Description Reset Value CRPT_TDES0_CNT CRYP_BA+0x230 R/W TDES/DES Byte Count Register for Channel 0 0x0000_0000 CRPT_TDES1_CNT CRYP_BA+0x270 R/W TDES/DES Byte Count Register for Channel 1 0x0000_0000 CRPT_TDES2_CNT CRYP_BA+0x2B0 R/W TDES/DES Byte Count Register for Channel 2 0x0000_0000...
Page 989 NUC970 Technical Reference Manual TDES/DES Data Input Port Register (CRPT_TDES_DATIN) Register Offset Description Reset Value CRPT_TDES_DATIN CRYP_BA+0x234 TDES/DES Engine Input data Word Register 0x0000_0000 DATIN DATIN DATIN DATIN Bits Description TDES/DES Engine Input Port [31:0] DATIN CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS. Feed data as INBUFFULL is 0.
Page 990 NUC970 Technical Reference Manual TDES/DES Data Output Port Register (CRPT_TDES_DATOUT) Register Offset Description Reset Value CRPT_TDES_DATOUT CRYP_BA+0x238 TDES/DES Engine Output data Word Register 0x0000_0000 DATOUT DATOUT DATOUT DATOUT Bits Description TDES/DES Engine Output Port [31:0] DATOUT CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS.
Page 991 NUC970 Technical Reference Manual TDES/DES Feedback x Register (CRPT_TDES_FDBCKx) Register Offset Description Reset Value CRPT_TDES_FDBCKH CRYP_BA+0x060 TDES/DES Engine Output Feedback High Word 0x0000_0000 Data after Cryptographic Operation CRPT_TDES_FDBCKL CRYP_BA+0x064 TDES/DES Engine Output Feedback Low Word 0x0000_0000 Data after Cryptographic Operation FDBCK FDBCK FDBCK...
Page 992 NUC970 Technical Reference Manual 5.27.7.5 SHA/HMAC Register Publication Release Date: Dec. 15, 2015 - 992 - Revision V1.30...
Page 993 NUC970 Technical Reference Manual SHA/HMAC Control Register (CRPT_HMAC_CTL) Register Offset R/W Description Reset Value CRPT_HMAC_CTL CRYP_BA+0x300 R/W SHA/HMAC Control Register 0x0000_0000 Reserved INSWAP OUTSWAP Reserved CMPEN Reserved OPMODE DMAEN Reserved DMALAST HMACEN Reserved STOP START Bits Description [31:24] Reserved Reserved. SHA/HMAC Engine Input Data Swap 0 = Keep the original order.
Page 994 NUC970 Technical Reference Manual SHA/HMAC Engine DMA Enable Control 0 = SHA/HMAC DMA engine Disabled. SHA/HMAC engine operates in Non-DMA mode, and gets data from the port DMAEN CRPT_HMAC_DATIN. 1 = SHA/HMAC DMA engine Enabled. SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
Page 995 NUC970 Technical Reference Manual SHA/HMAC Status Register (CRPT_HMAC_STS) Register Offset R/W Description Reset Value CRPT_HMAC_STS CRYP_BA+0x304 R SHA/HMAC Status Flag 0x0000_0000 Reserved Reserved DATINREQ CMPSTS Reserved DMAERR Reserved DMABUSY BUSY Bits Description [31:16] Reserved Reserved. SHA/HMAC Non-dMA Mode Data Input Request [16] DATINREQ 0 = No effect.
Page 996 NUC970 Technical Reference Manual SHA/HMAC Outputs Digest Word Register (CRPT_HMAC_DGSTx) Register Offset Description Reset Value CRPT_HMAC_DGS CRYP_BA+0x308 SHA/HMAC Digest Message 0 0x0000_0000 CRPT_HMAC_DGS CRYP_BA+0x30C R SHA/HMAC Digest Message 1 0x0000_0000 CRPT_HMAC_DGS CRYP_BA+0x310 SHA/HMAC Digest Message 2 0x0000_0000 CRPT_HMAC_DGS CRYP_BA+0x314 SHA/HMAC Digest Message 3 0x0000_0000 CRPT_HMAC_DGS CRYP_BA+0x318...
Page 997 NUC970 Technical Reference Manual DGST Bits Description SHA/HMAC Digest Message Output Register For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. [31:0] DGST For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11.
Page 998 NUC970 Technical Reference Manual SHA/HMAC Key Byte Count Register (CRPT_HMAC_KEYCNT ) Register Offset R/W Description Reset Value CRPT_HMAC_KEYCNT CRYP_BA+0x348 R/W SHA/HMAC Key Byte Count Register 0x0000_0000 KEYCNT KEYCNT KEYCNT KEYCNT Bits Description SHA/HMAC Key Byte Count The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates. The register is 32-bit and the maximum byte count is 4G bytes.
Page 999 NUC970 Technical Reference Manual SHA/HMAC DMA Source Address Register (CRPT_HMAC_SADDR) Register Offset R/W Description Reset Value CRPT_HMAC_SADDR CRYP_BA+0x34C R/W SHA/HMAC DMA Source Address Register 0x0000_0000 SADDR SADDR SADDR SADDR Bits Description SHA/HMAC DMA Source Address The SHA/HMAC accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
Page 1000 NUC970 Technical Reference Manual SHA/HMAC Byte Count Register (CRPT_HMAC_DMACNT) Register Offset R/W Description Reset Value CRPT_HMAC_DMACNT CRYP_BA+0x350 R/W SHA/HMAC Byte Count Register 0x0000_0000 DMACNT DMACNT DMACNT DMACNT Bits Description SHA/HMAC Operation Byte Count The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode.

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