ST STM32F0 Series Programming Manual
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Introduction
This programming manual provides information for application and system-level software
developers. It gives a full description of the STM32 Cortex™-M0 processor programming
model, instruction set and core peripherals.
The STM32 Cortex™-M0 processor is a high performance 32-bit processor designed for the
microcontroller market. It offers significant benefits to developers, including:
■
Outstanding processing performance combined with fast interrupt handling
■
Enhanced system debug with extensive breakpoint and trace capabilities
■
Efficient processor core, system and memories
■
Ultra-low power consumption with integrated sleep modes
■
Platform security
Table 1.
Microcontroller
April 2012
STM32F0xxx Cortex-M0 programming manual
Applicable products
Type
STM32F0xxx
Doc ID 022979 Rev 1
Programming manual
Part numbers
PM0215
1/91
www.st.com
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Table of Contents
Related Manuals for ST STM32F0 Series
Summary of Contents for ST STM32F0 Series
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Page 1: Table 1. Applicable Products
Enhanced system debug with extensive breakpoint and trace capabilities ■ Efficient processor core, system and memories ■ Ultra-low power consumption with integrated sleep modes ■ Platform security Table 1. Applicable products Type Part numbers Microcontroller STM32F0xxx April 2012 Doc ID 022979 Rev 1 1/91 www.st.com... -
Page 2: Table Of Contents
Contents PM0215 Contents About this document ........8 Typographical conventions . - Page 3 PM0215 Contents 2.5.2 Wakeup from sleep mode ........29 2.5.3 The external event input .
- Page 4 Contents PM0215 3.7.3 DMB ........... . 63 3.7.4 DSB .
- Page 5 PM0215 Contents 4.4.5 SysTick design hints and tips ....... . . 88 4.4.6 SysTick register map .
- Page 6 List of tables PM0215 List of tables Table 1. Applicable products ............1 Table 2.
- Page 7 PM0215 List of figures List of figures Figure 1. STM32 Cortex-M0 implementation ..........9 Figure 2.
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Page 8: About This Document
About this document PM0215 About this document This document provides the information required for application and system-level software development. It does not provide information on debug components, features, or operation. This material is for microcontroller software and hardware engineers, including those who have no experience of ARM products. -
Page 9: About The Stm32 Cortex-M0 Processor And Core Peripherals
PM0215 About this document About the STM32 Cortex-M0 processor and core peripherals The Cortex-M0 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: ● a simple architecture that is easy to learn and program ●... -
Page 10: System Level Interface
About this document PM0215 1.3.1 System level interface ® The Cortex-M0 processor provides a single system-level interface using AMBA technology to provide high speed, low latency memory accesses. 1.3.2 Integrated configurable debug The Cortex-M0 processor implements a complete hardware debug solution, with extensive hardware breakpoint and watchpoint options. -
Page 11: The Stm32 Cortex-M0 Processor
PM0215 The STM32 Cortex-M0 processor The STM32 Cortex-M0 processor Programmers model This section describes the Cortex-M0 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and stacks. 2.1.1 Processor modes The processor modes are: Thread mode: Used to execute application software. -
Page 12: Core Registers
The STM32 Cortex-M0 processor PM0215 2.1.3 Core registers Figure 2. Processor core registers /RZ UHJLVWHUV *HQHUDO SXUSRVH UHJLVWHUV +LJK UHJLVWHUV 63 5 6WDFN 3RLQWHU /5 5 /LQN 5HJLVWHU 3& 5 3URJUDP &RXQWHU 3URJUDP 6WDWXV 5HJLVWHU 6SHFLDO UHJLVWHUV 35,0$6. ,QWHUUXSW PDVN UHJLVWHU &21752/ &RQWURO 5HJLVWHU 06 9... -
Page 13: Table 4. Psr Register Combinations And Attributes
PM0215 The STM32 Cortex-M0 processor Stack pointer (SP) register R13 In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use: ● 0: Main Stack Pointer (MSP)(reset value). On reset, the processor loads the MSP with the value from address 0x00000000. ●... -
Page 14: Table 5. Apsr Bit Definitions
The STM32 Cortex-M0 processor PM0215 Application program status register Contains the current state of The condition flags from previous instruction executions. See the register summary in Table 3 on page 12 for its attributes. Table 5. APSR bit definitions Bits Description Bit 31 N: Negative or less than flag:... -
Page 15: Table 7. Epsr Bit Definitions
PM0215 The STM32 Cortex-M0 processor Execution program status register The EPSR contains the Thumb state bit. See the register summary in Table 3 on page 12 for the EPSR attributes. The bit assignments are: Table 7. EPSR bit definitions Bits Description Bits 31:25 Reserved. -
Page 16: Table 8. Primask Register Bit Definitions
The STM32 Cortex-M0 processor PM0215 Table 8. PRIMASK register bit definitions Bits Description Bits 31:1 Reserved PRIMASK: Bit 0 0: No effect 1: Prevents the activation of all exceptions with configurable priority. Control register The CONTROL register controls the stack used when the processor is in Thread mode. See the register summary in Table 3 on page 12 for its attributes. -
Page 17: Exceptions And Interrupts
PM0215 The STM32 Cortex-M0 processor 2.1.4 Exceptions and interrupts The Cortex-M0 processor supports interrupts and system exceptions. The processor and the NVIC prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions except for reset. -
Page 18: Memory Model
The STM32 Cortex-M0 processor PM0215 Memory model This section describes the processor memory map, and the behavior of memory accesses. The processor has a fixed memory map that provides up to 4 GB of addressable memory. Figure 6. Memory map [)))))))) 'HYLFH 0%... -
Page 19: Memory Regions, Types And Attributes
PM0215 The STM32 Cortex-M0 processor 2.2.1 Memory regions, types and attributes The memory map is split into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: Normal The processor can re-order transactions for efficiency, or... -
Page 20: Behavior Of Memory Accesses
The STM32 Cortex-M0 processor PM0215 2.2.3 Behavior of memory accesses The behavior of accesses to each region in the memory map is: Table 11. Memory access behavior Address Memory Memory Description range region type 0x00000000- Executable region for program code. Can also put Code Normal 0x1FFFFFFF... -
Page 21: Memory Endianness
PM0215 The STM32 Cortex-M0 processor Use memory barrier instructions in, for example: ● Vector table: If the program changes an entry in the vector table, and then enables the corresponding exception, use a DMB instruction between the operations. This ensures that if the exception is taken immediately after being enabled the processor uses the new exception vector. -
Page 22: Exception Model
The STM32 Cortex-M0 processor PM0215 Exception model This section describes the exception model. 2.3.1 Exception states Each exception is in one of the following states: Inactive The exception is not active and not pending. Pending The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. -
Page 23: Exception Handlers
PM0215 The STM32 Cortex-M0 processor Interrupt (IRQ) A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 12. -
Page 24: Vector Table
The STM32 Cortex-M0 processor PM0215 2.3.4 Vector table The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 8 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code. -
Page 25: Exception Priorities
PM0215 The STM32 Cortex-M0 processor 2.3.5 Exception priorities Table 12 on page 23 shows, all exceptions have an associated priority, with: ● A lower priority value indicating a higher priority ● Configurable priorities for all exceptions except Reset, Hard fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. -
Page 26: Figure 9. Cortex-M0 Stack Frame Layout
The STM32 Cortex-M0 processor PM0215 Late-arriving This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. -
Page 27: Table 13. Exception Return Behavior
PM0215 The STM32 Cortex-M0 processor If another higher priority exception occurs during exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. This is the late arrival case. Exception return Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:... -
Page 28: Fault Handling
The STM32 Cortex-M0 processor PM0215 Fault handling Faults are a subset of the exceptions, see Exception model on page 22. All faults result in the HardFault exception being taken or cause lockup if they occur in the NMI or HardFault handler. -
Page 29: Entering Sleep Mode
PM0215 The STM32 Cortex-M0 processor 2.5.1 Entering sleep mode This section describes the mechanisms software can use to put the processor into sleep mode. The system can generate spurious wakeup events, for example a debug operation wakes up the processor. Therefore software must be able to put the processor back into sleep mode after such an event. -
Page 30: The External Event Input
The STM32 Cortex-M0 processor PM0215 Wakeup from WFE The processor wakes up if: ● it detects an exception with sufficient priority to cause exception entry ● it detects an external event signal, see Section 2.5.3: The external event input In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. -
Page 31: The Stm32 Cortex-M0 Instruction Set
PM0215 The STM32 Cortex-M0 instruction set The STM32 Cortex-M0 instruction set This chapter is the reference material for the Cortex-M0 instruction set description in a User Guide. The following sections give general information: Section 3.1: Instruction set summary on page 31 Section 3.2: CMSIS intrinsic functions on page 35 Section 3.3: About the instruction descriptions on page 36 Each of the following sections describes a functional group of Cortex-M0 instructions. - Page 32 The STM32 Cortex-M0 instruction set PM0215 Table 14. Cortex-M0 instructions Mnemonic Operands Brief description Flags Page 3.5.2 on BICS {Rd,} Rn, Rm Bit clear page 51 3.7.1 on BKPT #imm Breakpoint page 61 3.6.1 on label Branch with link page 59 3.6.1 on Branch indirect with Link page 59...
- Page 33 PM0215 The STM32 Cortex-M0 instruction set Table 14. Cortex-M0 instructions Mnemonic Operands Brief description Flags Page 3.5.3 on LSRS {Rd,} Rn, <Rs|#imm> Logical shift right N,Z,C page 52 3.5.5 on MOV{S} Rd, Rm Move page 54 Move to general register from special 3.7.6 on Rd, spec_reg register...
- Page 34 The STM32 Cortex-M0 instruction set PM0215 Table 14. Cortex-M0 instructions Mnemonic Operands Brief description Flags Page 3.5.1 on SUB{S} {Rd,} Rn, <Rm|#imm> Subtract N,Z,C,V page 49 3.7.10 on #imm Supervisor call page 67 3.5.8 on SXTB Rd, Rm Sign extend byte page 57 3.5.8 on SXTH...
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Page 35: Cmsis Intrinsic Functions
PM0215 The STM32 Cortex-M0 instruction set CMSIS intrinsic functions ISO/IEC C code cannot directly access some Cortex-M0 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, you might have to use an inline assembler to access some instructions. -
Page 36: About The Instruction Descriptions
The STM32 Cortex-M0 instruction set PM0215 About the instruction descriptions The following sections give more information about using the instructions: ● Operands on page 36 ● Restrictions when using PC or SP on page 36 ● Shift operations on page 36 ●... -
Page 37: Figure 10. Asr#3
PM0215 The STM32 Cortex-M0 instruction set Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left-hand n bits of the result (see Figure 10: ASR#3). -
Page 38: Figure 12. Lsl#3
The STM32 Cortex-M0 instruction set PM0215 Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n bits of the result. And it sets the right-hand n bits of the result to 0 (see Figure 12: LSL#3 on page 38). -
Page 39: Address Alignment
PM0215 The STM32 Cortex-M0 instruction set 3.3.4 Address alignment An aligned access is an operation where a word-aligned address is used for a word, or multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned. There is no support for unaligned accesses on the Cortex-M0 processor. -
Page 40: Table 17. Condition Code Suffixes And Their Relationship With The Flags
The STM32 Cortex-M0 instruction set PM0215 A carry occurs: ● If the result of an addition is greater than or equal to 2 ● If the result of a subtraction is positive or zero ● As the result of a shift or rotate instruction Overflow occurs if the sign of a result, in bit[31], does not match the sign of the result had the operation been performed at infinite precision, for example: ●... -
Page 41: Memory Access Instructions
PM0215 The STM32 Cortex-M0 instruction set Memory access instructions Table 18 shows the memory access instructions: Table 18. Memory access instructions Mnemonic Brief description Load PC-relative address ADR on page 42 Load multiple registers LDM and STM on page 46 LDR{type} Load register using immediate offset LDR and STR, immediate offset on page 43... -
Page 42: Adr
The STM32 Cortex-M0 instruction set PM0215 3.4.1 Load PC-relative address. Syntax ADR Rd, label where: ● ‘Rd’ is the destination register ● ‘label’ is a PC-relative expression (see PC-relative expressions on page Operation ADR determines the address by adding an immediate value to the PC. It writes the result to the destination register. -
Page 43: Ldr And Str, Immediate Offset
PM0215 The STM32 Cortex-M0 instruction set 3.4.2 LDR and STR, immediate offset Load and store with immediate offset. Syntax LDR Rt, [<Rn | SP> {, #imm}] LDR<B|H> Rt, [Rn {, #imm}] STR Rt, [<Rn | SP>, {,#imm}] STR<B|H> Rt, [Rn {,#imm}] where: ●... -
Page 44: Ldr And Str, Register Offset
The STM32 Cortex-M0 instruction set PM0215 3.4.3 LDR and STR, register offset Load and store with register offset. Syntax LDR Rt, [Rn, Rm] LDR<B|H> Rt, [Rn, Rm] LDR<SB|SH> Rt, [Rn, Rm] STR Rt, [Rn, Rm] STR<B|H> Rt, [Rn, Rm] where: ●... -
Page 45: Ldr, Pc-Relative
PM0215 The STM32 Cortex-M0 instruction set 3.4.4 LDR, PC-relative Load register (literal) from memory. Syntax LDR Rt, label where: ● ‘Rt’ is the register to load or store ● ‘label’ is a PC-relative expression (see PC-relative expressions on page Operation Loads the register specified by Rt from the word in memory specified by label. -
Page 46: Ldm And Stm
The STM32 Cortex-M0 instruction set PM0215 3.4.5 LDM and STM Load and store multiple registers. Syntax LDM Rn{!}, reglist STM Rn!, reglist where: ● ‘Rn’ is the register on which the memory addresses are based ● ‘!’ is an optional writeback suffix. If ! is present, the final address that is loaded from or stored to is written back into Rn. -
Page 47: Push And Pop
PM0215 The STM32 Cortex-M0 instruction set Incorrect examples R5!,{R4,R5,R6} ; Value stored for R5 is unpredictable R2,{} ; There must be at least one register in the list 3.4.6 PUSH and POP Push registers onto, and pop registers off a full-descending stack. Syntax PUSH reglist POP reglist... -
Page 48: General Data Processing Instructions
The STM32 Cortex-M0 instruction set PM0215 General data processing instructions Table 19 shows the data processing instructions. Table 19. Data processing instructions Mnemonic Brief description ADD{S}, ADCS, SUB{S}, SBCS, and RSBS on ADCS Add with carry page 49 ADD{S}, ADCS, SUB{S}, SBCS, and RSBS on ADD(S) page 49 ANDS... -
Page 49: Add{S}, Adcs, Sub{S}, Sbcs, And Rsbs
PM0215 The STM32 Cortex-M0 instruction set 3.5.1 ADD{S}, ADCS, SUB{S}, SBCS, and RSBS Add, add with carry, subtract, subtract with carry, and reverse subtract. Syntax ADCS {Rd,} Rn, Rm ADD{S} {Rd,} Rn, <Rm|#imm> RSBS {Rd,} Rn, Rm, #0 SBCS {Rd,} Rn, Rm SUB{S} {Rd,} Rn, <Rm|#imm>... -
Page 50: Table 20. Adcs, Add, Rsbs, Sbcs And Sub Operand Restrictions
The STM32 Cortex-M0 instruction set PM0215 Table 20. ADCS, ADD, RSBS, SBCS and SUB operand restrictions Instructi Restrictions ADCS R0-R7 R0-R7 R0-R7 - Rd and must specify the same register. Rd and must specify the same register. R0-R15 R0-R15 R0-PC - Rn and Rm must not both specify PC. -
Page 51: Ands, Orrs, Eors And Bics
PM0215 The STM32 Cortex-M0 instruction set 3.5.2 ANDS, ORRS, EORS and BICS Logical AND, OR, exclusive OR and bit clear. Syntax ANDS {Rd,} Rn, Rm ORRS {Rd,} Rn, Rm EORS {Rd,} Rn, Rm BICS {Rd,} Rn, Rm where: ● ‘Rd’ is the destination register ●... -
Page 52: Asrs, Lsls, Lsrs And Rors
The STM32 Cortex-M0 instruction set PM0215 3.5.3 ASRS, LSLS, LSRS and RORS Arithmetic shift right, logical shift left, logical shift right, and rotate right. Syntax ASRS {Rd,} Rm, Rs ASRS {Rd,} Rm, #imm LSLS {Rd,} Rm, Rs LSLS {Rd,} Rm, #imm LSRS {Rd,} Rm, Rs LSRS {Rd,} Rm, #imm RORS {Rd,} Rm, Rs... -
Page 53: Cmp And Cmn
PM0215 The STM32 Cortex-M0 instruction set 3.5.4 CMP and CMN Compare and compare negative. Syntax CMN Rn, Rm CMP Rn, #imm CMP Rn, Rm where: ● ‘Rn’ is the register holding the first operand ● Rm is the register to compare with. ●... -
Page 54: Mov, Movs And Mvns
The STM32 Cortex-M0 instruction set PM0215 3.5.5 MOV, MOVS and MVNS Move and move NOT. Syntax MOV{S} Rd, Rm MOVS Rd, #imm MVNS Rd, Rm where: ● ‘S’ is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution on page 39). -
Page 55: Muls
PM0215 The STM32 Cortex-M0 instruction set 3.5.6 MULS Multiply using 32-bit operands, and producing a 32-bit result. Syntax MULS Rd, Rn, Rm where: ● ‘Rd’ is the destination register ● ‘Rn, Rm’ are registers holding the values to be multiplied. Operation The MUL instruction multiplies the values in the registers specified by Rn and Rm, and places the least significant 32 bits of the result in Rd. -
Page 56: Rev, Rev16, And Revsh
The STM32 Cortex-M0 instruction set PM0215 3.5.7 REV, REV16, and REVSH Reverse bytes and reverse bits. Syntax op Rd, Rn where: ● ‘op’ is one of: REV: Reverse byte order in a word REV16: Reverse byte order in each halfword independently REVSH: Reverse byte order in the bottom halfword, and sign extends to 32 bits ●... -
Page 57: Sxtb, Sxth, Uxtb And Uxth
PM0215 The STM32 Cortex-M0 instruction set 3.5.8 SXTB, SXTH, UXTB and UXTH Sign extend and Zero extend. Syntax SXTB Rd, Rm SXTH Rd, Rm UXTB Rd, Rm UXTH Rd, Rm where: ● ‘Rd’ is the destination register ● ‘Rn’ ,‘Rm’ are the registers holding the first and second operands Operation These instructions extract bits from the resulting value: SXTB extracts bits[7:0] and sign extends to 32 bits... -
Page 58: Tst
The STM32 Cortex-M0 instruction set PM0215 3.5.9 Test bits. Syntax TST Rn, Rm where: ● ‘Rn’ is the register holding the first operand ● ‘Rm’ is the register to test against. Operation This instruction tests the value in a register against another register. It updates the condition flags based on the result, but does not write the result to a register. -
Page 59: Branch And Control Instructions
PM0215 The STM32 Cortex-M0 instruction set Branch and control instructions Table 21 shows the branch and control instructions: Table 21. Branch and control instructions Mnemonic Brief description B{cc} Branch {conditionally} Branch with link B, BL, BX, and BLX on page 59 Branch indirect with link Branch indirect 3.6.1... - Page 60 The STM32 Cortex-M0 instruction set PM0215 Table 22. Branch ranges (continued) Instruction Branch range − 16 MB to +16 MB BL label BX Rm Any value in register BLX Rm Any value in register Restrictions The restrictions are: ● Do not use SP or PC in the BX or BLX instruction ●...
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Page 61: Miscellaneous Instructions
PM0215 The STM32 Cortex-M0 instruction set Miscellaneous instructions Table 23 shows the remaining Cortex-M0 instructions: Table 23. Miscellaneous instructions Mnemonic Brief description BKPT Breakpoint BKPT on page 61 CPSID Change Processor State, Disable Interrupts CPSID CPSIE on page 62 CPSIE Change Processor State, Enable Interrupts CPSID CPSIE on page 62 Data Memory Barrier... -
Page 62: Cpsid Cpsie
The STM32 Cortex-M0 instruction set PM0215 3.7.2 CPSID CPSIE Change processor state. Syntax CPSID i CPSIE i Operation CPS changes the PRIMASK special register values. CPSID causes interrupts to be disabled by setting PRIMASK. CPSIE cause interrupts to be enabled by clearing PRIMASK. See Exception mask registers on page 15 for more information about these registers. -
Page 63: Dmb
PM0215 The STM32 Cortex-M0 instruction set 3.7.3 Data memory barrier. Syntax Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction. -
Page 64: Isb
The STM32 Cortex-M0 instruction set PM0215 3.7.5 Instruction synchronization barrier. Syntax Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from cache or memory again, after the ISB instruction has been completed. -
Page 65: Msr
PM0215 The STM32 Cortex-M0 instruction set 3.7.7 Move the contents of a general-purpose register into the specified special register. Syntax MSR spec_reg, Rn where: ● ‘Rn’ is the general-purpose source register. ● ‘spec_reg’ is the special-purpose destination register: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL. -
Page 66: Nop
The STM32 Cortex-M0 instruction set PM0215 3.7.8 No operation. Syntax Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for example to place the following instruction on a 64-bit boundary. Restrictions None Condition flags... -
Page 67: Svc
PM0215 The STM32 Cortex-M0 instruction set 3.7.10 Supervisor call. Syntax SVC #imm where: ‘imm’ is an integer in the range 0-255. Operation The SVC instruction causes the SVC exception. imm is ignored by the processor. It can be retrieved by the exception handler to determine what service is being requested. Restrictions : None Condition flags... -
Page 68: Wfi
The STM32 Cortex-M0 instruction set PM0215 3.7.12 Wait for Interrupt. Syntax Operation WFI is a hint instruction that suspends execution until one of the following events occurs: ● An exception ● An interrupt becomes pending which would preempt if PRIMASK was clear ●... -
Page 69: Core Peripherals
PM0215 Core peripherals Core peripherals About the STM32 Cortex-M0 core peripherals The address map of the Private peripheral bus (PPB) is: Table 24. STM32 core peripheral register regions Address Core peripheral Description 0xE000E008-0xE000E00F System control block (SCB) Table 32 on page 84 0xE000E010-0xE000E01F SysTick timer (STK) Table 34 on page 89... -
Page 70: Nested Vectored Interrupt Controller (Nvic)
Core peripherals PM0215 Nested vectored interrupt controller (NVIC) This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: ● Up to 32 interrupts ● A programmable priority level of 0-192 in steps of 64 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority ●... -
Page 71: Interrupt Set-Enable Register (Iser)
PM0215 Core peripherals 4.2.2 Interrupt set-enable register (ISER) Address offset: 0x00 Reset value: 0x0000 0000 The ISER register enables interrupts, and shows which interrupts are enabled SETENA[31:16] SETENA[15:0] Bits 31:0 SETENA: Interrupt set-enable bits. Write: 0: No effect 1: Enable interrupt Read: 0: Interrupt disabled 1: Interrupt enabled. -
Page 72: Interrupt Set-Pending Register (Ispr)
Core peripherals PM0215 4.2.4 Interrupt set-pending register (ISPR) Address offset: 0x0100 Reset value: 0x0000 0000 This register forces interrupts into pending state, and shows which interrupts are pending. SETPEND[31:16] SETPEND[15:0] Bits 31:0 SETPEND: Interrupt set-pending bits Write: 0: No effect 1: Changes interrupt state to pending Read: 0: Interrupt is not pending... -
Page 73: Interrupt Priority Register (Ipr0-Ipr7)
PM0215 Core peripherals 4.2.6 Interrupt priority register (IPR0-IPR7) Address offset: 0x0300 Reset value: 0x0000 0000 The IPR registers provide an 8-bit priority field for each interrupt. These registers are only word-accessible. Each register holds four priority fields, as shown in Figure Figure 14. -
Page 74: Level-Sensitive And Pulse Interrupts
Core peripherals PM0215 4.2.7 Level-sensitive and pulse interrupts STM32 interrupts are both level-sensitive and pulse-sensitive. Pulse interrupts are also described as edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. -
Page 75: Nvic Design Hints And Tips
PM0215 Core peripherals 4.2.8 NVIC design hints and tips Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. See the individual register descriptions for the supported access sizes. An interrupt can enter pending state even it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt. -
Page 76: Nvic Register Map
Core peripherals PM0215 4.2.9 NVIC register map This table shows the NVIC register map and reset values. The base address of the main NVIC register block is 0xE000E100. Table 29. NVIC register map and reset values Offset Register NVIC_ISER SETENA[31:0] 0x000 Reset Value NVIC_ICER... -
Page 77: System Control Block (Scb)
PM0215 Core peripherals System control block (SCB) The System control block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. To improve software efficiency, the CMSIS simplifies the SCB register presentation, in the CMSIS, the array SHP[1] corresponds to the registers SHPR2-SHPR3. -
Page 78: Interrupt Control And State Register (Icsr)
Core peripherals PM0215 4.3.2 Interrupt control and state register (ICSR) Address offset: 0x04 Reset value: 0x0000 0000 The ICSR: ● Provides: – A set-pending bit for the Non-Maskable Interrupt (NMI) exception – Set-pending and clear-pending bits for the PendSV and SysTick exceptions ●... - Page 79 PM0215 Core peripherals Bit 27 PENDSVCLR: PendSV clear-pending bit. This bit is write-only. On a read, value is unknown. 0: No effect 1: Removes the pending state from the PendSV exception. Bit 26 PENDSTSET: SysTick exception set-pending bit. Write: 0: No effect 1: Change SysTick exception state to pending Read: 0: SysTick exception is not pending...
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Page 80: Application Interrupt And Reset Control Register (Aircr)
Core peripherals PM0215 4.3.3 Application interrupt and reset control register (AIRCR) Address offset: 0x0C Reset value: 0xFA05 0000 The AIRCR provides endian status for data accesses and reset control of the system. To write to this register, you must write 0x5FA to the VECTKEY field, otherwise the processor ignores the write. -
Page 81: System Control Register (Scr)
PM0215 Core peripherals 4.3.4 System control register (SCR) Address offset: 0x10 Reset value: 0x0000 0000 The SCR controls features of entry to and exit from low power state. Reserved SLEEP SEVON SLEEP PEND DEEP Reserved Res. Res. EXIT Bits 31:5 Reserved, must be kept cleared Bit 4 SEVEONPEND Send Event on Pending bit When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. -
Page 82: Configuration And Control Register (Ccr)
Core peripherals PM0215 4.3.5 Configuration and control register (CCR) Address offset: 0x14 Reset value: 0x0000 0204 The CCR is a read-only register and indicates some aspects of the behavior of the Cortex- M0 processor. Reserved ALIGN_ ALIGN Reserved Reserved Reserved Bits 31:10 Reserved, must be kept cleared Bit 9 STKALIGN Always reads as one, indicates 8-byte stack alignment on exception entry. -
Page 83: System Handler Priority Registers (Shprx)
PM0215 Core peripherals 4.3.6 System handler priority registers (SHPRx) The SHPR2-SHPR3 registers set the priority level, 0 to 192, of the exception handlers that have configurable priority. SHPR2-SHPR3 are word accessible. To access the system exception priority level using CMSIS, use the following CMSIS functions (where the input parameter IRQn is the IRQ number): ●... -
Page 84: Scb Usage Hints And Tips
Core peripherals PM0215 4.3.7 SCB usage hints and tips Ensure software uses aligned 32-bit word size transactions to access all the system control block registers. 4.3.8 SCB register map The table provides shows the System control block register map and reset values. The base address of the SCB register block is 0xE000 ED00 for register described in Table Table 32. -
Page 85: Systick Timer (Stk)
PM0215 Core peripherals SysTick timer (STK) When enabled, the timer: ● counts down from the reload value to zero, ● reloads (wraps to) the value in the STK_RVR on the next clock cycle, ● then decrements on subsequent clock cycles. Writing a value of zero to the STK_RVR disables the counter on the next wrap. -
Page 86: Systick Control And Status Register (Stk_Csr)
Core peripherals PM0215 4.4.1 SysTick control and status register (STK_CSR) Address offset: 0x00 Reset value: 0x0000 0004 The SysTick CSR register enables the SysTick features. COUNT FLAG Reserved CLKSO TICK URCE ABLE Reserved Bits 31:17 Reserved, must be kept cleared. Bit 16 COUNTFLAG: Returns 1 if timer counted to 0 since last time this was read. -
Page 87: Systick Reload Value Register (Stk_Rvr)
PM0215 Core peripherals 4.4.2 SysTick reload value register (STK_RVR) Address offset: 0x04 Reset value: Unknown The STK_RVR specifies the start value to load into the STK_CVR. RELOAD[23:16] Reserved RELOAD[15:0] Bits 31:24 Reserved, must be kept cleared. Bits 23:0 RELOAD: RELOAD value Value to load into the STK_CVR when the counter is enabled and when it reaches 0. -
Page 88: Systick Calibration Value Register (Stk_Calib)
Core peripherals PM0215 4.4.4 SysTick calibration value register (STK_CALIB) Address offset: 0x0C Reset value: 0x0000000 The CALIB register indicates the SysTick calibration properties. If calibration information is not known, calculate the calibration value required from the frequency of the processor clock or external clock. -
Page 89: Table 34. Systick Register Map And Reset Values
PM0215 Core peripherals 4.4.6 SysTick register map The table provided shows the SysTick register map and reset values. The base address of the SysTick register block is 0xE000 E010. Table 34. SysTick register map and reset values Offset Register STK_CSR 0x00 Reserved Reserved... -
Page 90: Table 35. Document Revision History
Revision history PM0215 Revision history Table 35. Document revision history Date Revision Changes 27-April-2012 Initial release. 90/91 Doc ID 022979 Rev 1... - Page 91 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
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