Pwm-Related Registers; Pwm Control Register Pwmcon; Pwm Output Enable Control Register Pwmoe - Cmsemicon CMS80F731 Series Reference Manual

17.5 PWM-related Registers

PWM Control Register PWMCON

17.5.1
F120H Bit7
PWMCON --
R/W R/W
Reset value 0
Bit7
Bit6 PWMRUN:
Bit5~Bit4 PWMMODE<1:0>:
Bit3 GROUPEN:
Bit2
Bit1
Bit0

PWM Output Enable Control Register PWMOE

17.5.2
F121H Bit7
PWMOE --
R/W R/W
Reset value 0
Bit7~Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
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Bit6 Bit5
PWMRUN PWMMODE1
R/W R/W
0 0
-- Reserved, must be 0.
PWM clock pre-division, clock division enable bit;
1= Prohibition (PWMmnPSC, PWMmnDIV are cleared 0);
0= Enable.
Mode control bit of PWM;
00= Standalone mode;
01= Complementary models;
10= Synchronous mode;
11= Retain.
PWM teaming function enable bit;
1= PG0 controls PG2, PG4; PG1 controls PG3, PG5;
0= All PWM channel signals are independent of each other.
-- Reserved, must be 0.
-- Reserved, must be 0.
-- Reserved, must be 0.
Bit6 Bit5
-- PWM5OE
R/W R/W
0 0
-- Reserved, must be 0.
PWM5OE: Output enable bit of PWM channel 5;
1= Enable;
0= Disable.
PWM4OE: Output enable bit of PWM channel 4;
1= Enable;
0= Disable.
PWM3OE: Output enable bit of PWM channel 3;
1= Enable;
0= Disable.
PWM2OE: Output enable bit of PWM channel 2;
1= Enable;
0= Disable.
PWM1OE: Output enable bit of PWM channel 1;
1= Enable;
0= Disable.
PWM0OE: Output enable bit of PWM channel 0;
Bit4
PWMMODE0
R/W
0
Bit4 Bit3
PWM4OE PWM3OE
R/W R/W
0 0
/
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CMS80F731x Reference Manual
Bit3 Bit2 Bit1
GROUPEN --
R/W R/W R/W
0 0
Bit2 Bit1
PWM2OE PWM1OE
R/W R/W
0 0
Bit0
-- --
R/W
0 0
Bit0
PWM0OE
R/W
0
Rev.
1.00