Cmsemicon CMS32H6157 User Manual

Ultra-low-power 32-bit measurement soc based on the arm cortex-m0+

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CMS32H6157 User Manual

Ultra-low-power 32-bit measurement SOC based on the ARM® Cortex®-M0+

Rev. 0.1.1

Please note the following CMS IP policy

*Zhongwei Semiconductor (Shenzhen) Co., Ltd. (hereinafter referred to as the Company) has applied for a patent and enjoys absolute legal

rights and interests. The patent rights related to the Company's MCUs or other products have not been authorized to be licensed, and any

company, organization or individual who infringes the Company's patent rights through improper means will take all possible legal actions to curb

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obtained by the infringer.

＊The name and logo of Zhongwei Semiconductor (Shenzhen) Co., Ltd. are registered trademarks of the Company.

＊The Company reserves the right to further explain the reliability, functionality and design improvements of the products in the data sheet.

However, the Company is not responsible for the use of the Specification Contents. The applications mentioned herein are for illustrative

purposes only and the Company does not warrant and does not represent that these applications can be applied without further modification, nor

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Page 1 CMS32H6157 User Manual Ultra-low-power 32-bit measurement SOC based on the ARM® Cortex®-M0+ Rev. 0.1.1 Please note the following CMS IP policy *Zhongwei Semiconductor (Shenzhen) Co., Ltd. (hereinafter referred to as the Company) has applied for a patent and enjoys absolute legal rights and interests.
Page 2: Contents Document Instructions
CMS32H6157 User Manual | Chapter 1 CPU Document Instructions This manual is the user manual for the CMS32H6157 microcontroller product. The user manual is the application instruction material on how to use this series of products, including the structure, function description, working mode and register configuration of each functional module.
Page 3: Table Of Contents
CMS32H6157 User Manual | Chapter 1 CPU Contents Document Instructions ............................2 CPU ........................ 19 Overview ............................19 Cortex-M0+ core features ......................19 Debugging features ........................19 SWD interface pins ........................21 ARM reference document ......................22 PORT FUNCTION ..................23 Port general function ........................
Page 4 CMS32H6157 User Manual | Chapter 1 CPU Oscillation stabilization time selection register (OSTS) ............80 Peripheral enabled registers 0, 1 (PER0, PER1) ..............82 Subsystem clock supply mode control register (OSMC) ............85 High-speed internal oscillator frequency selection register (HOCODIV) ......86 High-speed internal oscillator trim register (HIOTRM) ............
Page 5 CMS32H6157 User Manual | Chapter 1 CPU Operation of oscillation stop detection circuit in deep sleep mode ........122 Notes on the oscillation stop detection function ..............122 GENERAL-PURPOSE TIMER UNIT TIMER8 ..........123 General-purpose timer unit functions ..................125 Independent channel operation functions ................125 Multi-channel linkage operation functions ................127...
Page 6 CMS32H6157 User Manual | Chapter 1 CPU Timer interrupt and TOmn pin output when counting starts ..........177 Control of Timer Input (TImn) ......................178 Block diagram of the TImn pin input circuit ................178 Noise filter ..........................178 Cautions for channel input operation ...................179 Independent channel operation function for general purpose timer units ........180...
Page 7 CMS32H6157 User Manual | Chapter 1 CPU Start and stop control of counting ..................245 Flag access (TEDGF bit and TUNDF bit of TACR0 register) ..........245 Access to counting registers ....................246 Change in mode ........................246 Setting procedure for TAO pin and TAIO pin ...............246 When timer A is not used .....................247...
Page 8 CMS32H6157 User Manual | Chapter 1 CPU Structure of 15-bit Interval Timer ....................278 Registers controlling 15-bit Interval Timer ..................279 Peripheral enable register 0 (PER0) ..................279 Real-time clock selection register (RTCCL) ................280 15-bit interval timer control register (ITMC) .................281 15-bit interval timer operation .....................282 15-bit interval timer operation timing..................282...
Page 9 CMS32H6157 User Manual | Chapter 1 CPU Conversion result comparison upper limit setting register (ADUL) ........311 Conversion result comparison lower limit setting register (ADLL) ........312 A/D converter sampling time control register (ADNSMP) ..........313 A/D converter sampling time extension control register (ADSMPWAIT) ......315 A/D test register (ADTES) ....................316...
Page 10 CMS32H6157 User Manual | Chapter 1 CPU Data ready/data input and output (DRDYB/DOUT) .............340 Serial input clock (SCLK) .....................340 Serial data transmission .......................341 Function configuration ......................342 Description of SPI opcode command ..................343 Cautions for SPI Communication ..................343 Related registers .........................344 Sigma-Delta ADC control register 1..................344...
Page 11 CMS32H6157 User Manual | Chapter 1 CPU Output of comparator n (n=0, 1) ..................373 Stopping or Supplying comparator clock ................374 OPERATIONAL AMPLIFIER (OPA) ............375 Function of operational amplifier ....................375 Register of operational amplifier ....................376 Peripheral enable register 1 (PER1) ..................376 Operational amplifier control register (OPACTL) ..............377...
Page 12 CMS32H6157 User Manual | Chapter 1 CPU Master reception ........................421 Master transmission and reception ..................429 Slave transmission .......................437 Slave reception ........................445 Slave transmission and reception ..................451 Calculation of transmission clock frequency ................460 Procedure for handling errors during 3-wire serial I/O communication (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) .........................462...
Page 13 CMS32H6157 User Manual | Chapter 1 CPU Transmit buffer register (SOTB) ..................552 Receive buffer register (SIO) ....................552 Operation of SPI ..........................553 Master tramission and reception ..................554 Master reception ........................557 Slave transmission and reception ..................560 Slave reception ........................563 SERIAL INTERFACE IICA ................566 Function of IICA ..........................566...
Page 14 CMS32H6157 User Manual | Chapter 1 CPU Start condition ........................591 Address ..........................592 Designation of transmission direction ..................592 ACK ............................593 Stop Condition ........................594 Await .............................595 Method of release from wait state ..................597 Generation timing and waiting control of interrupt requests (INTIICAn) ......598 Detection method for address matching ................599...
Page 15 CMS32H6157 User Manual | Chapter 1 CPU 20.3.7 LCD port function register ....................678 20.4 LCD display data register ......................679 20.5 LCD display register selection ....................681 20.5.1 Data display in graphic area A and graphic area B .............682 20.5.2 Blinking display (alternate display of data in graph area A and graph area B) ....682 20.6 LCD drive voltage provided by V...
Page 16 CMS32H6157 User Manual | Chapter 1 CPU 21.5.6 Operation in standby mode ....................720 LINKAGE CONTROLLER (EVENTC) ............721 Function of EVENTC ........................721 Structure of EVENTC ........................721 Control register ..........................722 Output target selection register n(ELSELRn)(n=00~15) .............723 Operation of EVENTC .........................726 INTERRUPT FUNCTION ................728 23.1 Types of interrupt function ......................728...
Page 17 CMS32H6157 User Manual | Chapter 1 CPU VOLTAGE DETECTION CIRCUIT ............... 763 Function of voltage detection circuit ...................763 Structure of voltage detection circuit ...................764 Registers for controlling voltage detection circuit ...............765 Voltage detection register (LVIM) ..................765 Voltage detection level register (LVIS) ................766 Operation of voltage detection circuit ..................769...
Page 18 CMS32H6157 User Manual | Chapter 1 CPU Internal reference voltage ......................801 VDD calibration data register VDDCDR ................801 Instructions for using the internal reference voltage ............801 OPTION BYTES ..................802 Function of option bytes ......................802 User option bytes (000C0H~000C2H) .................802 Flash data protection option bytes (000C3H, 500004H) .............803 Format of the user option bytes ....................804...
Page 19: Cpu
CMS32H6157 User Manual | Chapter 1 CPU Overview This chapter provides a brief introduction to the features and debugging features of the ARM Cortex-M0+ core. For details, please refer to the ARM related documentation. Cortex-M0+ core features ⚫ ARM Cortex-M0+ processor is a 32-bit RISC core with a 2-stage pipeline that supports privileged and user modes ⚫...
Page 20 CMS32H6157 User Manual | Chapter 1 CPU Figure 1-1: Debug block diagram of Cortex-M0+ MCU Debug Support Cortex-M0+ Debug Support Cortex-M0+ System bus Core Bus matrix Bridge DBGMCU SWDIO SW-DP SWCLK NVIC Debug AP Notice: SWD does not work in deep sleep mode, please do debug operation in active and sleep mode.
Page 21: Swd Interface Pins
CMS32H6157 User Manual | Chapter 1 CPU SWD interface pins The 2 GPIOs of this product can be used as SWD interface pins, which are present in all packages. Table 1-1: SWD debug port pins SWD port name Debugging functions...
Page 22: Arm Reference Document
CMS32H6157 User Manual | Chapter 1 CPU ARM reference document The built-in debugging features in the Cortex®-M0+ kernel are part of the ARM® CoreSight design suite. For documentation, refer to: Cortex®-M0+ Technical Reference Manual (TRM) ⚫ ARM® Debug Interface V5 ⚫...
Page 23: Port Function
CMS32H6157 User Manual | Chapter 2 Port Function Port Function Port general function The general purpose I/O ports (GPIO) for this product are PA00~PA15, PB00~PB15, PC00~PC12, PD02~PD09, and PH00~PH04. The general purpose I/O ports used vary by product model, so please refer to the datasheet for each product series for details.
Page 24: Port Multiplexing Function
CMS32H6157 User Manual | Chapter 2 Port Function Port multiplexing function In addition to supporting general-purpose GPIO functions, each port can also be multiplexed as a function port for peripheral modules. Such as input and output signals of analog module ADC/DAC/CMP/AMP/ LCD, input and output signals of digital function modules (such as SPI, UART, I Timer, etc.).
Page 25 CMS32H6157 User Manual | Chapter 2 Port Function Table 2-2: List of multiplexing functions by port Port function configuration Default Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function PA00 TXD2/SDO20 TI00 TO00 VC0OUT...
Page 26 CMS32H6157 User Manual | Chapter 2 Port Function Port function configuration Default Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function PC00 SS21 TI00 TO00 TI03_GATE TA_TI/ PC01 SCLK21/SCL21 TI01/TO01 TA_TO PC02 SDI21/SDA21 TI02/TO02...
Page 27: Registers For Controlling Port Functions
CMS32H6157 User Manual | Chapter 2 Port Function Registers for controlling port functions The port function is controlled through the following registers. • Port Output Control Register (PMxx) • Port Register (Pxx) • Pull-up resistor selection register (PUxx) • Pull-down resistor selection register (PDxx) •...
Page 28 CMS32H6157 User Manual | Chapter 2 Port Function Bit Name Port PMxx PSETxx PCLRxx PUxx PDxx POMxx PREADxx PMCxx Register Register Register Register Register Register Register Register Register PMB0 PSETB0 PCLRB0 PUB0 PDB0 POMB0 PREADB0 PMCB0 PMB1 PSETB1 PCLRB1 PUB1...
Page 29: Port Output Control Register (Pmxx)
CMS32H6157 User Manual | Chapter 2 Port Function Port output control register (PMxx) When the port is used as a digital channel, this is the register that sets whether its output is enabled or not in bit units. After a reset signal is generated, each port defaults to the input state. When the port is used as a multiplexed port, it must be set as described in "2.5 Register settings when using the multiplexing function".
Page 30: Port Register (Pxx)
CMS32H6157 User Manual | Chapter 2 Port Function Port register (Pxx) This register is used to set the value of the output latch for each port. Reading this register when PMxx is 0 gives the value of the output latch of the corresponding port, while reading this register when PMxx is 1 gives the port level of the corresponding port.
Page 31: Port Set Control Register (Psetxx)
CMS32H6157 User Manual | Chapter 2 Port Function Port set control register (PSETxx) This is the register to set the port output latch in bit units. After a reset signal is generated, the value of these registers becomes "0000H". Register address = base address + offset address; the base address of Port Set Control Register is 0x40040000, and the offset address is shown in the figure below.
Page 32: Port Clear Control Register (Pclrxx)
CMS32H6157 User Manual | Chapter 2 Port Function Port clear control register (PCLRxx) This is the register to set the port output latch in bit units. After a reset signal is generated, the value of these registers becomes "0000H". Register address = base address + offset address; the base address of Port Clear Control Register is 0x40040000, and the offset address is shown in the figure below.
Page 33: Pull-Up Resistor Selection Register (Puxx)
CMS32H6157 User Manual | Chapter 2 Port Function Pull-up resistor selection register (PUxx) Pull-up resistor selection register. Setting this register allows the port in input mode (PMmn=1) or in N-channel open drain output mode to be pulled up by using an internal pull-up resistor in bit units. For ports set to output mode, independent of the pull-up resistor selection register setting, no internal pull-up resistor is connected.
Page 34: Pull-Down Resistor Selection Register (Pdxx)
CMS32H6157 User Manual | Chapter 2 Port Function Pull-down resistor selection register (PDxx) Internal pull-down resistor selection register. Setting this register allows the port in input mode (PMmn=1) to be pulled down by using an internal pull-down resistor in bit units. For ports set to output mode, independent of the pull- down resistor selection register setting, no internal pull-down resistor is connected.
Page 35: Port Output Mode Register (Pomxx)
CMS32H6157 User Manual | Chapter 2 Port Function Port output mode register (POMxx) This is a register for setting the output mode in bit units. The N-channel open drain output mode is selected for serial communication with external devices of different potentials and for I C communication with external devices of the same potential.
Page 36: Port Mode Control Register (Pmcxx)
CMS32H6157 User Manual | Chapter 2 Port Function Port mode control register (PMCxx) The PMC register sets the port in bit units for use as an analog channel or for other functions, which include digital port functions and LCD port functions.
Page 37: Port Readback Register (Preadxx)
CMS32H6157 User Manual | Chapter 2 Port Function Port readback register (PREADxx) This is a read-only register and the port level can be obtained by reading this register when the port is used as a digital port. Register address = base address + offset address; the base address of Port register is 0x40040000, and the offset address is shown in the figure below.
Page 38: Port Multiplexing Function Configuration Register (Pxxcfg)
CMS32H6157 User Manual | Chapter 2 Port Function Port multiplexing function configuration register (PxxCFG) The port multiplexing function configuration registers enables redirecting the digital input and output functions of peripheral modules to different ports. Each port corresponds to a port multiplexing function configuration register. The default function of ports other than PH00, PA13, PA14 is GPIO function after reset.
Page 39 CMS32H6157 User Manual | Chapter 2 Port Function Table 2-5: List of port multiplexing function configuration registers Base Address Offset Address Register Name Bit Width Reset Value 0x000 PA00CFG[2:0] 0x001 PA01CFG[2:0] 0x002 PA02CFG[2:0] 0x003 PA03CFG[2:0] 0x004 PA04CFG[2:0] 0x005 PA05CFG[2:0] 0x006...
Page 40 CMS32H6157 User Manual | Chapter 2 Port Function Base Address Offset Address Register Name Bit Width Reset Value 0x020 PC00CFG[2:0] 0x021 PC01CFG[2:0] 0x022 PC02CFG[2:0] 0x023 PC03CFG[2:0] 0x024 PC04CFG[2:0] 0x025 PC05CFG[2:0] 0x026 PC06CFG[2:0] 0x027 PC07CFG[2:0] 0x028 PC08CFG[2:0] 0x029 PC09CFG[2:0] 0x02a PC10CFG[2:0]...
Page 41: External Interrupt Port Selection Register (Intpnpcfg)
CMS32H6157 User Manual | Chapter 2 Port Function External interrupt port selection register (INTPnPCFG) This product supports 6 external interrupts INTP0~5, and each external interrupt can be redirected to multiple ports. By configuring the external interrupt port selection register (INTPnPCFG), the input function of INTPn can be redirected to a different port.
Page 42 CMS32H6157 User Manual | Chapter 2 Port Function Register Name Register Configuration INTP1 port selection 4'h0(default) PB00 4'h1 PB01 4'h2 PB02 4'h3 PB03 INTP1PCFG 4'h4 PB04 4'h5 PB05 4'h6 PB06 4'h7 PB07 Register Name Register Configuration INTP2 port selection 4'h0(default)
Page 43 CMS32H6157 User Manual | Chapter 2 Port Function Register Name Register Configuration INTP4 port selection 4'h0(default) PC14 4'h1 PD04 4'h2 PD05 INTP4PCFG 4'h3 PD06 4'h4 PD07 4'h5 PD08 4'h6 PD09 Register Name Register Configuration INTP5 port selection 4'h0(default) PD03 4'h1...
Page 44: External Reset Port Mask Register (Rstm)
CMS32H6157 User Manual | Chapter 2 Port Function External reset port mask register (RSTM) PH00 (RESETB) is used as an external reset input port by default, and system reset occurs when it is at low level. When you need to use the GPIO function of PH00, you need to configure the register RSTM to mask its external reset function first.
Page 45: Handling Of Unused Ports
CMS32H6157 User Manual | Chapter 2 Port Function Handling of unused ports The processing of each unused port isTable 2-7as follows. Table 2-7: Handling of each unused port Port name Recommended connection method when not in use PA00~PA15 PB00~PB15 Input: Connect to EV or EV via separate resistor.
Page 46: Register Settings When Using The Multiplexing Function
CMS32H6157 User Manual | Chapter 2 Port Function Register settings when using the multiplexing function Basic ideas when using multiplexing functions Firstly, for ports with analogue functions, the Port Mode Control Register (PMCxx) sets whether the port is to be used for analogue or other functions.
Page 47 CMS32H6157 User Manual | Chapter 2 Port Function Configuration methods of the multiplexing function Table 2-10: Configuration methods of the multiplexing function Port Function Register Settings Func Func Functio Port Port tion tion Function Function Function Default Function 5 Name...
Page 48 CMS32H6157 User Manual | Chapter 2 Port Function OPA0_DA SEG19 channel Digital Configure according to GPIO general requirements Multiplex TXD1/ ed output SDO10 type AND Multiplex ed output type OR Multiplex TI04 SPI0_NSS × × ed output Rev.0.1.1 www.mcu.com.cn 48 / 822...
Page 49 CMS32H6157 User Manual | Chapter 2 Port Function Port Function Register Settings Functi Functi Port Function Function Function Default on 2 on 3 Function 4 Function 5 Mode Functi Function Functi Functi Function Function Function Function Function ANI05 VC0_INN2 Analog ×...
Page 50 CMS32H6157 User Manual | Chapter 2 Port Function COM1 channel Configure Digital GPIO according to general requirements Multiplexe RXD0/S TI03_GAT TI02 × × d output DI00 Multiplexe bidirection SDAA Open- drain PA10 output type OR Multiplexe bidirection SDA00 Open- drain...
Page 51 CMS32H6157 User Manual | Chapter 2 Port Function Port Function Register Settings Functi Functi Functi Port Function Function Default on 1 on 2 on 3 Function 4 Function 5 Mode Functi Function Functi Functi Functi Function Function Function Function COM2...
Page 52 CMS32H6157 User Manual | Chapter 2 Port Function ANI08/ Analog AVREF × × × Channel SEG13 channel Digital Configure according GPIO general to requirements PB00 Multiplexe TXD1/ d output SDO1 type AND Multiplexe PCLBUZ d output TO00 type OR Multiplexe TI00 ×...
Page 53 CMS32H6157 User Manual | Chapter 2 Port Function Port Function Register Settings Port Functi Functi Functi Port Function Function Default on 1 on 2 on 3 Function 4 Function 5 Mode Functi Function Functio Functi Functi Function Function Function Function...
Page 54 CMS32H6157 User Manual | Chapter 2 Port Function drain output type OR Multiplex TO06 TA_TO output type OR Multiplex TXD0/ output SDO0 type Multiplex TI06 TA_TI × × output channel Digital Configure according GPIO general to requirements Multiplex TO07 TA_TON...
Page 55 CMS32H6157 User Manual | Chapter 2 Port Function Port Function Register Settings Functi Functi Port Port Function Function Function ction Default on 2 on 3 Function 5 Name Mode Functi Functi Functi Function Function Function Function Function ction channel Digital...
Page 56 CMS32H6157 User Manual | Chapter 2 Port Function drain output type OR Multiplex bidirectio Open- SDA10 drain output type Multiplex RxD1/ TI00_GA TI03 × × SDI10 output Analog ANI13 × × × Channel VC1_INP3 SEG0 channel Digital Configure according GPIO...
Page 57 CMS32H6157 User Manual | Chapter 2 Port Function Port Function Register Settings Port Functio Funct Functio Port Function Function Function Default ion 3 Function 5 Mode Functio PMxx Function Functio Funct Function Functio Function Function Function Analog ANI14 × ×...
Page 58 CMS32H6157 User Manual | Chapter 2 Port Function Multiplexe SCLK21/ d output SCL21 type AND Multiplexe d output TO01 TA_TO type OR Multiplexe SCLK21 TI01 TA_TI × × d output Rev.0.1.1 www.mcu.com.cn 58 / 822...
Page 59 CMS32H6157 User Manual | Chapter 2 Port Function Port Function Register Settings Port Function Function Function Function Function Function Function Port Mode Default Name PMCxx PMxx POMxx Function Function Function Function Function Function Function Function Function ANI19 Analog × ×...
Page 60 CMS32H6157 User Manual | Chapter 2 Port Function Open-drain output type Multiplexed SDI01 TI07 × × output Rev.0.1.1 www.mcu.com.cn 60 / 822...
Page 61 CMS32H6157 User Manual | Chapter 2 Port Function Port Function Register Settings Port Functio Functio Functio Functio Functio Functio Functio Default Port Mode PMCx POMx Functio Functio Functio Functio Functio Functio Functio Functio Functio SEG37 channel Digital Configure according to...
Page 62 CMS32H6157 User Manual | Chapter 2 Port Function Port Function Register Settings Port Function Function Function Function Function Function Port Mode Default Function 5 Name PMCxx PMxx POMxx Function Function Function Function Function Function Function Function Function SEG03/ LCD channel...
Page 63 CMS32H6157 User Manual | Chapter 2 Port Function Port Function Register Settings Port Functio Functio Functio Functio Functio Functio Functio Default Port Mode PMCx POMx Functio Functio Functio Functio Functio Functio Functio Functio Functio channel Digital Configure according to GPIO...
Page 64 CMS32H6157 User Manual | Chapter 2 Port Function Configuration Description: ➢ PA00~PA07, PB00~PB03, PB10~PB15, PC00~PC06, PD04, PD05, PD08, PD09 are used as analog ports by default after power on. If they are to be used for digital general purpose GPIO or digital multiplexing function, the ports need to be configured to digital mode (PMCxx=0).
Page 65: System Structure
CMS32H6157 User Manual | Chapter 3 System Structure System Structure Overview This product system consists of the following components: • 2 AHB buses Master: Cortex-M0+ Enhanced DMA • 4 AHB buses Slaves: FLASH Storage SRAM Memory 0 SRAM Memory 1...
Page 66: System Address Division
CMS32H6157 User Manual | Chapter 3 System Structure System address division Figure3-2: Address division diagram FFFF_FFFFH Reserved E00F_FFFFH Cortex-M0+ dedicated peripheral resource area E000_0000H Reserved 4005_FFFFH Peripherals Resource Area 4000_0000H Reserved 2000_1FFFH SRAM(up to 8KB) 2000_0000H Reserved 0050_0BFFH Data Flash 2.5KB...
Page 67: Peripheral Address Assignment
CMS32H6157 User Manual | Chapter 3 System Structure Peripheral address assignment Figure3-1: Start address of the peripheral register group Start Address Peripheral Remark 0x4000_0000 - 0x4000_4FFF Retain 0x4000_5000 - 0x4000_5FFF 0x4000_6000 - 0x4000_6FFF Interrupt control 0x4000_7000 - 0x4001_8FFF Retain 0x4001_9000 - 0x4001_AFFF...
Page 68: Clock Generation Circuit
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Clock generation circuit Function of clock generation circuit The clock generation circuit is the circuit that provides the clock to the CPU and peripheral hardware. There are the following 3 types of system clocks and clock oscillation circuits.
Page 69 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Note: The low-speed internal oscillator clock (F ) can be selected as the count clock for the real-time clock only when the fixed-cycle interrupt function is used. Remarks: F : X1 clock oscillation frequency : High-speed internal oscillator clock frequency (max.
Page 70: Structure Of Clock Generation Circuit
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Structure of clock generation circuit The clock generation circuit consists of the following hardware. Table 4-1: Structure of the clock generation circuit Item Structure Clock operation mode control register (CMC) System Clock Control Register (CKC)
Page 71 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Figure4-1: Block diagram of the clock generation circuit Rev.0.1.1 www.mcu.com.cn 71 / 822...
Page 72 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Remarks: FX : X1 clock oscillation frequency : High-speed internal oscillator clock frequency (max. 32MHz) HOCO : High-speed internal oscillator clock frequency (max. 32MHz) : External main system clock frequency : High-speed system clock frequency...
Page 73: Registers For Controlling Clock Generation Circuit
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Registers for controlling clock generation circuit The clock generation circuit is controlled through the following registers. • Clock operation mode control register (CMC) • System Clock Control Register (CKC) • Clock operation status control register (CSC) •...
Page 74 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Figure4-2: Format of the Clock Operation Mode Control Register (CMC) Address: 40020400H After reset: 00H Symbol Note Note Note Note EXCLK OSCSEL EXCLKS OSCSELS AMPHS1 AMPHS0 High-speed system clock Bit7~ Bit6...
Page 75: System Clock Control Register (Ckc)
CMS32H6157 User Manual | Chapter 4 Clock generation circuit System clock control register (CKC) This is the register that selects the CPU/peripheral hardware clock and the main system clock. The CKC register is set by an 8-bit memory manipulation instruction.
Page 76: Clock Operation Status Control Register (Csc)
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Clock operation status control register (CSC) This is the register that controls the operation of the high-speed system clock, the high-speed internal oscillator clock, and the subsystem clock (except the low-speed internal oscillator clock). The CSC register is set by an 8-bit memory manipulation instruction.
Page 77 CMS32H6157 User Manual | Chapter 4 Clock generation circuit speed system clock. External main system clock (CLS=0 and MCS=0, or CLS=1) CPU/peripheral hardware clock runs at a clock other than the XT1 Clock subsystem clock. XTSTOP=1 External subsystem clock (CLS=0)
Page 78: Status Register Of The Oscillation Stabilization Time Counter (Ostc)
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Status register of the oscillation stabilization time counter (OSTC) This is the register that indicates the count status of the oscillation stabilization time counter of the X1 clock. It can confirm the oscillation stabilization time of X1 clock in the following cases: •...
Page 79 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Figure4-5: Format of the status register (OSTC) of the oscillation stabilization time counter Address: 40020402H After reset: Symbol OSTC MOST8 MOST9 MOST10 MOST11 MOST13 MOST15 MOST17 MOST18 Bit7~Bit0 OSTC: Oscillation stabilization time state...
Page 80: Oscillation Stabilization Time Selection Register (Osts)
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Oscillation stabilization time selection register (OSTS) This is a register that selects the oscillation stabilization time of X1 clock. If the X1 clock is made to oscillate, it automatically waits for the time set in the OSTS register after the X1...
Page 81 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Deep sleep mode released X1pin of Voltage waveform Remarks: FX : X1 clock oscillation frequency Rev.0.1.1 www.mcu.com.cn 81 / 822...
Page 82: Peripheral Enabled Registers 0, 1 (Per0, Per1)
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Peripheral enabled registers 0, 1 (PER0, PER1) This is a register that sets a clock that is enabled or disabled for each peripheral hardware. Reduce power consumption and noise by stopping clocks to hardware that is not in use.
Page 83 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Provides input clock. • The SFR used by Universal Serial Communication Unit 1 can be read and written. Bit2 SCI0EN: Provides control of the input clock of Universal Serial Communication Unit 0 Stop providing input clock.
Page 84 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Figure4-8: Format of peripheral enabled register 1 (PER1) Address: 4002081AH After reset: Symbol PER1 OPAEN CMPEN DACEN ADCEN OSDCEN DMAEN SPIHSEN Bit7 OPAEN: Provides control of the input clock of the OPA Stop providing input clock.
Page 85: Subsystem Clock Supply Mode Control Register (Osmc)
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Subsystem clock supply mode control register (OSMC) OSMC registers are registers that reduce power consumption by stopping unneeded clock functions. If RTCLPC bit set to "1", it stops providing clock to peripheral functions other than the real-time clock and 15-bit interval timer in deep sleep mode or sleep mode where the CPU runs on the subsystem clock, thus reducing power consumption.
Page 86: High-Speed Internal Oscillator Frequency Selection Register (Hocodiv)
CMS32H6157 User Manual | Chapter 4 Clock generation circuit High-speed internal oscillator frequency selection register (HOCODIV) This is a register that changes the high-speed internal oscillator frequency set by the option byte (000C2H). The HOCODIV register is set by an 8-bit memory manipulation instruction.
Page 87: High-Speed Internal Oscillator Trim Register (Hiotrm)
CMS32H6157 User Manual | Chapter 4 Clock generation circuit High-speed internal oscillator trim register (HIOTRM) This is a register to correct the accuracy of the high-speed internal oscillator. It can be used for self-measurement and accuracy correction of the high-speed internal oscillator frequency using a timer with high-precision external clock input, etc.
Page 88: Subsystem Clock Selection Register (Subcksel)
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Subsystem clock selection register (SUBCKSEL) The SUBCKSEL register is the register for selecting the subsystem clock F and the low-speed internal oscillator clock F and for selecting the low-speed internal oscillator clock frequency.
Page 89: System Clock Oscillation Circuit
CMS32H6157 User Manual | Chapter 4 Clock generation circuit System clock oscillation circuit X1 oscillation circuit The X1 oscillator circuit is oscillated by a crystal resonator or ceramic resonator (1~20MHz) connected to pins X1 and X2. An external clock can also be input, where a clock signal must be input to the EXCLK pin.
Page 90: Xt1 Oscillation Circuit
CMS32H6157 User Manual | Chapter 4 Clock generation circuit XT1 oscillation circuit The XT1 oscillation circuit is oscillated by a crystal resonator (32.768KHz (typical)) connected to the XT1 pin and XT2 pin. When using the XT1 oscillation circuit, bit 4 (OSCSELS) of the clock operation mode control register (CMC) must be set to "1"...
Page 91 CMS32H6157 User Manual | Chapter 4 Clock generation circuit An incorrect example of a resonator connection is shown inFigure. Figure4-15: Example of incorrect resonator connection (1/2) (a) The wiring connecting the circuit is too long (b)Signal lines are crossed (cX1 and X2 signal lines cross wiring...
Page 92 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Figure4-15: Example of incorrect resonator connection (2/2) (f) Current flows along grounding of oscilation circuit (e) varying high current source close to singal lines (Point A, B, C has difference in electric potential)
Page 93: High-Speed Internal Oscillator
CMS32H6157 User Manual | Chapter 4 Clock generation circuit High-speed internal oscillator The CMS32H6157 has a built-in high-speed internal oscillator. The frequency can be selected from 32MHz, 16MHz, 12MHz, 8MHz, 6MHz, 4MHz, 3MHz, 2MHz and 1MHz by the option byte (000C2H). The oscillation can be controlled by bit0 (HIOSTOP) of the clock operation status control register (CSC).
Page 94: Operation Of Clock Generation Circuit
: CPU/peripheral hardware clock After the CMS32H6157 is released from reset, the CPU starts to operate through the output of the high-speed internal oscillator. The operation of the clock generation circuit when power is turned on is shown in Figure.
Page 95 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Figure4-16: Operation of the clock generation circuit when the power is turned on at least 10us low limit of working voltage range voltage of power source (V power on reset signal...
Page 96: Clock Control
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Clock control Example of setting up a high-speed internal oscillator After the reset is released, the CPU/peripheral hardware clock (F ) must run as the high-speed internal oscillator clock. The frequency of the high-speed internal oscillator can be selected from 32MHz, 16MHz, 8MHz, 4MHz, 2MHz, and 1MHz by using the FRQSEL0 to FRQSEL4 bits of the option byte (000C2H).
Page 97 CMS32H6157 User Manual | Chapter 4 Clock generation circuit 【Setting of high-speed internal oscillator frequency selection register (HOCODIV)】 Address: 0x40021C20 Symbol HOCODIV HOCODIV2 HOCODIV1 HOCODIV0 Bit2~Bit0 HOCODIV＜2:0＞: High-speed internal oscillator frequency 000= =32MHz HOCO =32MHz 001= =32MHz HOCO =16MHz 010=...
Page 98: Example Of Setting X1 Oscillation Circuit
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Example of setting X1 oscillation circuit After the reset is released, the CPU/peripheral hardware clock (F ) must run as the high-speed internal oscillator clock. Thereafter, if the X1 oscillation clock is changed, the setting of the oscillation circuit and the control...
Page 99: Example Of Setting Xt1 Oscillation Circuit
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Example of setting XT1 oscillation circuit After the reset is released, the CPU/peripheral hardware clock (F ) must run as the high-speed internal oscillator clock. Thereafter, if changed to the XT1 oscillation clock, the oscillation circuit is set and the oscillation...
Page 100: Cpu Clock State Transition Diagram
CMS32H6157 User Manual | Chapter 4 Clock generation circuit CPU clock state transition diagram The CPU clock state transition diagram of this product is as shown in Figure. Figure4-17: CPU Clock State Transition Diagram Power on X1 oscilation / EXCLK input: stop (input port mode)
Page 101 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Examples of CPU clock transfer and SFR register setting are inTable 4-3. Table 4-3: Examples of CPU clock transfer and SFR register set-up (1/5) (1) After the reset (A) is released, the CPU is transferred to the high speed internal oscillator clock to operate (B).
Page 102 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Table 4-3: Examples of CPU clock transfer and SFR register set-up (2/5) (4) The CPU moves from high-speed internal oscillator clock operation (B) to high-speed system clock operation (C). (SFR register setting order)
Page 103 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Table 4-3: Examples of CPU clock transfer and SFR register set-up (3/5) (6) The CPU moves from high-speed system clock operation (C) to high-speed internal oscillator clock operation (B). (SFR register setting order)
Page 104 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Table 4-3: Examples of CPU clock transfer and SFR register set-up (4/5) (9) The CPU moves from subsystem clock operation (D) to high-speed system clock operation (C). (SFR register setting order)
Page 105 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Table 4-3: Examples of CPU clock transfer and SFR register set-up (5/5) (11) The CPU moves from high-speed internal oscillator clock operation (B) to deep sleep mode (H). The CPU moves from high-speed system clock operation (C) to deep sleep mode (I).
Page 106: Conditions Before Cpu Clock Transfer And Post-Transfer Processing
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Conditions before CPU clock transfer and post-transfer processing The conditions before the CPU clock transfer and the processing after the transfer are shown below. Table4-4: Transfer of CPU clocks (1/2) CPU Clock...
Page 107 CMS32H6157 User Manual | Chapter 4 Clock generation circuit Table 4-4: Transfer of CPU clocks (2/2) CPU Clock Conditions before transfer Post-transfer processing Before After Transfer Transfer High-speed High-speed internal oscillator is oscillating internal oscillator and selecting high-speed internal The oscillator clock is used as the main system clock.
Page 108: Time Required To Switch Cpu Clock And Main System Clock
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Time required to switch CPU clock and main system clock It can switch CPU clock (main system clock↔sub system clock) and main system clock (high speed internal oscillator clock↔high speed system clock) by setting bit6 and bit4 (CSS, MCM0) of system clock control register.
Page 109: Conditions Before Clock Oscillation Stops
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Conditions before clock oscillation stops The register flag settings for stopping clock oscillations (invalid external clock input) and the conditions before stopping are as follows. Table 4-10: Conditions and flag settings before clock oscillation stops...
Page 110: High-Speed Internal Oscillation Correction
CMS32H6157 User Manual | Chapter 4 Clock generation circuit High-speed internal oscillation correction High-speed internal oscillation self-adjustment function This function measures the frequency of the high-speed internal oscillator using the subsystem clock F (32.768KHz) or the main system clock F...
Page 111: Register Description
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Register description Table 4-12 is the list of registers used for the high-speed internal oscillation frequency correction function. Table 4-12: High-speed internal oscillation frequency correction function register Item Structure Control register...
Page 112 CMS32H6157 User Manual | Chapter 4 Clock generation circuit frequency correction completion interrupt is generated by F . After writing 0 to FCST bit (high-speed HOCO internal oscillation frequency correction circuit operation is stopped), writing 1 to FCST bit (high-speed...
Page 113: Action Description
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Action description Action summary The high speed internal oscillator frequency correction function generates a correction cycle based on the subsystem clock (F ) or the main system clock (F ), measures the frequency of the high speed internal oscillator, and corrects the frequency accuracy of the high speed internal oscillator in real time.
Page 114 CMS32H6157 User Manual | Chapter 4 Clock generation circuit (1) Continuous action mode In continuous action mode, the high speed internal oscillator clock frequency correction action is always performed. The FCMD bit of the HOCOFC register is set to 0, which means continuous action mode.
Page 115 CMS32H6157 User Manual | Chapter 4 Clock generation circuit (2) Interval action mode In interval action mode, high-speed internal oscillator clock frequency correction is performed intermittently using timer interrupts, etc. The FCMD bit of the HOCOFC register is set to 1, which means that the interval action mode is set.
Page 116: Action Setting Flow
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Action setting flow The action start/stop flow when using the high-speed internal oscillator clock frequency correction function is shown in the figure below Figure 4-23: Action mode setting flow (example) ＜Continuous action mode＞...
Page 117: Notes On Use
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Notes on use SFR Access Regarding the control of the FCST bit during interval action mode, when writing a 1 to the FCST bit, you must first confirm that the current FCST bit is 0 before writing a 1 to it. Due to the hardware clear priority, when writing a 1...
Page 118: Oscillation Stop Detection Circuit
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Oscillation stop detection circuit The oscillation stop detection function uses the internal low-speed oscillation clock (F ) to monitor the action state of the main system clock (F ) or the sub-system clock (F...
Page 119: The Registers Used By The Oscillation-Stop Detection Circuit
CMS32H6157 User Manual | Chapter 4 Clock generation circuit The registers used by the oscillation-stop detection circuit Peripheral enabled Register 1(PER1) When using the oscillation-stop detection circuit, the bit4 (OSDCEN) of PER1 must be set to 1. Registers are described in "4.3.6 Peripheral enabled registers 0, 1 (PER0, PER1)”.
Page 120: Oscillation Stop Detection Mode Register (Scmmd)
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Oscillation stop detection mode register (SCMMD) The Oscillation Stop Detection Mode Register (SCMMD) is a register that selects the object of oscillation stop detection as the main system clock (F ) or the subsystem clock (F ), and whether the action after the oscillation stop is detected is to generate a reset or an interrupt.
Page 121: Operation Of Oscillation Stop Detection Circuit
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Operation of oscillation stop detection circuit Operation method of oscillation stop detection circuit After the external reset is released, the main system clock (F )/subsystem clock (F ) starts to oscillate.
Page 122: Operation Of Oscillation Stop Detection Circuit In Deep Sleep Mode
CMS32H6157 User Manual | Chapter 4 Clock generation circuit Operation of oscillation stop detection circuit in deep sleep mode If the oscillation stop detection circuit is enabled before entering deep sleep, the oscillation stop detection function will be switched off automatically after entering deep sleep, and the oscillation stop detection function will be switched on again after the standby release signal comes.
Page 123: General-Purpose Timer Unit Timer8
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 General-purpose timer unit Timer8 This product is equipped with a general-purpose timer unit Timer8, containing 8 channels. The number of channels of the timer unit varies from product to product.
Page 124 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 For details of each function, please refer to the following table. Independent channel operation functions Multi-channel linkage operation functions • Interval timer (refer to 5.8.1) • Single trigger pulse output (refer to 5.9.1) •...
Page 125: General-Purpose Timer Unit Functions
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 General-purpose timer unit functions The general-purpose timer unit has the following functions: Independent channel operation functions Independent channel operation function is the function that can use any channel independently without being affected by the operation mode of other channels.
Page 126 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 (6) Measurement of the high and low level width of the input signal The high and low level width of the input signal is measured by starting the count on one edge of the input signal at the timer input pin (TImn) and capturing the count value on the other edge.
Page 127: Multi-Channel Linkage Operation Functions
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Multi-channel linkage operation functions The multi-channel linked operation function is a combination of a master channel (the reference timer for the master control cycle) and a slave channel (a timer that operates in compliance with the master channel).
Page 128 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Comparision interrupt singnal operation Clock operation (INTTmn) channel N (master control) Comparision timer output operation (TOmp) channel P (slave) duty cycle period Comparision timer output operation (TOmq) channel q (slave)
Page 129: Lin-Bus Support Function (Channel 3 Only)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 LIN-bus support function (channel 3 only) The received signal in the LIN-bus communication is checked by the general-purpose timer unit to see if it fits the LIN-bus communication table. (1) Detection of wake-up signals The low level width is measured by starting a count on the falling edge of the input signal at the UART0 serial data input pin (RxD0) and capturing the count value on the rising edge.
Page 130: Structure Of The General-Purpose Timer Unit
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Structure of the general-purpose timer unit The general-purpose timer unit consists of the following hardware. Table 5-1: Structure of the general-purpose timer unit Item Structure Counter Timer Count Register mn (TCRmn)
Page 131 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 The block diagram of the general-purpose timer unit is shown in Figure 5-1. Figure 5-2: Overall block diagram of the general-purpose timer （ TPS0 ） Timer clock selection register 0 PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 （...
Page 132: General-Purpose Timer Unit Register List
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 General-purpose timer unit register list Register base address: 0x40043000 Offset Address Register Name Bit Width Reset Value 0x000 TCR00 FFFFH 0x002 TCR01 FFFFH 0x004 TCR02 FFFFH 0x006 TCR03 FFFFH 0x008...
Page 133: Timer Count Register Mn (Tcrmn)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer count register mn (TCRmn) The TCRmn register is a 16-bit read-only register that counts the count clock. The count is incremented or decremented synchronously with the rising edge of the count clock.
Page 134 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 As shown below, the read values of the TCRmn register vary depending on the operating mode and operating state. Figure5-2: The read value of the Timer Count Register mn (TCRmn) in each operating mode...
Page 135: Timer Data Register Mn (Tdrmn)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer data register mn (TDRmn) This is a 16-bit register that can be switched between capture and comparison functions. The operation mode is selected via the MDmn3 to MDmn0 bits of the Timer Mode Register mn (TMRmn) for switching between the capture and comparison functions.
Page 136: Registers That Control The General-Purpose Timer Unit
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Registers that control the general-purpose timer unit The registers that control the general-purpose timer unit are as follows: • Peripheral enable register 0(PER0) • Timer clock selection register m (TPSm) •...
Page 137: Peripheral Enable Register 0(Per0)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Peripheral enable register 0(PER0) The PER0 register is the register that sets whether to enable or disable the supply of clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocks to hardware that is not in use.
Page 138: Timer Clock Selection Register M (Tpsm)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer clock selection register m (TPSm) The TPSm register is a 16-bit register that selects the two or four common operating clocks (CKm0, CKm1, CKm2, CKm3) provided to each channel. CKm0 is selected via bits 3~0 of the TPSm register, and CKm1 is selected via bits 7~4 of the TPSm register.
Page 139 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure 5-6: Table of timer clock select register m (TPSm) (1/2) Symbol TPSm Note Selection of operating clock (CKmk) (k=0, 1) =2MHz =4MHz =8MHz F =20MHz F =32MHz 2MHz 4MHz...
Page 140 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure 5-7: Table of timer clock select register m (TPSm) (2/2) Symbol TPSm Note Selection of the running clock (CKm2) PRSm21 PRSm20 =2MHz =4MHz =8MHz F =20MHz F =32MHz 1MHz...
Page 141: Timer Mode Register Mn (Tmrmn)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer mode register mn (TMRmn) The MRmn register is the register for setting the operation mode of channel n. It carries out the selection of the operation clock (F ), the selection of the count clock, the selection of master/slave, the setting of start trigger and capture trigger, the selection of the active edge of the timer input and the setting of the operation mode (interval, capture, event counter, single count, capture &...
Page 142 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-9: Table of timer mode register mn (TMRmn) (2/ 4) Symbol TMRmn n=2,4,6 TERmn Symbol TMRmn Note 1 (n=0,1,3, 5,7) (Bit11 of TMRmn (n=2,4,6)) Selection of independent channel operation/multi-channel linked operation (slave...
Page 143 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure 5-10: Table of timer mode register mn (TMRmn) (3/ 4) Symbol TMRmn n=2,4,6 TERmn Symbol TMRmn Note 1 (n=0,1,3, 5,7) CISmn1 CISmn0 Active edge selection for TImn pins Falling edge...
Page 144 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure 5-11: Table of timer mode register mn (TMRmn) (4/4) Symbol TMRmn n=2,4,6 TERmn Symbol TMRmn (n=0,1,3, Note 1 5,7) Setting of channel n Counting Corresponding functions operation mode operation of TCR...
Page 145: Timer Status Register Mn (Tsrmn)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer status register mn (TSRmn) The TSRmn register is a register that indicates the overflow status of the channel n counter. The TSRmn register is valid only in capture mode (MDmn3~MDmn1=010B) and capture & single count mode (MDmn3~MDmn1=110B).
Page 146: Timer Channel Enable Status Register M (Tem)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer channel enable status register m (TEm) The TEm register is a register that indicates the enable or stop status of each channel timer operation. Each of the TEm register corresponds to each of the timer channel start register m (TSm) and timer channel stop register m (TTm).
Page 147: Timer Channel Start Register M (Tsm)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer channel start register m (TSm) The TSm register is a trigger register to initialize Timer Count Register mn (TCRmn) and set the start of each channel count operation. If each bit is set to "1", the corresponding bit of Timer Channel Enable Status Register m (TEm) is set to "1".
Page 148: Timer Channel Stop Register M (Tpsm)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer channel stop register m (TPSm) The TTm register is a trigger register to set the count stop of each channel. If each bit is set to "1", the corresponding bit of Timer Channel Enable Status Register m (TEm) is cleared to "1".
Page 149: Timer Input Output Selection Register (Tios0)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer input output selection register (TIOS0) The TIOS0 register selects the timer inputs for Channel 0 and Channel 1 of Unit 0 and the timer outputs for Channel 2. The TIOS0 register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of the TIOS0 register changes to "00H".
Page 150: Timer Output Enable Register M (Toem)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer output enable register m (TOEm) The TOEm register is a register that sets to enable or disable the timer output of each channel. For channel n, which allows timer output, the value of the TOmn bit of the latter timer output register m (TOm) cannot be rewritten by software, and the value reflected by the timer output function of the count operation is output from the output pin (TOmn) of the timer.
Page 151: Timer Output Register M (Tom)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer output register m (TOm) The TOm register is a buffer register for each channel timer output. The bit value of this register is output from the output pin (TOmn) of each channel timer.
Page 152: Timer Output Level Register M (Tolm)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer output level register m (TOLm) The TOLm register is a register that controls the output level of each channel timer. When timer output (TOEmn=1) is enabled and the multi-channel link operation function (TOMmn=1) is used, the set and reset timing of the timer output signal reflects the inverse setting of each channel n performed by this register.
Page 153: Timer Output Mode Register M (Tomm)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer output mode register m (TOMm) The TOMm register is a register that controls the output mode of each channel timer. When used as an independent channel operation function, the corresponding bit of the using channel should be set to "0”.
Page 154: Input Switching Control Register (Isc)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Input switching control register (ISC) The ISC1 and ISC0 bits of the ISC register are used for the coordination of channel 3 and the general-purpose serial communication unit to implement LIN-bus communication. If the ISC1 bit is set to "1", the input signal of the serial data input pin (RxD0) is selected as the input of the timer.
Page 155: Noise Filter Enable Register (Nfen1)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Noise filter enable register (NFEN1) The NFEN1 register sets whether the noise filter is used for the input signal of each channel timer input pin. For the pin that needs to eliminate noise, the corresponding bit must be set to "1” and make the noise filter effective.
Page 156: Registers For Controlling Timer Input/Output Pin Port Functions
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Note: The applicable pin can be switched by setting the ISC1 bit of the Input Switching Control Register (ISC). ISC1=0: You can choose whether to use the noise filter of the TI03 pin. ISC1=1: You can choose whether to use the noise filter of the RxD0 pin.
Page 157: Basic Rules Of The General-Purpose Timer Unit
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Basic rules of the general-purpose timer unit Basic rules of multi-channel linkage operation function The multi-channel linkage function is a function that combines a master channel (a reference timer that counts cycles) and a slave channel (a timer that operates in compliance with the master channel), and several rules need to be observed when using it.
Page 158 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Example 1 Timer8 Channel group 1 (multi-channel linkage operation function) CK00 Channel 0: Master Channel 1: Slave Channel group 2 (multi-channel linkage CK01 operation function) Channel 2: Master Channel 3: Slave...
Page 159 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Example 2 Timer 8 Channel Group 1 (multi-channel linked operation function) CK00 Channel 0: Master control CK01 Channel 1:independent channel operation function Channel 2: Slave CK00 Channel 3:independent channel operation function Rev.0.1.1...
Page 160: Timer Channel Start Register M (Tsm)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer channel start register m (TSm) The TSm register is a trigger register to initialize Timer Count Register mn (TCRmn) and set the start of each channel count operation. If each bit is set to "1", the corresponding bit of Timer Channel Enable Status Register m (TEm) is set to "1".
Page 161: Operation Of Counters
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Operation of counters Counting clock (F TCLK The count clock of the general purpose timer unit (F ) can be selected by the CCSmn bit of the Timer Mode TCLK Register mn (TMRmn) for any of the following clocks: •...
Page 162 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 (2) The case of selecting an active edge of the TImn pin input signal (CCSmn=1) The count clock (F ) is a signal that detects an active edge of the TImn pin input signal and is...
Page 163: Start Timing Of Counter
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Start timing of counter The timer count register mn(TCRmn) enters the operation enable state by setting TSmn bit of the timer channel start register m (TSm). Execution from the counting enable state to the start of the timer count register mn (TCRmn) is shown in Table 5-4.
Page 164: Operation Of Counters
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Operation of counters The following describes the counter operation for each mode. (1) Operation of the interval timer mode ① The operation enable state is entered by writing "1" to the TSmn bit (TEmn=1). The timer count register mn (TCRmn) remains at its initial value until a count clock is generated.
Page 165 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 (2) Operation of the event counter mode ① The timer count register mn (TCRmn) remains during the operation stop state (TEmn=0). ② The operation enable state is entered by writing "1" to the TSmn bit (TEmn=1).
Page 166 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 (3) Operation of capture mode (interval measurement of input pulses) ① The operation enable state is entered by writing "1" to the TSmn bit (TEmn=1). ② The timer count register mn (TCRmn) remains at its initial value until a count clock is generated.
Page 167 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 (4) Operation of the single count mode ① The operation enable state is entered by writing "1" to the TSmn bit (TEmn=1). ② The timer count register mn (TCRmn) remains the initial value until a start trigger signal is generated.
Page 168 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 (5) Operation of capture & single count mode (measurement of high level width) ① The operation enable state is entered by writing "1" to the TSmn bit of the timer channel start register m (TSm)(TEmn=1).
Page 169: Control Of Channel Outputs (Tomn Pins)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Control of channel outputs (TOmn pins) Block diagram of the TOmn pin output circuit Figure5-31: Block Diagram of the output circuit TOmn register Interrupt signal of master channel （INTTMmn） interrupt singal of slave...
Page 170: Settings Of The Tomn Pin Output
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Settings of the TOmn pin output The steps and state changes from the initial setting of the TOmn output pin to the start of timer operation are shown below. Figure5-32: State change from the setting timer output to the start of operation TCRmn Random value ( "FFFFH"...
Page 171: Cautions For Channel Output Operation
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Cautions for channel output operation (1) Change of setting values for TOm, TOEm, TOLm, TOMm registers in timer operation The operation of the timer (timer count register mn (TCRmn) and timer data register mn (TDRmn)) and the Tomn output circuit are independent.
Page 172 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-34: Output state of TOmn pin at PWM output (TOMmn=1) valid voltage level valid voltage level valid voltage level initial state (initial State: low voltage level) (valid high voltage level)
Page 173 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 (3) TOmn pin change for slave channel output mode (TOMmn=1) (a) Settings of changing the timer output level register m (TOLm) during timer operation If the setting of the TOLm register is changed during timer operation, the setting is valid when the TOmn pin change condition is generated.
Page 174 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-36: Set/reset timing operation status (1) Basic operation timing TCLK INTTMmn master channel internal reset signal Tomn Pin/TOmn swap swap internal reset signal delay 1 clock cycle INTTMmp slave channel...
Page 175 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Remark: Internal reset signal: reset/alternating signal on TOmn pin Internal set signal: set signal on TOmn pin m: unit number (m=0) n: channel n=0~7 (master control channel: n=0, 2, 4, 6)
Page 176: One-Time Operation Of Tomn Bit
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 One-time operation of TOmn bit Like the timer channel start register m (TSm), the timer output register m (TOm) has the set bits (TOmn) for all channels and can therefore operate the TOmn bits for all channels at once.
Page 177: Timer Interrupt And Tomn Pin Output When Counting Starts
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Timer interrupt and TOmn pin output when counting starts In interval timer mode or capture mode, the MDmn0 bit of Timer Mode Register mn (TMRmn) is the bit that sets whether to generate a timer interrupt when counting starts.
Page 178: Control Of Timer Input (Timn)
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Control of Timer Input (TImn) Block diagram of the TImn pin input circuit The signal from the timer input pins is input to the timer control circuit via a noise filter and the edge detection circuit.
Page 179: Cautions For Channel Input Operation
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Cautions for channel input operation When set to not use the timer input pin, no operating clock is provided to the noise filter circuit. Therefore, the following wait time is required from the time set to use the timer input pin to the time the channel corresponding to the timer input pin is set to operate the enable trigger.
Page 180: Independent Channel Operation Function For General Purpose Timer Units
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Independent channel operation function for general purpose timer units Operation as interval timer/square wave output (a) Interval Timer It can be used as a reference timer to generate INTTMmn (timer interrupt) at fixed intervals. The interrupt INTTMmn (timer interrupt) generation period = counting clock period(setting value of TDRmn+1)
Page 181 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-42: Example of basic timing operating as an interval timer/square wave output (MDmn0=1) note operational clock Timer count register mn output Tomn Pin (TCRmn) control circuit Timer data register mn...
Page 182 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-44: Example of register setting contents for interval timer/square wave output (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 note...
Page 183 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-45: Procedure for the interval timer/square wave output function Software operation Hardware status The input clock of timer unit m is in the stop- providing state. (Stop providing clock, cannot write to each...
Page 184: Operation As External Event Counter
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Operation as external event counter It can be used as an event counter to count the active edges (external events) detected on the TImn pin input and generate an interrupt if the specified count value is reached. The specified count value can be calculated using...
Page 185 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-47: Example of register contents setting in external event counter mode (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn...
Page 186 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-48: Procedure for the external event counter function Software operation Hardware status The input clock of timer unit m is in the stop- providing state. (Stop providing clock, cannot write to each...
Page 187: Operation As Frequency Divider
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Operation as frequency divider The clock input from the TImn pin can be divided and used as a divider for the output of the TOmn pin. The divided clock frequency of the TOmn output can be calculated using the following equation: •...
Page 188 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-50: Example of register contents setting when operating as a frequency divider (channel 0 of unit 0) (a) Timer mode register 00 (TMR00) CKS001 CKS000 CCS00 STS002 STS001 STS000 CIS001...
Page 189 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-51: Procedure for the frequency divider function Software operation Hardware status The input clock of timer unit 0 is in the stop- providing state. (Stop providing clock, cannot write to each register)
Page 190: Operation As Input Pulse Interval Measurement
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Operation as input pulse interval measurement The count value can be captured at the active edge of TImn and the interval between TImn input pulses can be measured. The software operation (TSmn=1) can also be set to capture the count value during the period when the TEmn bit is "1".
Page 191 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 TImn: TImn pin input signal TCRmn: timer count register mn (TCRmn) TDRmn: timer data register mn (TDRmn) OVF: bit 0 of Timer Status Register mn (TSRmn) Rev.0.1.1 www.mcu.com.cn 191 / 822...
Page 192 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-53: Example of register contents setting in measuring input pulse interval (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn 注 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 MDmn3 MDmn2 MDmn1...
Page 193 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-54: Procedure for the input pulse interval measurement function Software operation Hardware status The input clock of timer unit m is in the stop- providing state. (Stop providing clock, cannot write to each...
Page 194: Operation As Input Signal High And Low Level Width Measurement
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Operation as input signal high and low level width measurement Note: When used as a LIN-bus support feature, the bit1 (ISC1) of the input switching control register (ISC) must be set to "1", and in the instructions below, please use RxD0 Instead of TImn.
Page 195 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-55: Example of basic timing operating as an high and low level width measurement of input signal 0000H Remark: m: unit number (m=0) n: channel number (n=0~7) TSmn: bit n of timer channel start register m (TSm)
Page 196 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-56: Example of register contents setting in measuring high and low level width of input signal (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn 注 STSmn2 STSmn1 STSmn0 CISmn1...
Page 197 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-57: Procedure for high and low level width measurement function of input signal Software operation Hardware status The input clock of timer unit m is in the stop- providing state.
Page 198: Operation As Delay Counter
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Operation as delay counter The count can be decremented by the active edge detection (external event) of the TImn pin input and INTTTMmn (Timer interrupt) is generated at any set interval.
Page 199 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-59: Example of register contents setting for delay counter function (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn operation mode of Channel N...
Page 200 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-60: Procedure for the delay counter function Software operation Hardware status The input clock of timer unit m is in the stop- providing state. (Stop providing clock, cannot write to each register)
Page 201: Multi-Channel Linkage Operation Function For General Purpose Timer Units
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Multi-channel linkage operation function for general purpose timer units Operation as single trigger pulse output function Using the 2 channels in pairs, a single trigger pulse with any delay pulse width can be generated from the input of the TImn pin.
Page 202 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-61: Block diagram of operation as single trigger pulse output function master control channel (single counting mode) operational clock Timer count register mn (TCRmn) interrupt Timer data register mn control...
Page 203 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-62: Example of basic timing operating as a single trigger pulse output function TSmn TEmn TImn Master FFFFH channel TCRmn 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H...
Page 204 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-63: Example of register contents setting for single trigger pulse output function (master channel) (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 MDmn3...
Page 205 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-64: Example of register contents setting forsingle trigger pulse output function (slave channel) (a) Timer mode register mn (TMRmn) CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp0 Note MDmp3...
Page 206 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-65: Procedure for the single trigger pulse output function (1/2) Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register)
Page 207 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-66: Procedure for the single trigger pulse output function (2/2) Software operation Hardware status The setting values of the CISmn1 bit and the The master channel loads the value of the...
Page 208: Operation As Pwm Function
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Operation as PWM function By using the 2 channels in pairs, pulses of any period and duty cycle can be generated. The period and duty Pulse period = {TDRmn (master) set value+1}counting clock period Duty cycle[%] = {TDRmp (slave) set value}/{TDRmn (master) set value+1}100...
Page 209 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-67: Block diagram of operation as PWM function master control channel (interval Timer mode) operational clock Timer count register mn (TCRmn) interrupt Timer data register mn control interrupt signal (TDRmn)
Page 210 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-68: Example of basic timing operating as PWM function TSmn TEmn FFFFH TCRmn 0000H Master channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel TDRmp TOmp INTTMmp Remark: m: unit number (m=0) n: master channel number (n=0, 2, 4, 6) p: slave channel number (n <...
Page 211 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-69: Example of register contents setting for PWM function (master channel) (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 MDmn3 MDmn2 MDmn1 TMRmn...
Page 212 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-70: Example of register contents setting for PWM function (master channel) (a) Timer mode register mn (TMRmn) CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp0 Note MDmp3 MDmp2 MDmp1...
Page 213 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-71: Procedure for the PWM function (1/2) Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register)
Page 214 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-72: Procedure for the PWM function (2/2) Software operation Hardware status Set the TOEmp bit to “1” (only limited to restart operation). Set both the TSmn bit (master) and TSmp bit The TEmn and TEmp bits become "1".
Page 215: Operation As Multiple Pwm Output Function
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Operation as multiple PWM output function This is a function that extends the PWM function and uses multiple slave channels for multiple PWM outputs with different duty cycles. For example, when using 2 slave channels in pairs, the period and duty cycle of the output pulse can be Pulse period = {TDRmn (master) set value+1}counting clock period...
Page 216 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-73: Block diagram of operation as multiple PWM output function (output two types of PWMs) master control channel (interval Timer mode) operational clock Timer count register mn (TCRmn) interrupt Timer data register...
Page 217 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-74: Example of basic timing operating as multiple PWM output function (output two types of PWMs) TSmn TEmn FFFFH TCRmn 0000H master control channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH...
Page 218 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Remark: m: unit number (m=0) n: master channel number (n=0, 2, 4) p: slave channel number q: slave channel number For m = 0: n < p < q ≤ 7 (p and q are integers greater than n)
Page 219 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-75: Example of register contents setting for multiple PWM output function (master channel) (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 MDmn3 MDmn2...
Page 220 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-76: Example of register contents setting for multiple PWM output function (slave channel) (output two types of PWMs) (a) Timer mode registers mp, mq (TMRmp, TMRmq) CKSmp1 CKSmp0 CCSmp STSmp2...
Page 221 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Note: TMRm2, TMRm4: MASTERmp bit, MASTERmq bit Remark: m: unit number (m=0) n: master channel number (n= 2, 4, 6) p: slave channel number q: slave channel number m = 0 when: n < p < q ≤ 7 (p and q are integers greater than n) Rev.0.1.1...
Page 222 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-77: Procedure for the multiple PWM output function (output two types of PWMs) (1/2) Software operation Hardware status The input clock of timer unit m is in the stop-providing state.
Page 223 CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Figure5-78: Procedure for the multiple PWM output function (output two types of PWMs) (2/2) Software operation Hardware status (Set the TOEmp bit and TOEmq bit only when The TEmn, TEmp and TEmq bits become "1".
Page 224: Cautions When Using The General-Purpose Timer Unit
CMS32H6157 User Manual | Chapter 5 General-purpose timer unit Timer8 Cautions when using the general-purpose timer unit Cautions when using timer output Depending on the product, the pins assigned with timer output functions may also be assigned with outputs of other multiplexed functions.
Page 225: Timera
CMS32H6157 User Manual | Chapter 6 TimerA TimerA TimerA function Timer A is a 16-bit timer capable of pulse output, pulse width and period measurement of external inputs, and counting of external events. The 16-bit timer consists of a reload register and a decrement counter. The reload register and the decrement counter are assigned at the same address.
Page 226: Structure Of Timer A
CMS32H6157 User Manual | Chapter 6 TimerA Structure of Timer A The block diagram and pin structure of Timer A are as follows Figure6-1 and Table 6-2respectively. Figure6-1: Block diagram of Timer A TCK2~TCK0 =000B =001B =011B =100B 注 2...
Page 227: Registers For Controlling Timer A
CMS32H6157 User Manual | Chapter 6 TimerA Registers for controlling Timer A The registers controlling Timer A are shown inTable 6-3. Table 6-3: Registers for controlling Timer A Register Name Symbol Port multiplexing function configuration register PxxCFG Peripheral enable register 0...
Page 228: Peripheral Enable Register 0(Per0)
CMS32H6157 User Manual | Chapter 6 TimerA Peripheral enable register 0(PER0) The PER0 register is a register that sets to enable or disable providing clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocks to hardware that is not in use.
Page 229: Subsystem Clock Supply Mode Control Register (Osmc)
CMS32H6157 User Manual | Chapter 6 TimerA Subsystem Clock Supply Mode Control Register (OSMC) The operating clock of timer A can be selected by the WUTMMCK0 bits. The RTCLPC bit is a bit that reduces power consumption by stopping the unwanted clock function. For the setting of RTCLPC bit, please refer to "Chapter 4 Clock Generation Circuit".
Page 230: Timer A Count Register 0 (Ta0)
CMS32H6157 User Manual | Chapter 6 TimerA Timer A count register 0 (TA0) This is a 16-bit register. If this register is written, the data is written to the reload register. If this register is read, the count value is read. The status of the reload register and counter changes depending on the value of the TSTART bit of the TACR0 register.
Page 231: Timer A Control Register 0 (Tacr0)
CMS32H6157 User Manual | Chapter 6 TimerA Timer A control register 0 (TACR0) The TACR0 register is the register that controls the count and stop of register A and indicates the status of timer A. The TACR0 register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of the TACR0 register changes to "00H".
Page 232: Timer Ai/O Control Register 0 (Taioc0)
CMS32H6157 User Manual | Chapter 6 TimerA Note 1: If you write "1" to the TSTOP bit (force stop counting), the TSTART bit and TCSTF bit are initialized at the same time, and the pulse output levels are also initialized.
Page 233 CMS32H6157 User Manual | Chapter 6 TimerA Table 6-4: Edge and polarity switching of TAIO input/output Operation mode Function Timer mode Not used (IO Ports). 0: Output from the "H" level (initial level: "H"). Pulse output mode 1: Output from the "L" level (initial level: "L").
Page 234: Timer A Control Register 0 (Tamr0)
CMS32H6157 User Manual | Chapter 6 TimerA Timer A control register 0 (TAMR0) The TAMR0 register is a register that sets the operating mode of register A. The TAMR0 register is set by an 8- bit memory manipulation instruction. After a reset signal is generated, the value of the TAMR0 register changes to "00H".
Page 235: Timer A Event Pin Selection Register 0 (Taisr0)
CMS32H6157 User Manual | Chapter 6 TimerA Timer A event pin selection register 0 (TAISR0) The TAISR0 register is a register that selects the timer that controls the event count period in the event counter mode and sets the polarity. The TAISR0 register is set by an 8-bit memory manipulation instruction.
Page 236: Timer A Operation
CMS32H6157 User Manual | Chapter 6 TimerA Timer A operation Rewriting the reload register and counter Independent of the operation mode, the rewrite timing of the reload registers and counters varies depending on the value of the TSTART bit in the TACR0 register. When the TSTART bit is "0" (stop counting), the reload register and counter are written directly.
Page 237: Timer Mode
CMS32H6157 User Manual | Chapter 6 TimerA Timer mode This is a mode of decreasing count by the count source selected by the TCK0~TCK2 bits of TAMR0 register. In the timer mode, the count value is decremented by 1 whenever the count source is input, and if the count value becomes "0000H"...
Page 238: Pulse Output Mode
CMS32H6157 User Manual | Chapter 6 TimerA Pulse output mode In this mode, the count source selected by bits TCK0 to TCK2 of the TAMR0 register is decremented to count, and the output levels of the TAIO pin and TAO pin are inverted and output whenever an underflow occurs.
Page 239: Event Counter Mode
CMS32H6157 User Manual | Chapter 6 TimerA Event counter mode This is a mode of decrementing counting via an external event signal (count source) input from the TAIO pin. Various settings during event counting can be made via the TIOGT0~TIOGT1 bits of TAIOC0 register and TAISR0 register, and the filter function of TAIO input can be specified via the TIPF0~TIPF1 bits of TAIOC0 register.
Page 240 CMS32H6157 User Manual | Chapter 6 TimerA Figure 6-13: Example of operating the event counter mode 2 example of timing sequence to configure operational mode to following scenario. TAMR0 register: TMOD2, 1, 0=010B (Event counter mode) TAIOC0 register: TIOGT1,0=01B(event count during external interrupt pin defined period)
Page 241: Pulse Width Measurement Mode
CMS32H6157 User Manual | Chapter 6 TimerA Pulse width measurement mode This is a mode to measure the pulse width of the external signal input to the TAIO pin. In the pulse width measurement mode, if the level specified by the TEDGSEL bit of the TAIOC0 register is input to the TAIO pin, counting starts decreasingly by the selected counting source.
Page 242: Pulse Period Measurement Mode
CMS32H6157 User Manual | Chapter 6 TimerA Pulse period measurement mode This is a mode to measure the pulse period of the external signal input to the TAIO pin. The counter counts decreasingly by the count source selected by bits TCK0 to TCK2 of the TAMR0 register. If a...
Page 243: Collaboration With Eventc
CMS32H6157 User Manual | Chapter 6 TimerA Collaboration with EVENTC By working with EVENTC, events entered by EVENTC can be set as the count source. Counting is performed on the rising edge of the event of the ELC input via bits TCK0 to TCK2 of the TAMR0 register.
Page 244: Output Settings For Each Mode
CMS32H6157 User Manual | Chapter 6 TimerA Output settings for each mode The status of the TAO pin and TAIO pin in each mode are shown inTable 6-6andTable 6-7. Table 6-6: TAO pin settings TAIOC0 register Operation mode Output of the TAO pin...
Page 245: Cautions When Using Timer A
CMS32H6157 User Manual | Chapter 6 TimerA Cautions when using timer A Start and stop control of counting • Event counting mode or when the counting source is set to non-EVENTC If "1" is written to the TSTART bit of the TACR0 register during the counting stop, the TCSTF bit of the TACR0 register will be "0"...
Page 246: Access To Counting Registers
CMS32H6157 User Manual | Chapter 6 TimerA Access to counting registers If the TSTART bit and TCSTF bit of the TACR0 register are both "1" (counting), successive writes to the TA0 register must be separated by at least 3 count source clock cycles between the respective write operations.
Page 247: When Timer A Is Not Used
CMS32H6157 User Manual | Chapter 6 TimerA When timer A is not used When Timer A is not used, you must set the TMOD2~TMOD0 register to "000B" (Timer mode) and set the TAIOC0 register to "0" (TAO output is disabled).
Page 248: Function Limitations In Deep Sleep Mode (Event Counter Mode Only)
CMS32H6157 User Manual | Chapter 6 TimerA Function limitations in deep sleep mode (event counter mode only) To make the event counter mode run in deep sleep mode, the digital filter function cannot be used. Forced count stop via the TSTOP bit The following SFRs cannot be taken 1 count source cycle after forcing the counter to stop counting via the TSTOP bit of the TACR0 register.
Page 249: Selecting Fil As The Count Source
CMS32H6157 User Manual | Chapter 6 TimerA Selecting F as the count source To select F as the count source, the WUTMMCK0 bit of the subsystem clock supply mode control register (OSMC) must be set to "1”. However, when F...
Page 250: Real Time Clock
CMS32H6157 User Manual | Chapter 7 Real time clock Real time clock Functions of real-time clock The real-time clock has the following functions. • Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years.
Page 251 CMS32H6157 User Manual | Chapter 7 Real time clock Figure7-1: Block diagram of real-time clock real time clock control register 1 real time clock control register 0 secondary system provide mode control register (OSMC) alarm week alarm hour alarm minute...
Page 252: Registers For Controlling Real-Time Clock
CMS32H6157 User Manual | Chapter 7 Real time clock Registers for controlling real-time clock The real-time clock is controlled by the following registers. • Peripheral enable register 0 (PER0) • Real-time clock selection register (RTCCL) • Real-time clock control register 0 (RTCC0) •...
Page 253: Peripheral Enable Register 0 (Per0)
CMS32H6157 User Manual | Chapter 7 Real time clock Peripheral enable register 0 (PER0) The PER0 register is the register that sets whether to enable or disable the supply of clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocks to hardware that is not in use.
Page 254: Real-Time Clock Selection Register (Rtccl)
CMS32H6157 User Manual | Chapter 7 Real time clock Real-time clock selection register (RTCCL) The count clock (F ) of the real-time clock and the 15-bit interval timer can be selected via RTCCL. Figure7-3: Format of real-time clock selection register (RTCCL)
Page 255: Real-Time Clock Control Register 0 (Rtcc0)
CMS32H6157 User Manual | Chapter 7 Real time clock Real-time clock control register 0 (RTCC0) This is an 8-bit register that sets the start or stop of the real-time clock, the control of the RTC1HZ pin, the 12/24-hour system, and the fixed cycle interrupt function.
Page 256: Real-Time Clock Control Register 1 (Rtcc1)
CMS32H6157 User Manual | Chapter 7 Real time clock Real-time clock control register 1 (RTCC1) This is an 8-bit register that controls the alarm clock interrupt function and counter wait. The RTCC1 register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "00H".
Page 257 CMS32H6157 User Manual | Chapter 7 Real time clock Figure7-5: Format of real-time clock control register 1 (RTCC1)(2/ 2) Fixed-cycle interrupt status flag RIFG No fixed-cycle interruptions are generated. Generate fixed-cycle interrupts. This is a status flag that indicates a fixed-cycle interrupt. When a fixed-cycle interrupt is generated, this flag is "1".
Page 258: Watch Error Correction Register (Subcud)
CMS32H6157 User Manual | Chapter 7 Real time clock Watch error correction register (SUBCUD) This is a register that can correct the clock speed with high accuracy by changing the overflow value (reference value: 7FFFH) from the internal counter (16 bits) to the second count register (SEC).
Page 259: Second Count Register (Sec)
CMS32H6157 User Manual | Chapter 7 Real time clock Second count register (SEC) The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of seconds. It counts up when the internal counter (16-bit) overflows.
Page 260: Minute Count Register (Min)
CMS32H6157 User Manual | Chapter 7 Real time clock Minute count register (MIN) The MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes. It counts up when the second counter overflows.
Page 261: Hour Count Register (Hour)
CMS32H6157 User Manual | Chapter 7 Real time clock Hour count register (HOUR) The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and indicates the count value of hours. It counts up when the minute counter overflows.
Page 262 CMS32H6157 User Manual | Chapter 7 Real time clock Table7-2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value, and time. Table7-2: Displayed Time Digits 24-Hour Display (AMPM = 1) 12-Hour Display (AMPM = 0)
Page 263: Day Count Register (Day)
CMS32H6157 User Manual | Chapter 7 Real time clock Day count register (DAY) The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows. This counter counts as follows.
Page 264: Week Count Register (Week)
CMS32H6157 User Manual | Chapter 7 Real time clock Week count register (WEEK) The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. It counts up in synchronization with the day counter.
Page 265: Month Count Register (Month)
CMS32H6157 User Manual | Chapter 7 Real time clock Month count register (MONTH) The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows.
Page 266: Year Count Register (Year)
CMS32H6157 User Manual | Chapter 7 Real time clock Year count register (YEAR) The YEAR register is an 8-bit register that takes a value of 0 to 99 (decimal) and indicates the count value of years. It counts up when the month count register (MONTH) overflows. Values 00, 04, 08, …, 92, and 96 indicate a leap year.
Page 267: Alarm Minute Register (Alarmwm)
CMS32H6157 User Manual | Chapter 7 Real time clock Alarm minute register (ALARMWM) This register is used to set minutes of alarm. The ALARMWM register can be set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "00H".
Page 268: Alarm Hour Register (Alarmwh)
CMS32H6157 User Manual | Chapter 7 Real time clock Alarm hour register (ALARMWH) This register is used to set hours of alarm. The ALARMWH register can be set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "12H".
Page 269: Alarm Week Register (Alarmww)
CMS32H6157 User Manual | Chapter 7 Real time clock Alarm week register (ALARMWW) This register is used to set date of alarm. The ALARMWW register can be set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "00H".
Page 270: Starting Operation Of Real-Time Clock
CMS32H6157 User Manual | Chapter 7 Real time clock Starting operation of real-time clock Figure7-17: Procedure for starting operation of real-time clock start configure to provide Note1 RTCEN=1 input clock RTCE=0 configure to stop counting 。 configure RTCCL configure f select 12 hour system or 24 configure AMPM，...
Page 271: Shifting To Sleep Mode After Starting Operation
CMS32H6157 User Manual | Chapter 7 Real time clock Shifting to sleep mode after starting operation Perform some of the following processing when shifting to sleep mode immediately after setting the RTCE bit to 1. However, after setting the RTCE bit to 1, this processing is not required when shifting to sleep mode after the INTRTC interrupt has occurred.
Page 272: Reading/Writing Real-Time Clock
CMS32H6157 User Manual | Chapter 7 Real time clock Reading/writing real-time clock Read or write the counter after setting “1” to RWAIT first. Set RWAIT to “0” after completion of reading or writing the counter. Figure7-19: Procedure for reading real-time clock...
Page 273 CMS32H6157 User Manual | Chapter 7 Real time clock Figure7-20: Procedure for reading real-time clock Start configure as SEC~Year counter RWAIT=1 stop operating, enter into read/ write mode of counter. confirm counter wait state RWST=1? 设定SEC Write SEC Write second count register...
Page 274: Setting Alarm Of Real-Time Clock
CMS32H6157 User Manual | Chapter 7 Real time clock Setting alarm of real-time clock Set alarm time after setting 0 to WALE (alarm operation invalid.) first. Figure7-21: Alarm setting steps Start WALE=0 alarm alignment operation invalid generate interrupt via alarm...
Page 275: Hz Output Of Real-Time Clock
CMS32H6157 User Manual | Chapter 7 Real time clock 1 Hz output of real-time clock Figure7-22: 1 Hz Output Setting Procedure Start RTCE=0 configure to stop counting 设定SEC Configure Port Pxx=1'b0,PMxx=1'b0 RCLOE1=1 allow RTC1HZ pin output (1Hz). RTCE=1 configure start counting...
Page 276: Example Of Watch Error Correction Of Real-Time Clock
CMS32H6157 User Manual | Chapter 7 Real time clock Example of watch error correction of real-time clock The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error Example of calculating the correction value correction register.
Page 277 CMS32H6157 User Manual | Chapter 7 Real time clock Correction example Example of correcting from 32767.4Hz to 32768Hz (32767.4Hz+18.3ppm) [Measuring the oscillation frequency] When the watch error correction register (SUBCUD) is the initial value ("0000H"), the oscillation frequency of each product is measured by outputting a signal of approximately 1Hz from the RTC1HZ pinNote.
Page 278: 15-Bit Interval Timer
CMS32H6157 User Manual | Chapter 8 15-bit interval timer 15-bit interval timer Functions of 15-bit Interval Timer An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from deep sleep mode. Structure of 15-bit Interval Timer The 15-bit interval timer includes the following hardware.
Page 279: Registers Controlling 15-Bit Interval Timer
CMS32H6157 User Manual | Chapter 8 15-bit interval timer Registers controlling 15-bit Interval Timer The 15-bit interval timer is controlled by the following registers. • Peripheral enable register 0 (PER0) • Real-time clock selection register (RTCCL) • 15-bit interval timer control register (ITMC)
Page 280: Real-Time Clock Selection Register (Rtccl)
CMS32H6157 User Manual | Chapter 8 15-bit interval timer Real-time clock selection register (RTCCL) The real-time clock and the count clock (F ) of the 15-bit interval timer can be selected via RTCCL. Figure8-3: Format of real-time clock selection register (RTCCL)
Page 281: 15-Bit Interval Timer Control Register (Itmc)
CMS32H6157 User Manual | Chapter 8 15-bit interval timer 15-bit interval timer control register (ITMC) This register is used to set up the starting and stopping of the 15-bit interval timer operation and to specify the timer compare value. The ITMC register is set by a 16-bit memory manipulation instruction.
Page 282: 15-Bit Interval Timer Operation
CMS32H6157 User Manual | Chapter 8 15-bit interval timer 15-bit interval timer operation 15-bit interval timer operation timing The count value specified for the ITCMP14 to ITCMP0 bits is used as an interval to operate an 15-bit interval timer that repeatedly generates interrupt requests (INTIT). When the RINTE bit is set to “1”, the 15-bit counter starts counting.
Page 283: Start Of Count Operation And Re-Enter To Sleep Mode After Returned From Sleep Mode
CMS32H6157 User Manual | Chapter 8 15-bit interval timer Start of count operation and re-enter to sleep mode after returned from sleep mode When setting the RINTE bit after returned from sleep mode and entering sleep mode again, write 1 to the RINTE bit, and confirm the written value of the RINTE bit is reflected or wait for at least one cycle of the count clock.
Page 284: Clock Output/Buzzer Output Controller
CMS32H6157 User Manual | Chapter 9 Clock Output/Buzzer Output Controller Clock Output/Buzzer Output Controller Functions of clock output/buzzer output controller The clock output controller is intended for clock output for supply to peripheral ICs. Buzzer output is a function to output a square wave of buzzer frequency.
Page 285 CMS32H6157 User Manual | Chapter 9 Clock Output/Buzzer Output Controller Note 1: For the frequencies that can be output from CLKBUZ0 and CLKBUZ1 pins, please refer to "AC Characteristics” in the data sheet. Note 2: When the WUTMMCK0 bit of the OSMC register is set to "1", the actual output is F when F selected as the output clock for the clock output/buzzer output.
Page 286: Registers For Controlling Clock Output/Buzzer Output Controller
CMS32H6157 User Manual | Chapter 9 Clock Output/Buzzer Output Controller Registers for controlling clock output/buzzer output controller Table9-1: Registers for controlling clock output/buzzer output controller Item Register list Control register Clock output select registers n (CKSn) Clock output select registers n (CKSn) These registers set output enable/disable for clock output or for the buzzer frequency output pin (CLKBUZn), and set the output clock.
Page 287 CMS32H6157 User Manual | Chapter 9 Clock Output/Buzzer Output Controller Note: Use the output clock within a range of 16 MHz. For details, please refer to "AC Characteristics” in the data sheet. Notice: Change the output clock after disabling clock output (PCLOEn = 0).
Page 288: Operations Of Clock Output/Buzzer Output Controller
CMS32H6157 User Manual | Chapter 9 Clock Output/Buzzer Output Controller Operations of clock output/buzzer output controller One pin can be used as clock output or buzzer output The CLKBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).
Page 289: Watch Dog Timer
CMS32H6157 User Manual | Chapter 10 Watch dog timer Watch dog timer Functions of watchdog timer The counting operation of the watchdog timer is set by the option byte (000C0H). The watchdog timer operates on the low-speed internal oscillator clock (F ).
Page 290 CMS32H6157 User Manual | Chapter 10 Watch dog timer Figure10-1: Block diagram of watchdog timer interval time control circuit option bytes (000C0H) interval time (count value overflow time x3/4 WDTINT +1/2fIL) option bytes (000C0H) WDCS2~WDCS0 interval clock overflow signal counter...
Page 291: Registers For Controlling Watchdog Timer
CMS32H6157 User Manual | Chapter 10 Watch dog timer Registers for controlling watchdog timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). Watchdog timer enable register (WDTE) Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again. The WDTE register is set by an 8-bit memory manipulation instruction.
Page 292: Lockup Control Register (Lockctl)And Its Protection Register(Prcr)
CMS32H6157 User Manual | Chapter 10 Watch dog timer LOCKUP control register (LOCKCTL)and its protection register(PRCR) The LOCKCTL register is a configuration register for controlling the Cortex-M0+ LockUp function to operate the watchdog timer, and PRCR is its write-protect register.
Page 293: Wdtcfg Configuration Registers (Wdtcfg0/1/2/3)
CMS32H6157 User Manual | Chapter 10 Watch dog timer WDTCFG configuration registers (WDTCFG0/1/2/3) The WDTCFG configuration registers are the registers for whether to force the watchdog timer to operate. The WDTCFG register is set by an 8-bit memory manipulation instruction.
Page 294: Operation Of Watchdog Timer
CMS32H6157 User Manual | Chapter 10 Watch dog timer Operation of watchdog timer Operational control of watchdog timer When using the watchdog timer, set the following items by option byte (000C0H): • The bit 4 (WDTON) of the option byte (000C0H) must be set to "1" to enable the watchdog timer...
Page 295 CMS32H6157 User Manual | Chapter 10 Watch dog timer When operating with the X1 oscillation clock after releasing the deep sleep mode, the CPU starts operating after the oscillation stabilization time has elapsed. Therefore, if the period between the deep sleep mode release and the watchdog timer overflow is short, an overflow occurs during the oscillation stabilization time, causing a reset.
Page 296: Setting Overflow Time Of Watchdog Timer
CMS32H6157 User Manual | Chapter 10 Watch dog timer Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H). If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts counting again by writing “ACH”...
Page 297: Setting Window Open Period Of Watchdog Timer
CMS32H6157 User Manual | Chapter 10 Watch dog timer Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows: •...
Page 298: Setting Watchdog Timer Interval Interrupt
CMS32H6157 User Manual | Chapter 10 Watch dog timer Setting watchdog timer interval interrupt Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be generated when 75%+1/2F of the overflow time is reached.
Page 299: Ad Converter
CMS32H6157 User Manual | Chapter 11 AD converter AD converter Function of A/D converter The A/D converter is used to convert analog input signals into digital values, including the following functions. ⚫ 12-bit resolution A/D conversion ⚫ Option to convert the analogue voltage of the external pins ANI0 to ANI25 input, the operational amplifier OPA output(OPAO), the internal reference voltage (1.45V) and the temperature sensor voltage...
Page 300 CMS32H6157 User Manual | Chapter 11 AD converter Figure11-1: Block Diagram of A/D converter Internal Bus Port Mode A/D mode Control register 2 Register (ADM2) Conversion result Conversion result ADREFP0 ADREFM ADRCK PMCxx ADREFP1 comparison upper limit value comparison lower limit value...
Page 301: Registers For Controlling A/D Converter
CMS32H6157 User Manual | Chapter 11 AD converter Registers for controlling A/D converter The A/D converter is controlled by the following registers: Register base address: PGCSC_BASE=4002_0800H;ADC_BASE=4004_5000H;PORT_BASE=4004_0000H Register name Register description Reset value Register address PER1 Peripheral enable register 1 PGCSC_BASE+1AH...
Page 302: Peripheral Enable Register (Per1)
CMS32H6157 User Manual | Chapter 11 AD converter Peripheral enable register (PER1) The PER1 register is the register that sets whether to enable or disable the supply of clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocks to hardware that is not in use.
Page 303: A/D Converter Mode Register 0 (Adm0)
CMS32H6157 User Manual | Chapter 11 AD converter A/D converter mode register 0 (ADM0) This register sets the clock for A/D converter, and starts/stops conversion. The ADM0 register is set by an 8- bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "00H".
Page 304: A/D Converter Mode Register 1 (Adm1)
CMS32H6157 User Manual | Chapter 11 AD converter A/D converter mode register 1 (ADM1) This register sets the mode for A/D converter. The ADM1 register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "00H".
Page 305: A/D Converter Mode Register 2 (Adm2)
CMS32H6157 User Manual | Chapter 11 AD converter A/D converter mode register 2 (ADM2) The ADM2 register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "00H". Figure11-5: Format of A/D converter mode register 2 (ADM2) (1/3)
Page 306: A/D Converter Trigger Mode Register (Adtrg)
CMS32H6157 User Manual | Chapter 11 AD converter A/D converter trigger mode register (ADTRG) This is the register that sets the A/D conversion trigger mode and the hardware trigger signal. The ADTRG register is set by an 8-bit memory manipulation instruction.
Page 307: Analog Input Channel Specification Register (Ads)
CMS32H6157 User Manual | Chapter 11 AD converter Analog input channel specification register (ADS) This is the register that specifies the analog voltage input channel for A/D converter. The ADS register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "00H".
Page 308 CMS32H6157 User Manual | Chapter 11 AD converter • 4-channel scan mode (ADM1.ADMD=1) Analog input channel ADISS ADS[5:0] Scan 0 Scan 1 Scan 2 Scan 3 1’b0 6’h00 ANI0 ANI1 ANI2 ANI3 1’b0 6’h01 ANI1 ANI2 ANI3 ANI4 1’b0 6’h02...
Page 309 CMS32H6157 User Manual | Chapter 11 AD converter • 2-channel scan mode (ADM1.ADMD=1) Analog input channel ADISS ADS[5:0] Scan 0 Scan 1 1’b0 6’h00 ANI0 ANI1 1’b0 6’h01 ANI1 ANI2 1’b0 6’h02 ANI2 ANI3 1’b0 6’h03 ANI3 ANI4 1’b0 6’h04...
Page 310: 12-Bit A/D Conversion Result Register (Adcr)
CMS32H6157 User Manual | Chapter 11 AD converter 12-bit A/D conversion result register (ADCR) This is a 16-bit register that stores the A/D conversion result, and this register is read-only. Each time A/D Note conversion ends, the conversion result is loaded from the successive approximation register (SAR) The high 4 bits of this register are fixed to "0"...
Page 311: 8-Bit A/D Conversion Result Register (Adcrh)
CMS32H6157 User Manual | Chapter 11 AD converter 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 12-bit resolution Note are stored The ADCRH register can be read by an 8-bit memory manipulation instruction.
Page 312: Conversion Result Comparison Lower Limit Setting Register (Adll)
CMS32H6157 User Manual | Chapter 11 AD converter Conversion result comparison lower limit setting register (ADLL) This register is used to specify the setting for checking the lower limit of the A/D conversion results. The A/D conversion results and ADLL register value are compared, and interrupt signal (INTAD) generation...
Page 313: A/D Converter Sampling Time Control Register (Adnsmp)
CMS32H6157 User Manual | Chapter 11 AD converter A/D converter sampling time control register (ADNSMP) This register controls the A/D sampling time. The ADNSMP register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "0dH".
Page 314 CMS32H6157 User Manual | Chapter 11 AD converter Time required to perform an ADC conversion: High-speed conversion mode: ADC conversion time = (number of sampling clocks + number of successive comparison clocks (31.5))/F Low-current conversion mode: ADC conversion time = (number of sampling clocks + number of successive comparison clocks (40.5))/F...
Page 315: A/D Converter Sampling Time Extension Control Register (Adsmpwait)
CMS32H6157 User Manual | Chapter 11 AD converter A/D converter sampling time extension control register (ADSMPWAIT) This register is used to extend the A/D sampling time. The ADSMPWAIT register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "00H".
Page 316: A/D Test Register (Adtes)
CMS32H6157 User Manual | Chapter 11 AD converter A/D test register (ADTES) This register is used to set the test mode of A/D converter. The ADTES register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "00H".
Page 317: A/D Converters Charge-Discharge Control Register (Adndis)
CMS32H6157 User Manual | Chapter 11 AD converter A/D converters charge-discharge control register (ADNDIS) This register is used to control the charge and discharge action and time of A/D converter The ADNDIS register can be read and written by an 8-bit memory manipulation instruction.
Page 318: Input Voltage And Conversion Result
CMS32H6157 User Manual | Chapter 11 AD converter Input voltage and conversion result The analogue input voltage at the analogue input pin (ANIx) and the theoretical A/D conversion result (12-bit A/D Conversion Result Register (ADCR)) are related by the following expressions.
Page 319: Operation Mode Of A/D Converter
CMS32H6157 User Manual | Chapter 11 AD converter Operation mode of A/D converter The A/D converter conversion operations are described below. For the setting of each mode, please refer to "11.5 A/D converter setup flowchart". Software trigger mode (select mode, sequential conversion mode) ①...
Page 320: Software Trigger Mode (Select Mode, Single Conversion Mode)
CMS32H6157 User Manual | Chapter 11 AD converter Software trigger mode (select mode, single conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to "1”.
Page 321: Software Trigger Mode (Scan Mode, Sequential Conversion Mode)
CMS32H6157 User Manual | Chapter 11 AD converter Software trigger mode (scan mode, sequential conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to "1”.
Page 322: Software Trigger Mode (Scan Mode, Single Conversion Mode)
CMS32H6157 User Manual | Chapter 11 AD converter Software trigger mode (scan mode, single conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to "1”.
Page 323: Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)
CMS32H6157 User Manual | Chapter 11 AD converter Hardware trigger no-wait mode (select mode, sequential conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to "1”.
Page 324: Hardware Trigger No-Wait Mode (Select Mode, Single Conversion Mode)
CMS32H6157 User Manual | Chapter 11 AD converter Hardware trigger no-wait mode (select mode, single conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to "1”.
Page 325: Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)
CMS32H6157 User Manual | Chapter 11 AD converter Hardware trigger no-wait mode (scan mode, sequential conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to "1”.
Page 326: Hardware Trigger No-Wait Mode (Scan Mode, Single Conversion Mode)
CMS32H6157 User Manual | Chapter 11 AD converter Hardware trigger no-wait mode (scan mode, single conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to "1”.
Page 327: Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
CMS32H6157 User Manual | Chapter 11 AD converter Hardware trigger wait mode (select mode, sequential conversion mode) ① In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 328: Hardware Trigger Wait Mode (Select Mode, Single Conversion Mode)
CMS32H6157 User Manual | Chapter 11 AD converter Hardware trigger wait mode (select mode, single conversion mode) ① In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 329: Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)
CMS32H6157 User Manual | Chapter 11 AD converter Hardware trigger wait mode (scan mode, sequential conversion mode) ① In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 330: Hardware Trigger Wait Mode (Scan Mode, Single Conversion Mode)
CMS32H6157 User Manual | Chapter 11 AD converter Hardware trigger wait mode (scan mode, single conversion mode) ① In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 331: A/D Converter Setup Flowchart
CMS32H6157 User Manual | Chapter 11 AD converter A/D converter setup flowchart The A/D converter setup flowchart in each operation mode is described below. Setting up software trigger mode Figure11-30: Setting up software trigger mode configuration starts configure PER0 register...
Page 332: Setting Up Hardware Trigger No-Wait Mode
CMS32H6157 User Manual | Chapter 11 AD converter Setting up hardware trigger no-wait mode Figure11-31: Setting up hardware trigger no-wait mode configuration starts configure PER0 register set ADCEN bit of PER0 register to 1, start provide clock configure PMC register...
Page 333: Setting Up Hardware Trigger Wait Mode
CMS32H6157 User Manual | Chapter 11 AD converter Setting up hardware trigger wait mode Figure11-32: Setting up hardware trigger wait mode configuration starts configuration PER0 set ADCEN bit of PER0 register to 1, start provide clock register configuration PMC register...
Page 334: Setup When Temperature Sensor Output Voltage/Internal Reference Voltage Is Selected
CMS32H6157 User Manual | Chapter 11 AD converter Setup when temperature sensor output voltage/internal reference voltage is selected (example for software trigger mode and single conversion mode) Figure11-33: Setup when temperature sensor output voltage/internal reference voltage is selected configuration starts...
Page 335: Setting Up Test Mode
CMS32H6157 User Manual | Chapter 11 AD converter Setting up test mode Figure11-34: Setting up test mode (V /half_V as conversion object) configuration starts configure PER0 register set ADCEN bit of PER0 register to 1, start provide clock ADM0 register FR2~FR0 bit: configure A/D conversion time.
Page 336: Sigma-Delta Adc
CMS32H6157 User Manual | Chapter 12 SIGMA-DELTA ADC SIGMA-DELTA ADC Overview The 24-Bit Sigma-Delta ADC is a high-precision, low-power analog-to-digital conversion module. It supports one differential input channel, one built-in linear voltage regulator(LDO), temperature sensor and high-precision oscillator. The output capacity of LDO is 20 mA. The programmable gain amplifier (PGA) of Sigma-Delta ADC supports selectable gain options of 1, 2, 4, 8, 16, 32, 64, 128 and 256.
Page 337: Description Of Adc Working Principle
CMS32H6157 User Manual | Chapter 12 SIGMA-DELTA ADC Description of ADC working principle The built-in LDO of Sigma-Delta ADC can supply power to the on-chip analog module, at the same time, it can provide 20 mA current to the off-chip circuit. LDOOUT pin shall be connected externally with a capacitor at least 1uF.
Page 338: Adc Clock, Output Data Rate
CMS32H6157 User Manual | Chapter 12 SIGMA-DELTA ADC ADC clock, output data rate Sigma-Delta ADC has a built-in clock to provide the frequency required by the system. 328KHz or 656KHz can be selected by FADC.The ODR of ADC can be configured by FADC and OSR [2:0]. The clock, ODR, and chopping frequency are shown in the table below.
Page 339: Reset And Sleep Mode
CMS32H6157 User Manual | Chapter 12 SIGMA-DELTA ADC Reset and sleep mode When the mode is powered on, the built-in power-on reset circuit will generate a reset signal to reset the mode automatically. When SCLK toggles from low to high level and keeps high state for more than 100us, the Sigma-Delta ADC enters sleep mode, and the power consumption is less than 50nA.
Page 340: Spi Serial Interface
CMS32H6157 User Manual | Chapter 12 SIGMA-DELTA ADC SPI Serial Interface The Sigma-Delta ADC uses 2-wire SPI serial interface SCLK, DRDYB/DOUT for data reception and function configuration. Digital output codes The Sigma-Delta ADC outputs data as a digital output code of 24-bit binary complement, where B23 is the sign bit, 0 is positive and 1 is negative.
Page 341: Serial Data Transmission
CMS32H6157 User Manual | Chapter 12 SIGMA-DELTA ADC Serial data transmission Read data timing chart 1: Data New Data DRDYB Ready Ready SCLK Read data timing chart 2: 24-bit ADC data Register Status Data Update1 Update2 DRDYB Force High New Data...
Page 342: Function Configuration
CMS32H6157 User Manual | Chapter 12 SIGMA-DELTA ADC Function configuration The Sigma-Delta ADC can read and configure the registers through SCLK and DRDYB/DOUT, and the functional configuration timings are shown below: Switching Write command Force Switch Write command word data...
Page 343: Description Of Spi Opcode Command
CMS32H6157 User Manual | Chapter 12 SIGMA-DELTA ADC Description of SPI opcode command Sigma-Delta ADC has 8 opcode command word with 7-bit length, which are described as follows: Opcode command Name Function Remark (controlled) SPI communication required for register 0x65...
Page 344: Related Registers
CMS32H6157 User Manual | Chapter 12 SIGMA-DELTA ADC Related registers Sigma-Delta ADC control register 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDADCCON1 SET_LDO_1 SET_LDO_0 OSR_2 OSR_1 PGA_SEL2 PGA_SEL1 PGA_SEL0 Reset value Bit7~Bit6 LDO output voltage control SET_LDO<1:0>: 2.4V;...
Page 345: Sigma-Delta Adc Control Register 2
CMS32H6157 User Manual | Chapter 12 SIGMA-DELTA ADC Sigma-Delta ADC control register 2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDADCCON2 CHSEL2 CHSEL1 CHSEL0 LPWR FADC OSR_0 ENCHOPB FCHOP_ADC Reset value Bit7~Bit5 CHSEL<2:0>: Channel N select low bits, N determined by CHSEL <3> Channel N selects high bits;...
Page 346: Sigma-Delta Adc Control Register 3
CMS32H6157 User Manual | Chapter 12 SIGMA-DELTA ADC Sigma-Delta ADC control register 3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDADCCON3 BYPASSLDO OCP_DIS_LDO Reset value Bit7~Bit4 Reserved, and it must be 1000. Bit3 Reserved, and it must be 1.
Page 347: Sigma-Delta Adc Control Register 4
CMS32H6157 User Manual | Chapter 12 SIGMA-DELTA ADC Sigma-Delta ADC control register 4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDADCCON4 FCHOP_1 FCHOP_0 Reset value Bit7~Bit4 Reserved, and it must be 1000. Bit3-Bi2 Reserved, and it must be 00.
Page 348: D/A Converter
CMS32H6157 User Manual | Chapter 13 D/A Converter D/A Converter Function of D/A converter The D/A converter converts digital inputs to analog signals with 8-bit resolution and can control analog outputs. The D/A converter has the following functions:  8-bit resolution ...
Page 349: Structure Of D/A Converter
CMS32H6157 User Manual | Chapter 13 D/A Converter Structure of D/A converter Figure12-1shows the block diagram of the D/A converter. Figure12-1: Block diagram of D/A converter Remark: ELCREQ0 is a trigger signal is used in the real-time output mode (EVENTC's event signal).
Page 350: Registers For Controlling D/A Converter
CMS32H6157 User Manual | Chapter 13 D/A Converter Registers for controlling D/A converter The D/A converter is controlled by the following registers. • Peripheral enable register 1 (PER1) • D/A converter mode register (DAM) • D/A conversion value setting register 0 (DACS0) •...
Page 351: D/A Converter Mode Register (Dam)
CMS32H6157 User Manual | Chapter 13 D/A Converter D/A converter mode register (DAM) This register controls the operation of the D/A converter. The DAM register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "00H".
Page 352: Operation Of D/A Converter
CMS32H6157 User Manual | Chapter 13 D/A Converter Operation of D/A Converter Operation in Normal Mode The D/A conversion is initiated using the write operation of the DACSi register as the initiation trigger. The setup method is as follows: ①...
Page 353: Operation In Real-Time Output Mode
CMS32H6157 User Manual | Chapter 13 D/A Converter Operation in real-time output mode Each channel of the D/A conversion is performed on using the signals from the EVENTC as triggers. The setup method is as follows: ① Set the DACEN bit of the peripheral enable register 1 (PER1) to 1 to start the supply of the input clock to the D/A converter.
Page 354: D/A Conversion Output Timing
CMS32H6157 User Manual | Chapter 13 D/A Converter D/A conversion output timing Figure12-5shows the output timing of the D/A conversion. general mode real time output mode (DACEi=1) real time output mode (DACEi=0) DAMDi bit operational clock DACSi register write enable...
Page 355: Cautions For D/A Converter
CMS32H6157 User Manual | Chapter 13 D/A Converter Cautions for D/A Converter Observe the following cautions when using the D/A converter. (1) The digital port I/O function, which is the alternate function of the ANO0 pin, does not operate if the ports are set to analog pins by using the port mode control register (PMC).
Page 356: Comparator
CMS32H6157 User Manual | Chapter 14 Comparator Comparator This product has 2 built-in comparators CMP0 and CMP1. Function of comparator The comparators have the following functions: • The positive terminal input of CMPn can be selected from one of six inputs, and the external port can be selected.
Page 357: Structure Of Comparator
CMS32H6157 User Manual | Chapter 14 Comparator Structure of comparator Figure14-1 shows the block diagram of comparator 0. Figure14-1 shows the block diagram of comparator 1. Figure14-1: Block diagram of comparator 0 CMPSELn CnMON CnENB CnFCK CnEPO CnEDG CnIE PA00/VC0_INP0...
Page 358 CMS32H6157 User Manual | Chapter 14 Comparator Figure14-2: Block diagram of comparator 1 CMPSELn CnMON CnENB CnFCK CnEPO CnEDG CnIE PB02/VC1_INP0 Edge CMPn PB10/VC1_INP1 detection interrupt PB11/VC1_INP2 Selector circuit PB12/VC1_INP3 CMPn EVENTC PC00/VC1_INP4 event PC01/VC1_INP5 CMPn Noise Removal/ PB13/VC1_INN0 Digital Filters...
Page 359: Registers For Controlling Comparator
CMS32H6157 User Manual | Chapter 14 Comparator Registers for controlling comparator The registers controlling comparator are shown in Table14-2. The register addresses of the comparator are shown in Table14-3: List of registers for comparators. Table14-2: Registers for controlling comparator Register Name...
Page 360: Peripheral Enable Register 1 (Per1)
CMS32H6157 User Manual | Chapter 14 Comparator Peripheral enable register 1 (PER1) The PER1 register is the register that sets whether to enable or disable the supply of clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocks to hardware that is not in use.
Page 361: Comparator Mode Setting Register (Compmdr)
CMS32H6157 User Manual | Chapter 14 Comparator Comparator mode setting register (COMPMDR) The COMPMDR register is a register that enables/disables the comparator and detects the comparator output. Setting the CnENB bit to "0” is disabled when the comparator output is enabled (set the CnOE bit of the COMPOCR register to "1”).
Page 362: Comparator Filter Control Register (Compfir)
CMS32H6157 User Manual | Chapter 14 Comparator Comparator filter control register (COMPFIR) The COMPFIR register is a control register for the digital filter. The COMPFIR register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "00H".
Page 363 CMS32H6157 User Manual | Chapter 14 Comparator controller is not linking the outputs of comparator 0. In addition, the IF of the interrupt request flag register must be cleared to "0" after the change. If bits C0FCK1 to C0FCK0 are changed from "00B"...
Page 364: Comparator Output Control Register (Compocr)
CMS32H6157 User Manual | Chapter 14 Comparator Comparator output control register (COMPOCR) The COMPOCR register is a control register that sets the polarity of the comparator output, enables/disables the output and the interrupt output. In the following cases, the CnOE bit of the COMPOCR register "1” is disabled (output enable). (n= 0, 1) ➢...
Page 365 CMS32H6157 User Manual | Chapter 14 Comparator Note 1: When comparator 1 uses TIMER WINDOW mode, the bit7 (C1EDG) of register COMPFIR must be set to "1". The C1OE and C1OTWMD bits cannot be set at the same time, and the C1OE bit must be set to "1"...
Page 366: Comparator Negative Reference Selection Register (Cnrefs)
CMS32H6157 User Manual | Chapter 14 Comparator Comparator negative reference selection register (CnREFS) The CnREFS register is a register to set the negative terminal reference of the comparator. The CnREFS register can be rewritten when the comparator stops operating (CnENB=0). (n= 0, 1) The CnREFS register is set by an 8-bit memory manipulation instruction.
Page 367: Comparator Positive Input Selection Register (Cmpseln)
CMS32H6157 User Manual | Chapter 14 Comparator Comparator positive input selection register (CMPSELn) The CMPSELn register is a positive input selection register for the comparator. The CMPSELn register can be rewritten when the comparator stops operating (CnENB=0). (n= 0, 1) The CMPSELn register is set by an 8-bit memory manipulation instruction.
Page 368: Comparator Hysteresis Control Register (Cmpnhy)
CMS32H6157 User Manual | Chapter 14 Comparator Comparator hysteresis control register (CMPnHY) The CMPnHY register is a hysteresis function control register of the comparator. The CMPnHY register can be rewritten when the comparator stops operating (CnENB=0). The CMPnHY register is set by an 8-bit memory manipulation instruction.
Page 369: Operation
CMS32H6157 User Manual | Chapter 14 Comparator Operation Comparator 0 and comparator 1 can operate independently. CMP0 and OPA can be combined and linked. The setting steps of independent operation and linkage of the comparator are shown in Table14-4. Table14-4: Setup steps for comparator-related registers...
Page 370 CMS32H6157 User Manual | Chapter 14 Comparator Figure14-10 shows the operation of comparator n (n=0, 1). In the basic mode, when the analog input voltage is higher than the reference input voltage, the CnMON bit in the COMPMDR register is "1”. When the analog input voltage is lower than the reference input voltage, the CnMON bit is "0".
Page 371: Digital Filter Of Comparator N (N=0, 1)
CMS32H6157 User Manual | Chapter 14 Comparator Digital filter of comparator n (n=0, 1) The comparator n has a built-in digital filter that can select the sampling clock by the CnFCK1 to CnFCK0 bits of the COMPFIR register. The output signal of comparator n is sampled by each sample clock, and the digital...
Page 372: Event Signal Output To The Coordination Controller (Eventc)
CMS32H6157 User Manual | Chapter 14 Comparator Event signal output to the coordination controller (EVENTC) The event signal to EVENTC is generated by detecting the output edge of the digital filter set by the COMPFIR register under the same conditions as the interrupt request. However, unlike the interrupt request, the event signal is always output to EVENTC regardless of the CnIE bit of the COMPOCR register.
Page 373: Output Of Comparator N (N=0, 1)
CMS32H6157 User Manual | Chapter 14 Comparator Output of comparator n (n=0, 1) The CnOE bit of the COMPOCR register can be used to set whether the comparison result of the comparator is output to an external pin, and the CnOP bit of the COMPOCR register can be used to set the output polarity (positive or negative output).
Page 374: Stopping Or Supplying Comparator Clock
CMS32H6157 User Manual | Chapter 14 Comparator Stopping or Supplying comparator clock To stop the comparator by setting peripheral enable register 1 (PER1), use the following procedure: ① Set the CnENB bit in the COMPMDR register to “0” (stop the comparator).
Page 375: Operational Amplifier (Opa)
CMS32H6157 User Manual | Chapter 15 Operational Amplifier (OPA) Operational Amplifier (OPA) Function of operational amplifier This product has a built-in one channel operational amplifier (OPA) with the following functions: ⚫ Support rail-to-rail ⚫ The OPA works in constant current mode and Buffer mode. The Buffer mode can be used to test OPA offset ⚫...
Page 376: Register Of Operational Amplifier
CMS32H6157 User Manual | Chapter 15 Operational Amplifier (OPA) Register of operational amplifier Table15-1: Registers for controlling operational amplifier Register name Symbol Peripheral enable register 1 PER1 Operational amplifier control register OPACTL Operational amplifier digital-to-analog control register OPADAC Port mode control register...
Page 377: Operational Amplifier Control Register (Opactl)
CMS32H6157 User Manual | Chapter 15 Operational Amplifier (OPA) Operational amplifier control register (OPACTL) The OPACTL register is used to control the operational amplifier to start, stop and select the operating mode. The OPACTL register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "00H".
Page 378: Operational Amplifier Digital-To-Analog Control Register (Opadac)
CMS32H6157 User Manual | Chapter 15 Operational Amplifier (OPA) Operational amplifier digital-to-analog control register (OPADAC) The OPADAC register is used to control the op-amp's built-in 5-bit DAC. When the OPA has a built-in 5bit DAC for input selection, this register can be set to control the power selection of the 5bit DAC and the range of the DAC output voltage.
Page 379: General-Purpose Serial Communication Unit
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit General-Purpose Serial Communication Unit This product is equipped with 3 general-purpose serial communication units, each unit has 2 serial channels, each channel can realize 3-wire serial (SSPI), UART and simplified I C communication.
Page 380: Function Of General-Purpose Serial Communication Unit
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Function of general-purpose serial communication unit Each serial interface supported by this product has the following features. 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Synchronizes with the serial clock (SCLK) output from the master device for data transmission and reception.
Page 381: Uart (Uart0~Uart2)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit UART (UART0~UART2) This is a asynchronous function using two lines: serial data transmission (TxD) and serial data reception (RxD) lines. By using these two communication lines, data is sent and received asynchronously (using the internal baud rate) with other communicating parties by data frame (consisting of start bits, data, parity bits, and stop bits).
Page 382: Simplified I C (Iic00, Iic01, Iic10, Iic11, Iic20, Iic21)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) This is a function for clock synchronization communication with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master.
Page 383: Structure Of General-Purpose Serial Communication Unit
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Structure of general-purpose serial communication unit The general-purpose serial communication unit consists of the following hardware. Figure16-1: Structure of general-purpose serial communication unit Item Structure Shift register 16-bit Note Buffer register...
Page 384 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit The block diagram of general-purpose serial communication unit is shown in Figure 15-1. (Unit 0 is used as an example) Figure16-1: Block diagram of general-purpose serial communication unit Noise Filter Ena ble...
Page 385: Shift Register
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Shift register This is a 16-bit register that converts parallel data into serial data or vice versa. During reception, it converts data input to the serial pin into parallel data. When data is transmitted, the value set to this register is output as serial data from the serial output pin.
Page 386 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-2 : Format of the serial data register mn (SDRmn) After reset: 0000H SDRmn Shift register Remark: For the function of the higher 7 bits of the SDRmn register, please refer to "16.3 Registers for controlling general-purpose serial communication unit".
Page 387: Registers For Controlling General-Purpose Serial Communication Unit
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Registers for controlling general-purpose serial communication unit The registers controlling general-purpose serial communication unit are shown below: • Peripheral enable register 0 (PER0) • Serial Clock Select Register m (SPSm) •...
Page 388 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial Communication Unit Register List Unit 0 register base address: 0x40046000 Unit 1 register base address: 0x40046400 Unit 2 register base address: 0x40046800 Offset address Register name Reset value 0x000...
Page 389: Peripheral Enable Register 0 (Per0)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Peripheral enable register 0 (PER0) The PER0 register is the register that sets whether to enable or disable the supply of clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocks to hardware that is not in use.
Page 390: Serial Clock Selection Register M (Spsm)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial clock selection register m (SPSm) The SPSm register is a 16-bit register that selects two common operating clocks (CKm0, CKm1) available to each channel. Select CKm1 by bit7 to 4 of the SPSm register and select from bit3 to 0 CKm0.
Page 391: Serial Mode Register Mn (Smrmn)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial mode register mn (SMRmn) The SMRmn register is a register that sets the operating mode of channel n, selects the operating clock ), specifies whether the serial clock (F...
Page 392 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-5: Format of serial mode register mn (SMRmn) (2/2) After reset: 0020H Symbol SISmn SMRmn Note1 Note1 SISmn0 Level inversion control of channel n receives data in UART mode Detect the falling edge as the starting bit.
Page 393: Serial Communication Run Setting Register Mn (Scrmn)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial communication run setting register mn (SCRmn) The SCRmn register is the communication operation setting register of channel n, which sets the data transmission and reception modes, data and clock phases, whether to mask the error signal, parity test bits, start bits, stop bits, and data length.
Page 394 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-6: Format of serial communication run setting register mn (SCRmn) (2/3) After reset: 0087H Symbol SLCm SCRmn Note Setting of parity bits in UART mode PTCmn1 PTCmn0 Send Receiving No parity bits are output...
Page 395 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-6: Format of serial communication run setting register mn (SCRmn) (3/3) After reset: 0087H Symbol SLCm DLSm SCRmn Note1 Note 2 Serial function correspondence The setting of the data length...
Page 396: Serial Data Register Mn (Sdrmn)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial data register mn (SDRmn) The SDRmn register is the data register (16-bit) that channel n sends and receives. When the operation stops (SEmn=0), bit15~9 is used as a crossover setting register for the operating clock ).
Page 397: Serial Flag Clear Trigger Register Mn(Sirmn)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial flag clear trigger register mn(SIRmn) This is a trigger register used to clear each error flag for channel n. If each bit (FECTmn, PECTmn, OVCTmn) is set to "1", the corresponding bits (FEFmn, PEFmn, OVFmn) of the serial status register mn (SSRmn) are cleared to "0".
Page 398: Serial Status Register Mn (Ssrmn)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial status register mn (SSRmn) The SSRmn register indicates the communication status of channel n and the condition in which an error occurred. Errors represented are frame errors, parity errors, and overflow errors. Read the SSRmn registers via a 16-bit memory manipulation instruction.
Page 399 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-9: Serial status register mn (SSRmn) (2/2) After reset: 0000H Symbol SSRmn Note Note 1 FEFmn Detection flag for channel n frame errors No errors occurred. An error occurred (when the UART was received).
Page 400: Serial Channel Start Register M(Ssm)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial channel start register m(SSm) The SSm register is a trigger register to set the enable communication/start count for each channel. If a "1" is written to each bit (SSmn), the corresponding bit (SEmn) in the serial channel enable status register m (SEm) is set to a "1"...
Page 401: Serial Channel Stop Register M(Stm)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial channel stop register m(STm) The STm register isa trigger register for setting to enable communication/stop count for each channel. If a "1" is written to each bit (STmn), the corresponding bit (SEmn) in the serial channel enable status register m (SEm) is cleared to "0"...
Page 402: Serial Channel Enable Status Register M (Sem)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial channel enable status register m (SEm) The SEm register is used to confirm the allow or stop status of serial transmit and receive for each channel. If "1" is written to each of the serial start allow register m (SSm), the corresponding bit is set to "1". If you write "1"...
Page 403: Serial Output Enable Register M (Soem)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial output enable register m (SOEm) The SOEm register setting enable or stops the output of serial communication for each channel. For channel n that enable serial output, the value of the SOmn bit of the serial output register m (SOm) described below cannot be rewritten by software, but the value reflected by the communication operation is output from the serial data output pin.
Page 404: Serial Output Register M (Som)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial output register m (SOm) The SOm register is a buffer register for the serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n.
Page 405: Serial Output Level Register M (Solm)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial output level register m (SOLm) The SOLm register is a register for setting the data output level inversion for each channel. This register can be set only in UART mode. In SSPI mode and simple I C mode, the corresponding bits must be set to "0".
Page 406: Serial Standby Control Register M (Sscm)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Serial standby control register m (SSCm) The SSC0 register is the register that controls the start of receive operation from deep sleep mode during serial data reception at SSPI00 or UART0.
Page 407: Slave Select Function Enable Register M (Ssem)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Slave select function enable register m (SSEm) The SSEm register controls whether the input to the SSImn terminal is valid or invalid when used as a slave function in SSPImn communication.
Page 408: Input Switching Control Register (Isc)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Input switching control register (ISC) When LIN-bus communication is implemented via UART0, the ISC1 bits and ISC0 bits of the ISC registers are used for coordination of external interrupts and timer array units. If bit0 is placed at "1", the input signal of the serial data input (RxD0) pin is selected as the input to the external interrupt (INTP0), so it can pass THE INTP0 interrupt detects the wake-up signal.
Page 409: Noise Filter Enable Register 0 (Nfen0)
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Noise filter enable register 0 (NFEN0) The NFEN0 register sets whether the noise filter is used for the input signal of each channel's serial data input pin. For pins used for SSPI or simple I C communication, the corresponding bit must be "0"...
Page 410: Operation Stop Mode
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Operation stop mode Each serial interface of a general-purpose serial communication unit has an operation stop mode. Serial communication is not possible in operation stop mode, so power consumption is reduced. In addition, pins for the serial interface can be used as port functions in operation stop mode.
Page 411: Stopping The Operation By Channels
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure16-22: Each register setting when stopping the operation by channels (a) Serial channel stop register m (STm) This register is a trigger register that is used to enable stopping communication/count by each channel.
Page 412: 3-Wire Serial I/O(Sspi00, Sspi01, Sspi10, Sspi11, Sspi20, Sspi21) Communication
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit 3-wire serial I/O(SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) communication This is a clock synchronization communication function implemented by three lines of serial clock (SCLK) and serial data (SDI and SDO).
Page 413: Master Transmission
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Master transmission Master transmission refers to the operation of this product output transmission clock and sending data to other devices. 3-wire serial SSPI00 SSPI01 SSPI10 SSPI11 SSPI20 SSPI21 Object Channel 0 of...
Page 414 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure16-23: 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register setting content when the master transmits (a) serial mode register mn (SMRmn) SMRmn...
Page 415 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Procedure Figure16-24: The initial setup steps of the master transmission initial configuration starts release general-purpose serial configure PER0 register communication unit from reset state, and start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 416 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-26: Restart the setup step of the master transmission Starting setting for resumption wait till commuication target (slave slave device ready? device) stops or communication ends (Necessary) via Configure port register and port...
Page 417 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (3) Process flow (single send mode) Figure 16-27: Timing diagram of the master transmission (single send mode) (type 1: DAPmn= 0, CKPmn = 0) SSmn STmn SEmn transmit data1 transmit data2...
Page 418 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-28: Flowchart of the master transmission (single transmit mode) SSPI communication starts relevant initial configuration, refer to the previous diagram (select SCI initial configuration transmission completion interrupt) configure transmission data and data count, clear communication completion flag (via...
Page 419 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (4) Process flow (continuous transmit mode) Figure 16-29: Timing diagram of the master transmission (continuous transmit mode) (type 1: DAPmn= 0, CKPmn = 0) SSmn STmn SEmn transmit transmit data2...
Page 420 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-30: Flowchart of the master transmission (continuous transmit mode) SSPI communication starts relevant initial configuration, refer to the previous diagram (select SCI initial configuration transmission completion interrupt) configure transmission data and data count, clear communication completion flag...
Page 421: Master Reception
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Master reception Master reception refers to the operation of this product output transmission clock and receiving data from other devices. 3-Wire Serial I/O SSPI00 SSPI01 SSPI10 SSPI11 SSPI20 SSPI21 channel 0 of...
Page 422 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure 16-31: 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register setting content when the master receives (a) serial mode register mn (SMRmn)
Page 423 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Procedure Figure 16-32: Initial setup steps for master reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 424 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-34: Restart the setup step of the master transmission restart configuration starts. wait till commuication target (slave device) stops or communication ends (neccessary) slave device ready? via Configure port register and port mode...
Page 425 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (3) Process flow (single receive mode) Figure 16-35: Timing diagram of the master receive (single receive mode) (type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn data reception2...
Page 426 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-36: Flowchart of the master receive (single receive mode) SSPI communication starts relevant initial configuration, refer to the previous diagram SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear...
Page 427 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (4) Process flow (continuous receive mode) Figure 16-37: master receive (continuous receive mode) (type 1: DAPmn= 0, CKPmn = 0) SSmn STmn SEmn data reception3 SDRmn data reception2 virtual data...
Page 428 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-38: Flowchart of the master receiver (continuous receive mode) SSPI communication starts relevant initial configuration, refer to the previous diagram (select buffer empty interrupt) SCI initial configuration For the received data, set the storage area and the...
Page 429: Master Transmission And Reception
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Master transmission and reception The transmission and reception of the master refers to the operation of this product output transmission clock and data transmission and reception with other devices. 3-wire serial I/O...
Page 430 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure16-39: 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register settings for master sending and receiving (a) serial mode register mn (SMRmn) SMRmn...
Page 431 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Procedure Figure16-40: initial setup steps for master sending and receiving initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 432 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-42: Restart the setup steps of the master send and receive restart configuration starts. wait till commuication target (slave device) (neccessary) slave device ready? stops or communication ends via Configure port register and port mode...
Page 433 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (3) Process flow (single send and receive mode) Figure 16-43: Timing diagram of the master transmit and receive (single transmit and receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn...
Page 434 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-44: Flowchart of the master transmit and receive (single send and receive mode) SSPI communication starts relevant initial configuration, refer to the previous setting diagram (select SCI initial configuration transmission completion interrupt)
Page 435 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (4) Process flow (continuous send and receive mode) Figure16-45: Timing diagram of the master transmit and receive (continuous transmit and receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception 3...
Page 436 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-46: Flowchart of the master transmit and receive (continuous transmit and receive mode) SSPI communication starts relevant initial configuration, refer to the SCI initial configuration previous setting diagram (select buffer...
Page 437: Slave Transmission
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Slave transmission Slave transmission refers to the operation of the CMS32H6157 microcontroller to send data to other devices in the state of transmitting clocks from other device inputs. 3-wire serial I/O...
Page 438 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure16-47: 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register settings at the time of slave transmission (a) serial mode register mn (SMRmn)
Page 439 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Procedure Figure 16-48: Initial setup steps for slave sending initial configuration starts release universal serial communication configure PER0 register unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 440 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-50: Restarts the setup step of the slave send restart configuration starts. wait till commuication target (master device) master device stops or communication ends (mandatory) preparation complete? via Configure port register and port mode...
Page 441 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (3) Process flow (single send mode) Figure 16-51: Timing diagram of a Slave send (single send mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3...
Page 442 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-52: Flowchart of Slave send (single send mode) SSPI communication starts relevant intial configure, please refer to SCI initial configuration diagram (select the previous setting transmission completion interrupt) regarding transmit data, configure storage region and...
Page 443 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (4) Process flow (continuous send mode) Figure 16-53: Timing diagram of Slave send (continuous send mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn SDRmn transmit data2 transmit data3 transmit data1...
Page 444 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-54: Flowchart of Slave send (continuous send mode) SSPI communication starts relevant intial configure, please refer to SCI initial configuration the previous setting diagram (select buffer empty interrupt) regarding transmit data, configure storage region and data...
Page 445: Slave Reception
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Slave reception Slave reception refers to the operation of this product receiving data from other devices in the state of transmitting clocks from other devices. 3-wire serial I/O SSPI00 SSPI01...
Page 446 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure16-55: 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register setting content at slave receive time (a) serial mode register mn (SMRmn) SMRmn...
Page 447 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Procedure Figure16-56: Initial setup step of slave reception initial configuration starts release general-purpise serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 448 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-58: Restart the setup step of slave reception restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode...
Page 449 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (3) Process flow (single receive mode) Figure16-59: Timing diagram of slave receive (single receive mode) (type 1: DAPmn= 0, CKPmn = 0) SSmn STmn SEmn data reception3 SDRmn data reception1...
Page 450 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-60: Flowchart of slave receive (single receive mode) SSPI communication starts relevant initial configuration, refer to the previous SCI initial configuration setting diagram (select transmission completion interrupt) configure receiving data storage region, clear receiving...
Page 451: Slave Transmission And Reception
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Slave transmission and reception Slave transmission and reception refers to the operation of data transmission and reception by microcontrollers and other devices of this product in the state of transmitting clocks from other device inputs.
Page 452 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure16-61: 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register settings for Slave transmit and receive (a) serial mode register mn (SMRmn) SMRmn...
Page 453 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Procedure Figure16-62: Initial setup steps for slave sending and receiving initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 454 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-63: Stop steps for slave sending and receiving stop configuration starts if there are ongoing data transmission, (selection) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 455 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-64: Restart steps for slave sending and receiving restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode...
Page 456 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (3) Process flow (single send and receive mode) Figure16-65: Timing diagram of Slave transmit and receive (single transmit and receive mode) SSmn STmn SEmn data reception1 data reception3 data reception2...
Page 457 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-66: Flowchart of slave send and receive (single send and receive mode) SSPI communication starts Refer to the previous setting diagram (select buffer SCI initial configuration empty interrupt) For transmitting and receiving data, set the save area and the...
Page 458 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (4) Process flow (continuous send and receive mode) Figure16-67: Timing diagram of Slave send and receive (continuous transmit and receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception 3...
Page 459 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-68: Flowchart of Slave transmit and receive (continuous transmit and receive mode) SSPI communication starts relevant initial configuration, refer to the SCI initial configuration previous setting diagram (select buffer empty interrupt)
Page 460: Calculation Of Transmission Clock Frequency
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Calculation of transmission clock frequency 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) communication transmission clock frequency can be calculated using the following calculation equations. (1) Master （（...
Page 461 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Table 16-2: 3-wire serial I/O operating clocks SMRmn Note Running Clock (f SPSm register Register When F =32MHz is in CKSmn operation 32MHz 16MHz 8MHz 4MHz 2MHz 1MHz 500KHz 250KHz 125KHz 62.5KHz...
Page 462: Procedure For Handling Errors During 3-Wire Serial I/O Communication
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Procedure for handling errors during 3-wire serial I/O communication (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) In 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21), the processing steps when an...
Page 463: Operation Of Clock-Synchronous Serial Communication With Slave Selection Input Function
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Operation of clock-synchronous serial communication with slave selection input function Each channel is a channel that supports clock-synchronous serial communication with a slave select input function. [Data transmission and reception] •...
Page 464 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit By using the slave selection input function, a master device can be connected to multiple slave devices for communication. The master device outputs the slave selection signal to the slave device (1) of the communication object, and each slave device determines whether it is selected as the communication object and controls the output of the SDO pin.
Page 465 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-71: Timing diagram of the Slave selection input function DAPmn=0 configure transmit data BFFmn TSFmn SSEmn SCLKmn (CKPmn=0) SDImn sample timing sequence SDOmn SSmn During the period when SSImn is high, no transmission is performed even at the falling edge of SCKmn (serial clock), and no sampling of received data is performed synchronously with the rising edge.
Page 466: Slave Transmission
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Slave transmission Slave transmission refers to the operation of this product to send data to other devices in the state of transmitting clocks from other device inputs. Slave selection input function...
Page 467 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure16-72: Example of register settings when slave select input function (SSPImn) slave transmits (1/2) (a) serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn0 MDmn1 channel n operational clock （fMCK）...
Page 468 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-72: Example of register settings when slave select input function (SSPImn) slave transmits (2/2) (f) serial channel start register m (SSm) . Only set bit of target channel to 1.
Page 469 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Procedure Figure16-73: Initial setup steps for slave sending initial configuration starts release general-purpose serial communication unit from reset state, start configure PER0 register providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 470 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-74: Abort step of the slave send Stop configuration starts if there are ongoing data transmission, (selection) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 471 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-75: Restarts the setup step of the slave send restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode...
Page 472 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (3) Process flow (single send mode) Figure16-76: Timing diagram of a Slave send (single send mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn transmit data1 SDRmn transmit data 2 transmit data 3...
Page 473 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-77: lowchart of slave send (single send mode) SSPI communication starts relevant initial configure, please refer to the previous setting diagram (select SCI initial configuration transmission completion interrupt) regarding transmit data, configure storage region and data...
Page 474 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (4) Process flow (continuous send mode) Figure 16-78: Timing diagram of Slave send (continuous send mode) (type 1: DAPmn= 0, CKPmn = 0) SSmn STmn SEmn SDRmn transmit data2 transmit data3...
Page 475 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-79: Flowchart of slave send (continuous send mode) SSPI communication starts relevant intial configure, please refer to SCI initial configuration the previous setting diagram (select buffer empty interrupt) regarding transmit data, configure storage region...
Page 476: Slave Reception
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Slave reception Slave reception refers to the operation of this product receiving data from other devices in the state of transmitting clocks from other devices. Slave selection input function SSPImn...
Page 477 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure16-80: Slave Selection Input Function (SSPImn) Example of register setting content when slave receives (1/2) (a) serial mode register mn (SMRmn) SMRmn CKSmn CCSmn MDmn0 STSmn SISmn0...
Page 478 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-81: Slave Selection Input Function (SSPImn) Example of register setting content when slave receives (2/2) (f) serial channel start register m (SSm) . Only set bit of target channel to 1.
Page 479 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Procedure Figure16-82: Initial setup step of slave reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 480 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-84: Restart the setup step of Slave reception restart configuration starts. wait till commuication target (master device) master device stops or communication ends preparation complete? (mandatory) via Configure port register and port mode...
Page 481 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (3) Process flow (single receive mode) Figure16-85: Timing diagram of slave receive (single receive mode) (type 1: DAPmn= 0, CKPmn = 0) SSmn STmn SEmn data reception 3 SDRmn transmit data1...
Page 482 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-86: Flowchart of slave receive (single receive mode) SSPI communication starts relevant initial configuration, refer to the previous setting diagram (select transmission completion SCI initial configuration interrupt) configure receiving data storage region, clear receiving...
Page 483: Slave Transmission And Reception
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Slave transmission and reception Slave transmission and reception refers to the operation of data transmission and reception of this product and other devices in the state of input transmission clock from other devices.
Page 484 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure 16-87: Slave Selection Input Function (SSPImn) Example of register setting content when slave send and receive (1/2) (a) serial mode register mn (SMRmn) SMRmn CKSmn CCSmn...
Page 485 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-87: Slave Selection Input Function (SSPImn) Example of register setting content when slave send and receive (2/2) (f) serial channel start register m (SSm) . Only set bit of target channel to 1.
Page 486 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Procedure Figure16-88: Initial setup steps for slave sending and receiving initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 487 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-89: Stop steps for slave sending and receiving stop configuration starts if there are ongoing data transmission, (selection) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 488 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-90: Restart steps for slave sending and receiving restart configuration starts. wait till commuication target (master device) master device preparation (mandatory) stops or communication ends complete? via Configure port register and port mode...
Page 489 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (3) Process flow (single send and receive mode) Figure16-91: Timing diagram of Slave transmit and receive (single transmit and receive mode) SSmn STmn SEmn data reception1 data reception2 data reception3...
Page 490 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-92: Flowchart of slave send and receive (single send and receive mode) SSPI communication starts relevant initial configuration, refer to diagram the previous SCI initial configuration setting (select transmission completion interrupt)
Page 491 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (4) Process flow (continuous send and receive mode) Figure16-93: Timing diagram of Slave send and receive (continuous transmit and receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception 3...
Page 492 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-94: Flowchart of Slave send and receive (continuous transmit and receive mode) SSPI communication starts relevant initial configuration, refer to the previous setting diagram (select buffer SCI initial configuration empty interrupt)
Page 493: Calculation Of Transmission Clock Frequency
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Calculation of transmission clock frequency The transmit clock frequency of the slave select input function (SSPImn) communication can be calculated using the following calculation equation. (1) Slave （Transmit Clock Frequency)={ Serial Clock (SCLK) Frequency Rate Provided by the Master...
Page 494: Procedure For Handling Errors During Clock-Synchronous Serial Communication With The Slave Selection Input Function
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Procedure for handling errors during clock-synchronous serial communication with the slave selection input function The processing steps for errors that occur during clock synchronization serial communication with the slave select input function are shown in Figure16-95.
Page 495: Operation Of Uart (Uart0~Uart2) Communication
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Operation of UART (UART0~UART2) communication This is a asynchronous function using two lines: serial data transmission (TxD) and serial data reception (RxD) lines. By using these two communication lines, data is sent and received asynchronously (using the internal baud rate) with other communicating parties by data frame (consisting of start bits, data, parity bits, and stop bits).
Page 496: Uart Transmission
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit UART transmission UART transmission is the operation of this product microcontroller to asynchronously send data to other devices. An even number of the 2 channels used by UART is used for UART transmission.
Page 497 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure 16-96: Register setting content when UART is transmitted by UART (UART0~UART2) (1/2) (a) serial mode register mn (SMRmn) SMRmn CKSmn CCSmn MDmn0 MDmn2 MDmn1 channel n interrupt source...
Page 498 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure16-96: Register setting content when UART is transmitted by UART (UART0~UART2) (2/2) (e) serial output register m (SOm) Only configure bit of target channel 0: serial data output value as "0"...
Page 499 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Procedure Figure 16-97: UART transmission initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 500 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-99: Reset the setup steps for the new start UART transmission restart configuration starts. wait till commuication target (slave device) stops or (mandatory) Ready to communicate? communication ends The data output of the target channel is disabled by...
Page 501 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (3) Process flow (single send mode) Figure 16-100: UART send (single send mode) SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3 TxDq pin transmit data1 transmit data3 transmit data2...
Page 502 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (4) Process flow (continuous send mode) Figure 16-102: UART transmission (continuous send mode) SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3 TxDq pin transmit data1 transmit data2 transmit data3...
Page 503 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-103: Flowchart of UART sending (continuous send mode) UART communication starts relevant initial configuration, refer to the previous setting SCI initial configuration diagram (select transmission completion interrupt) configure transmission data and data count, clear communication...
Page 504: Uart Reception
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit UART reception UART receive is the operation of this product microcontroller asynchronously receiving data from other devices. The odd number of the 2 channels used by the UART is used for UART reception. However, the SMR registers for odd and even channels need to be set.
Page 505 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure16-104: Example of register setting contents for UART reception of UART (UART0~UART2) (1/2) (a) serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
Page 506 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-104: Example of register setting contents for UART reception of UART (UART0~UART2) (2/2) (e) serial output register m (SOm) Not used in this mode. (f) serial output enable register m (SOEm) Not used in this mode.
Page 507 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Procedure Figure 16-105: UART reception initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 508 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-107: Reset the setup steps for restarting UART reception restart configuration starts. wait till commuication target stops or commuication target (mandatory) communication ends ready？ re-configure when modifing operational clock...
Page 509 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (3) Process flow Figure 16-108: UART reception SSmn STmn SEmn transmit data 3 SDRmn transmit data1 transmit data 2 RxDq pin data reception 2 data reception 3 data reception 1...
Page 510 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-109: Flowchart of UART reception UART communication starts relevant initial configuration, refer to the SCI initial configuration previous setting diagram (select transmission completion interrupt) configure reciving data storage region and communication data...
Page 511: Low-Power Uart Mode Function
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Low-power UART mode function This is a mode that enables the UART to receive by detecting the input of the RxDq pin in deep sleep mode. Normally, the UART stops communicating in Deep Sleep mode, but if you use Low Power UART mode, you can receive UART while the CPU is not running.
Page 512 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Table 16-4: Setting of UART receive baud rate in low power UART mode UART receive baud rate in low power UART mode High-speed internal oscillator Baud rate 4800bps Operation SDRmn[15:9]...
Page 513 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Low power UART mode operation (EOCm1=0, SSECm=0/1) Because the EOCm1 bit is "0", regardless of the SSECm bit setting, and no error interrupt is generated even if a communication error occurs. However, the end-of-transmission interrupt (INTSRq) is generated.
Page 514 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-111: Flow chart of low-power UART mode operation (EOCm1=0, SSECm=0/1) Setting starts TSFmn = 0 for all channels? Write "1" to the STmn bit stop all channels to shift to deep sleep mode...
Page 515 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Low power UART mode operation (EOCm1=1, SSECm=1) Because the EOCm1 bit is "1", a communication error does not generate an error interrupt. Figure 16-112: Timing diagram for low-power UART mode operation (EOCm1=1, SSECm=1)
Page 516 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-113: Flow chart of low-power UART mode operation (EOCm1=1, SSECm=1) Setting starts TSFmn = 0 for all channels? Clear all error flags SIRm1=0007H Write "1" to the STmn bit...
Page 517: Calculation Of Baud Rate
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Calculation of baud rate (1) Equation for calculating baud rate The baud rate of UART (UART0~UART2) communication can be calculated using the following （ of the object channel Baud rate...
Page 518 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Table 16-5: UART operating clocks SMRmn Note SPSm register Running Clock (F Register CKSmn =32MHz runtime 32MHz 16MHz 8MHz 4MHz 2MHz 1MHz 500KHz 250KHz 125KHz 62.5KHz 31.25KHz 15.63KHz 7.81KHz 3.91KHz 1.95KHz...
Page 519 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Baud rate error when sending The baud rate error during UART (UART0~UART2) communication transmission can be calculated using the following calculation equation, and the baud rate of the sender must be set within the allowable baud （...
Page 520 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (3) Allowable range of baud rate when receiving The baud rate tolerance range for UART (UART0~UART2) communication reception can be calculated using the following equation, and the baud rate of the sender must be set within the baud 2 k Nfr （Maximum baud rate that can be received)=...
Page 521: Handling Steps When An Error Occurs During Uart (Uart0~Uart2) Communication
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Handling steps when an error occurs during UART (UART0~UART2) communication The processing steps for errors that occur during UART (UART0~UART2) communication are shown in Figure16-115andFigure 16-116. Figure16-115: Processing steps when a parity error or overflow error occurs...
Page 522: Operation Of Lin Communication
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Operation of LIN communication LIN transmission UART0 supports LIN communication in UART delivery. LIN sends channel 0 of usage unit 0. UART UART0 UART1 UART2 LIN Communication Support object channel...
Page 523 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit LIN is the abbreviation of Local Interconnect Network, which is a low-speed (1~20kbps) serial communication protocol to reduce automobile network cost. LIN communications are single-master communications, with up to 15 slave devices connected to a single master device.
Page 524 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-118: Flowchart sent by LIN hardware operation(reference) LIN transmit start Transmit wakeup signal frame (80H->TxD0) generate wakeup signal frame 8 bit Transmit wakeup TxD0 TSF00=0? Note signal frame transmit data wait for transmit result stop UART0(1->ST00 bit)
Page 525: Lin Reception
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit LIN reception In UART receiving, UART0 supports LIN communication. The LIN receives the channel 1 of the Unit0. UART UART0 UART1 UART2 LIN Communication Support Object channels Channel 1 of SCI0...
Page 526 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit A summary of the receive operations for the LIN is shown in Figure 14-115. Figure 16-119: Receive operation for LIN wake up signal frame interval field sync field identifier data field...
Page 527 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-120: LIN Flowchart for LIN Reception LIN Bus signal state and hardware operation. LIN communication starts wake up signal frame wait for wake up signal INTTM03 occurs? RxD0 pin NOTE.
Page 528 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit The port structure diagram for LIN receive operations is shown in Figure Figure 16-121. The wake-up signal sent by the LIN master is received through edge detection of the INTP0. The invention can measure the length of the synchronization segment sent by the LIN master and calculate the baud rate error through external event capture operation.
Page 529 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Peripheral features for LIN communication operations are summarized as follows: <Peripheral Features Used> • External interrupt (INTP0): Detection of wake-up signal Purposes: Detects edges of wake-up signals and the start of communication.
Page 530: Operation Of Simple I C (Iic00, Iic01, Iic10, Iic11, Iic20, Iic21) Communication
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Operation of simple I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication This is a function for clock synchronization communication with two or more devices by using two lines: serial clock (SCL) and serial data (SDA).
Page 531: Address Segment Sending
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Address segment sending Address segment sending is the first transmission operation in I C communication to specify the transmission object (slave device) in particular. After the start condition is generated, the address (7 bits) and the transmission direction (1 bit) are sent as 1 frame.
Page 532 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure 16-122: Example of register setting contents when sending address segments of Simple I (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) (a) serial mode register mn (SMRmn) SMRmn...
Page 533 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Procedure Figure 16-123: Initial set-up steps for address segment transmission initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 534 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (3) Process flow Figure 16-124: Timing Diagram for Address Segment Transmission address field transmit SDLr output bit operation SDAr output Somn bit operation address SDAr input shift operation shift register mn Remark: m: unit number(m=0, 1, 2)n: channel number(n=0, 1)r: IIC number(r=00, 01, 10, 11, 20, 21) www.mcu.com.cn...
Page 535 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-125: Flowchart for address segment delivery address field transmit relevant initial configuration, refer to initial configuration diagram 19-129 set SOmn bit to '0'. set SOmn bit to '0'. generate start condition...
Page 536: Data Transmission
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Data transmission Data transmission is the operation of transmitting data to the transmission object (slave device) after the address segment is transmitted. A stop condition is generated after all data is sent to the object slave and the bus is released.
Page 537 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure 16-126: Example of register setting contents for simple I C data transmission (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) (a) serial mode register mn (SMRmn) do not operate this register wihle data is transmitting or receiving.
Page 538 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Process flow Figure 16-127: Timing diagram of data transmission transmit data 1 SDLr output SDAr output SDAr input shift register mn shift operation Figure 16-128: Flow chart for data delivery address field transmit completes.
Page 539: Data Reception
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Data reception Data reception is a run that receives data from a transfer object (slave) after sending an address segment. A stop condition is generated and the bus is released after receiving all the data from the object slave.
Page 540 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (1) Register setting Figure 16-129: Example of register setting contents for simple I C data reception (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) (a) serial mode register mn (SMRmn) do not operate this register while data is transmitting or receiving.
Page 541 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit (2) Process flow Figure16-130: Timing diagram for data reception (a) Start of receiving data virtual data(FFH) receiving data SCLr output SDAr output SDAr input shift register mn shift operation (b) Status of receipt of final data...
Page 542 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Figure 16-131: Flow chart for data reception address field transmit completes. data reception stop operation in order to modify set STmn bit to 1. SCRmn register cofigure channel operation mode to write "0"...
Page 543: Generation Of Stop Condition
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Generation of stop condition After sending and receiving all the data with the object slave, a stop condition is generated and the bus is released. (1) Process flow Figure 16-132:Timing diagram for generating stop condition...
Page 544: Calculation Of Transfer Rate
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Calculation of transfer rate The transfer rate for simple I C (IIC00, IIC01, IIC10, IIC11, IIC20,IIC21) communication can be （ Transfer Rate Runtime Clock (F ) Frequency }÷(SDRmn[15:9]+1)÷2 calculated using the following formula.
Page 545 CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Table 16-6: Simple I C Operating Clock Selection SMRmn Note SPSm register Runtime Clock (F Register CKSmn =32MHz in operation 32MHz 16MHz 8MHz 4MHz 2MHz 1MHz 500KHz 250KHz 125KHz 62.5KHz 31.25KHz...
Page 546: Processing Steps When An Error Occurs In A Simple I
CMS32H6157 User Manual | Chapter 16 General-Purpose Serial Communication Unit Processing steps when an error occurs in a simple I (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication process The processing steps when an error occurs during a simple I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21)
Page 547: Serial Interface Spi
CMS32H6157 User Manual | Chapter 17 Serial Interface SPI Serial Interface SPI Function of SPI This product is equipped with a SPI, and has the following two modes. (1) Run stop mode This is a mode used when serial transfer is not in progress and reduces power consumption.
Page 548: Registers For Controlling Spi
CMS32H6157 User Manual | Chapter 17 Serial Interface SPI Registers for controlling SPI The SPI is controlled by the following registers. • Peripheral enable register 1 (PER1) • Serial operating mode register (SPIM) • Serial clock selection register (SPIC) •...
Page 549: Spi Operating Mode Register (Spim)
CMS32H6157 User Manual | Chapter 17 Serial Interface SPI SPI operating mode register (SPIM) SPIM is used to select the mode of operation and control the permission or prohibition of the operation. SPIM can be set by an 8-bit memory manipulation instruction.
Page 550: Spi Clock Selection Register (Spic)
CMS32H6157 User Manual | Chapter 17 Serial Interface SPI SPI clock selection register (SPIC) This register specifies the timing of data send/receive and sets the serial clock. can be set by an 8-bit storage operation instruction. A reset signal is generated to clear the register to 01H.
Page 551: Spi Status Register (Spis)
CMS32H6157 User Manual | Chapter 17 Serial Interface SPI SPI status register (SPIS) The SPIT register is used to confirm the communication status of the SPI. SPIS can be read by an 8-bit storage operation instructionsa. A reset signal is generated to clear the register to 00H.
Page 552: Transmit Buffer Register (Sotb)
CMS32H6157 User Manual | Chapter 17 Serial Interface SPI Transmit buffer register (SOTB) The register is set to send data. When setting bits 7 (SPIE) and bit 6 (TRMD) of the serial operating mode register (SPIM) to 1 When sending/receiving starts by writing data to SOTB.
Page 553: Operation Of Spi
CMS32H6157 User Manual | Chapter 17 Serial Interface SPI Operation of SPI In 3-wire serial I/O mode, data is sent or received in 8-bit or 16-bit units. The data is sent or received synchronously with the serial clock. After communication begins, bit 0 (SPTF) of SPIT is set to 1. When the communication of data is complete, set the communication completion interrupt request flag (SPIIF) and clear SPTF to 0.
Page 554: Master Tramission And Reception
CMS32H6157 User Manual | Chapter 17 Serial Interface SPI Master tramission and reception If the bit 6 (TRMDn) of the serial operating mode register (SPIMn) is 1, data can be sent or received. When a value is written to the transmit buffer register (SDROn), send/receive starts.
Page 555 CMS32H6157 User Manual | Chapter 17 Serial Interface SPI Figure 17-8: Stop step of the master transmit/receive Start of stop setting If there is data being SPTF=0? transferred, wait for the transfer to end Set the SPIE bit to "0" and...
Page 556 CMS32H6157 User Manual | Chapter 17 Serial Interface SPI (2) Processing Figure 17-9: Timing diagram of transmit/receive (single transmit mode) (INTMD=0,CPHA=1, CPOL=1) SPIE 写SDRO Write SDRO transmit data1 发送数据1 transmit data2 发送数据2 SDRO 移位运行移位运行 shift register 移位寄存器 shift operation shift operation 接收数据1...
Page 557: Master Reception
CMS32H6157 User Manual | Chapter 17 Serial Interface SPI Master reception If bit 6 (TRMD) of the serial operating mode register (SPIM) is 0, only data can be received. When data is read from the receive buffer register (SIO), the reception begins...
Page 558 CMS32H6157 User Manual | Chapter 17 Serial Interface SPI Figure 17-12: Stop step of master receive Start of stop setting Note 1 The penultimate (m- 1) reads out the data Set the SPIE to "0", stop the SPI Write the SPIM...
Page 559 CMS32H6157 User Manual | Chapter 17 Serial Interface SPI (2) Processing Figure 17-13: Timing diagram of the receiving (CPHA=1, CPOL=1) SPIE 读SDRI Read SDRI Receiving& Receiving& 接收&移位运行接收&移位运行移位寄存器 shift register shift operation shift operation receiving data1 接收数据1 receiving data2 接收数据2...
Page 560: Slave Transmission And Reception
CMS32H6157 User Manual | Chapter 17 Serial Interface SPI Slave transmission and reception If bits CKS2-0 of the serial clock selection register (SPIC) select slave mode, bit 6 (TRMD) of the serial operation mode register (SPIM) is 1, you enter slave send/receive mode. When a value is written to the transmit buffer register (SOTB), wait for the clock of the master device to start sending/receiving.
Page 561 CMS32H6157 User Manual | Chapter 17 Serial Interface SPI Figure 17-15: Stop step of slave send/receive Start of stop setting there data being SPTF=0? transferred, wait transfer to end Set the SPIE bit to "0" to Write the SPIM register...
Page 562 CMS32H6157 User Manual | Chapter 17 Serial Interface SPI (2) Processing Figure 17-16: Timing diagram of send/receive (single-send mode) (INTMD=0,CPHA=1, CPOL=1) SPIE 发送数据1 发送数据2 transmit data1 transmit data2 SDRO shift register shift operation 移位运行 shift operation 移位运行移位寄存器接收数据1 接收数据2...
Page 563: Slave Reception
CMS32H6157 User Manual | Chapter 17 Serial Interface SPI Slave reception If bits CKS2-0n of the serial clock selection register (SPIC) select slave mode and bit 6 (TRMD) of the serial operation mode register (SPIM) is 0, slave receive mode is entered. When reading data from the receive buffer register (SIO), wait for the clock of the master device to start receiving.
Page 564 CMS32H6157 User Manual | Chapter 17 Serial Interface SPI Figure 17-19: Stop step of slave reception Start of abort setting Note 1 The penultimate (m-1) reads out the data Set the SPIE bit to "0" to Write the SPIM register...
Page 565 CMS32H6157 User Manual | Chapter 17 Serial Interface SPI (2) Processing Figure 17-20: Diagram of the receiving (CPHA=1, CPOL=1) SPIE 读SDRI Read SDRI Receiving& Receiving& 接收&移位运行接收&移位运行 shift register 移位寄存器 shift operation shift operation 接收数据1 接收数据2 receiving data1 receiving data2...
Page 566: Serial Interface Iica
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Serial Interface IICA Function of IICA This product is equipped with a serial interfaces IICA0, and has the following three modes. Run stop mode This is a mode used when serial transfer is not in progress and reduces power consumption.
Page 567 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure 18-1: Diagram of the serial interface IICA www.mcu.com.cn 567 / 822 Rev.0.1.1...
Page 568 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA An example of the structure of a serial bus is shown in Figure 18-2. Figure 18-2: Example of a serial bus structure for I C-bus serial data bus master CPU2 master CPU1...
Page 569: Structure Of Iica
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Structure of IICA The serial interface IICA consists of the following hardware. Table 18-1: Structure of the serial interface IICA Item Structure IICA shift register n (IICAn) Register slave address register n(SVAn) Peripheral enable register 0 (PER0) IICA control register n0 (IICCTLn0).
Page 570: Iica Shift Register N (Iican)
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA IICA shift register n (IICAn) IICAn registers are registers that convert 8-bit serial data and 8-bit parallel data to and from a serial clock for sending and receiving. Actual sending and receiving can be controlled by reading and writing IICAn registers.
Page 571: Wake-Up Control Circuitry
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Wake-up control circuitry This circuit generates an interrupt request (INTIICAn) when the address value set to the slave address register n(SVAn) is the same as the received address or when an extension code is received.
Page 572: Stop Condition Generation Circuitry
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Stop condition generation circuitry If the SPTn bit is "1", the circuit generates a stop condition Bus status detection circuitry This circuit detects whether the bus is released by detecting the start and stop conditions. However, the bus state cannot be detected immediately at the very beginning of operation, so the initial state of the bus state detection circuit must be set by the STCENn bit.
Page 573: Registers For Controlling Iica
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Registers for controlling IICA The serial interface IICA is controlled by the following registers. • Peripheral enable register 0 (PER0) • IICA control register n0 (IICCTLn0). • IICA flag register n (IICFn).
Page 574: Iica Control Register N0 (Iicctln0)
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA IICA control register n0 (IICCTLn0) This is a register that starts or stops I C operation, sets the wait sequence, and sets other I C operations. The IICCTLn0 register is set by the 8-bit memory manipulation instruction. However, the SPIEn bits, WTIMn bits, and ACKEn bits must be set when the IICEn bit is "0"...
Page 575 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Note 2: In the state where the IICEn bit is "0", the signal for this bit is invalid. Note 3: The read values for LRELn bits and WRELn bits are always "0".
Page 576 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure 18-6: Format of IICA control register n0 (IICCTLn0) (3/4) The triggering of the start condition Note 1,2 STTn No start conditions are generated. When the bus is released (standby, IICBSYn bit is "0"): If this bit is "1", a start condition (boot as the master device) is generated.
Page 577 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure 18-6: Format of IICA control register n0 (IICCTLn0) (4/4) The trigger of the stop condition Note SPTn No stop conditions are generated. Generate a stop condition (end of transfer as master).
Page 578: Iica Status Register N(Iicsn)
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA IICA status register n(IICSn) This is the register that represents the I C state. The IICSn register can only be read by the 8-bit memory manipulation instruction during the STTn bit "1" and waiting.
Page 579 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure 18-7: Format of IICA status register n (IICSn) (2/3) Receive detection of extension codes EXCn The extension code was not received. Extended code received. Clear condition (EXCn=0). Set condition (EXCn=1).
Page 580 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA LRELn: Bit6 of IICA control register n0 (IICCTLn0) IICEn: Bit7 of IICA control register n0 (IICCTLn0) Figure 18-7: Format of IICA status register n (IICSn) (3/3) Detection of the Ack (ACK).
Page 581: Iica Flag Register N(Iicfn)
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA IICA flag register n(IICFn) This is the register that sets the I C operating mode and indicates the status of the I C-bus. The IICFn register is set by the 8-bit memory manipulation instruction. However, only the STTn clear flag (STCFn) and the I C-bus status flag (IICBSYn) can be read.
Page 582 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Note: Bit6 and bit7 are read-only bits. Notice: The STCENn bit can only be written when it is stopped (IICEn=0). If the STCENn bit is "1", the bus is considered to be free (IICBSYn=0) regardless of the actual bus state, so as to avoid the first starting condition ( STTn=1) when breaking other communications requires confirmation that there is no third party being communicated.
Page 583: Iica Control Register N1(Iicctln1)
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA IICA control register n1(IICCTLn1) This is a register used to set the I C operating mode and to detect the status of the SCLAn pin and SDAAn pin. The IICCTLn1 register is set by an 8-bit memory manipulation instruction. However, only CLDn bits and DADn bits can be read.
Page 584 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure 18-9: Format of IICA control register n1 (IICCTLn1) (2/2) Level detection of the SCLAn pin (valid only when the IICEn bit is "1"). CLDn The SCLAn pin was detected low.
Page 585: Iica Low-Level Width Setting Register N(Iicwln)
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA IICA low-level width setting register n(IICWLn) This register controls the SCLAn pin signal low level width (T ) and SDAAn pin signal from the serial interface IICA output. The IICWLn register is set by an 8-bit memory manipulation instruction.
Page 586: Registers For Controlling The Iica Pin Port Function
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Registers for controlling the IICA pin port function This product can multiplex the pin function of IICAn to multiple ports. The SCALn pin and SDAAn pin can be configured to the port separately by setting the port multiplexing function configuration registers (SCLAnPCFG and SDAAnPCFG).
Page 587: Function Of I C-Bus Mode
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Function of I C-bus mode Pin structure The serial clock pin (SCLAn) and serial data bus pin (SDAAn) are structured as follows. SCLAn……Input/output pins of the serial clock The outputs of both the master and slave devices are N-channel open-drain outputs, and the inputs are Schmidt inputs.
Page 588: Setting The Transmit Clock Via Iicwln Register And Iicwhn Register
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Setting the transmit clock via IICWLn register and IICWHn register (1) The method by which the master transmits the clock Transmit clock = IICWL +IICWH+ F At this point, the optimal setpoints for the IICWLn register and the IICWHn register are as follows: (All setpoints are rounded to decimals) •...
Page 589 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Enhanced quick mode: F =10MHz(Min.) Standard mode: F =1MHz(Min.) Remark: Because the rise time (T ) and fall time (T ) of the SDAAn signal and the SCLAn signal differ depending on the pull-up resistance and the routing capacitance, they must be calculated separately.
Page 590: Definition And Control Method Of I C-Bus
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Definition and control method of I C-bus The following describes the serial data communication format and the signals used for the I C-bus. The Start Condition, Address, Data generated on the serial data bus of the I C-bus The respective transmission timings for and "Stop Condition"...
Page 591: Start Condition
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Start condition When the SCLAn pin is high, a start condition is generated if the SDAAn pin changes from high to low. The starting conditions for the SCLAn pin and the SDAAn pin are the signals generated when the master device starts serially transmitting to the slave.
Page 592: Address
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Address The next 7 bits of data for the start condition are defined as addresses. The address is 7 bits of data output by the master device in order to select a particular slave device from a plurality of slave devices connected to the bus.
Page 593: Ack
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA The serial data status of the sender and receiver can be acknowledged by answer (ACK). The receiver returns a reply each time it receives 8 bits of data. Typically, the sender receives a reply after sending 8 bits of data. When the receiver returns the reply, it is deemed to have been received normally and continues processing.
Page 594: Stop Condition
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Stop Condition When the SCLAn pin is high, a stop condition is generated if the SDAAn pin changes from low to high. The stop condition is the signal generated when the master ends serial transmission to the slave. When used as a slave, a stop condition is detected.
Page 595: Await
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Await Notify the other master or slave that the other master or slave is preparing to send/receive data by waiting (waiting status). Notify the other party that it is in a waiting state by setting the SCLAn pin low. If both the master and slave wait states are released, the next transfer can begin.
Page 596 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure 18-19: Await (2/2) (2) A situation where both the master and slave devices are waiting for 9 clocks (Master: Transmit, Slave: Receive, ACKEn=1) master device and master slave device all enter...
Page 597: Method Of Release From Wait State
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Method of release from wait state In general, I C can release the wait with the following processing. • Write data to IICA shift register n (IICAn). • Set the bit5 (WRELn) of the IICA control register n0 (IICCTLn0) (de-wait).
Page 598: Generation Timing And Waiting Control Of Interrupt Requests (Intiican)
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Generation timing and waiting control of interrupt requests (INTIICAn) By setting the IICA control register n0 (IICCTLn0) bit3 (WTIMn), in Table 18-2 The timing shown generates INTIICAn and is subject to wait control.
Page 599: Detection Method For Address Matching
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (4) Release method of waiting There are 4 ways to release from waiting: • Write data to IICA shift register n (IICAn). • Set the bit5 (WRELn) of the IICA control register n0 (IICCTLn0) (de-wait).
Page 600: Extension Code
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Extension code (1) When the high 4 bits of the receiving address are "0000" or "1111", as the received extension code, the extended code receive flag (EXCn) is set to "1", and in the 8th The falling edge of the clock generates an interrupt request (INTIICAn).
Page 601: Arbitration
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Arbitration When multiple master devices generate start conditions at the same time (Set STTn bit to "1" before the STDn bit becomes "1"), the communication of the master device is carried out while adjusting the clock until the data is different.
Page 602 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Table 18-4: Status at the time of arbitration and timing of generation of interrupt requests The state in which the arbitration occurred Timing of the generation of interrupt requests Address during sending...
Page 603: Wake-Up Function
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Wake-up function This is a subordinate function of I C, which is the function of generating an interrupt request signal (INTIICAn) when the local station address and extension code are received. The processing efficiency is improved by not generating unwanted INTIICAn signals under different addresses.
Page 604 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure 18-22: Flow when the WUPn bit is set to "0" by address matching (including receiving extension codes) deep sleep mode state INTIICAn=1？ WUPn=0 wait wait for 5 fMCK clock. Read IICSn after confirming serial interface IICA operation status, process accordingly.
Page 605 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure 18-23: Operation as a master device after being released from deep sleep mode by an interrupt other than INTIICAn START SPIEn=1 WUPn=1 wait deep sleep instruction deep sleep mode state...
Page 606: Communication Appointment
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Communication appointment (1) Cases where the communication appointment function is allowed (bit0 (IICRSVn) = 0 of the IICA flag register n (IICFn)) To perform the next master communication without joining the bus, you can send a start condition when the bus is released through a communication appointment.
Page 607 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Timing of the communication appointment is shown in the following figure Figure 18-24: Timing of communication appointment program Write STTn=1 IICAn processing. hardware SPDn and communi STDnset cation INTIICAn processing. to '1'...
Page 608 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA The steps of the communication appointment are shown in below. Figure 18-26: Communication appointment step stop interrupt request set STTn flag to '1' STTn=1 (communication preserve) define communication define as in communication preserve state.
Page 609 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA • When not operating as a slave device after receiving an extension code (bit 6 (LRELn) of the IICCTLn0 register is set to "1" instead of returning an answer, and the bus is released after exiting...
Page 610: Other Cautions
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Other cautions (1) The case where the STCENn bit is "0" Just after I C is allowed to run (IICEn=1), it is considered a communication state (IICBSYn=1) regardless of the actual bus state. To perform master communication in a state where no stop condition is detected, the stop condition must be made and the master communication must be performed after the bus is released.
Page 611: Communication Operation
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Communication operation Here, the following three running steps are represented by a flowchart. (1) Master operation of a single-master system The flowchart used as a master device in a single master system is shown below.
Page 612 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (1) Master operation of a single-master system Figure 18-27: Master operation of the single master control system START release serial interface IICA from reset state, configure PER0 register start providing clock.
Page 613 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Remark: The format of sending and receiving must conform to the specifications of the product in communication n=0. www.mcu.com.cn 613 / 822 Rev.0.1.1...
Page 614 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (2) Master operation of multi-master system Figure 18-28: Operation of a multi-master system (1/3) START release serial interface IICA from reset state, configure PER0 register start providing clock. configure pins and multiplexed ports to be used.
Page 615 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure 18-28: Operation of a multi-master system(2/3) allow communication preservation prepare starting STTn=1 communication. (generate stop condition) ensure wait time via Wait Note. software. MSTSn=0？ does INTIICAn interrupt occur? wait to release bus.
Page 616 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure 18-28: Operation of a multi-master system(3/3) Start communication. Write IICAn (Specify address and transfer direction) does INTIICAn interrupt wait for detecing occur? acknowledgement MSTSn=1？ ACKDn=1？ TRCn=1？ ACKEn=1 WTIMn=0 WTIMn=1 start...
Page 617 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (3) Slave operation The processing steps for a slave run are as follows. Slave operations are basically event-driven, so they need to be handled through INTIICAn interrupts (large changes to the operating state such as stop condition detection in communications) need to be handled).
Page 618 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA At send time, the send is repeated until the master device does not return a reply. If the master does not return an Ack, the communication ends. At the time of receiving, receive the required amount of data. If the communication ends, no reply is returned at the next data.
Page 619 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure 18-29: Slave operation step (1) START release serial interface IICA from reset state, configure PER0 register start providing clock. configure pins and multiplexed ports to be used. Configure Port First port configured to be input mode and output latch set to "0“...
Page 620 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA An example of the steps for a slave to process via an INTIICAn interrupt is shown below (assuming no extension code is used here). Confirm the status by interrupting THROUGH INTIICAn and perform the following processing.
Page 621: Timing Of I C Interrupt Request (Intiican) Generation
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Timing of I C interrupt request (INTIICAn) generation The values of the data send and receive timing, the timing of the generation of the INTIICAn interrupt request signal, and the IICA status register n (IICSn) when the INTIICAn signal is generated are shown below.
Page 622 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (1) Mastet operation (a) Start~Address~Data~Data~Stop(transmit and receive) hen WTIMn=0 SPTn=1 ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B Note 3:IICSn=1000X000B(set WTIMn bit to 4:IICSn=1000XX00B(set SPTn bit to 1 ) 5:IICSn=00000001B Note: to generate stop condition, must set WTIMn bit to '1' and modify INTIICAn interrupt requet signal generation timing sequenc e.
Page 623 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (b) Start~Address~Data~Start~Address~Data~Stop(Restart) When WTIMn=0 STTn=1 SPTn=1 ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=1000X110B Note1 2:IICSn=1000X000B(set WTIMn bit to 3:IICSn=1000XX00B(set WTIMn bit to Note 2 and set STTn bit to 4:IICSn=1000X110B Note3...
Page 624 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (c) Start~Code~Data~Data~Stop(transmit expansion bit) When WTIMn=0 SPTn=1 ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=1010X110B 2:IICSn=1010X000B Note 3:IICSn=1010X000B(set WTIMn bit to 4:IICSn=1010XX00B(set SPTn bit to 1 ) 5:IICSn=00000001B Note： to generate stop condition, must set WITIMn bit to '1' and modify INTIICAn interrupt request signal generation timing sequence.
Page 625 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (2) Slave operation (when receiving a slave address) (a) Start~Address~Data~Data~Stop When WTIMn=0 ST AD6~AD0 R/W D7~D0 D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0001X000B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 626 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (b) Start~Address~Data~Start~Address~Data~Stop When WTIMn=0(same for SVAn after restart) ST AD6~AD0 R/W ACK D7~D0 ST AD6~AD0 R/W ACK D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0001X110B 4:IICSn=0001X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 627 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (c) Start~Address~Data~Start~Code~Data~Stop When WTIMn=0(the address is different after restart (extension code)) ST AD6~AD0 R/W ACK D7~D0 ST AD6~AD0 R/W ACK D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0010X010B 4:IICSn=0010X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 628 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (d) Start~Address~Data~Start~Address~Data~Stop When WTIMn=0(the addresses are different after restart (non-extension code)) ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=00000110B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 629 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (3) Slave operation(when receiving an extension code) Always participate in the communication when receiving an extension code. (a) Start~Code~Data~Data~Stop When WTIMn=0 ST AD6~AD0 R/W D7~D0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0010X000B 4:IICSn=00000001B Remark...
Page 630 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (b) Start~Code~Data~Start~Address~Data~Stop When WTIMn=0(same SVAn after restart) ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0001X110B 4:IICSn=0001X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) When WTIMn=1(same SVAn after restart)
Page 631 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (c) Start~Code~Data~Start~Code~Data~Stop When WTIMn=0(receive the extension code after restarting) ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0010X010B 4:IICSn=0010X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) When WTIMn=1(receive the extension code after restarting)
Page 632 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (d) Start~Code~Data~Start~Address~Data~Stop When WTIMn=0(the addresses are different after restart (non-extension code)) ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=00000X10B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 633 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (4) Not participate in the operation of the communication (a) Start~Code~Data~Data~Stop (5) Operation of the arbitration failure (operate as a slave after arbitration failure) When used as a master device in a multi-master system, the MSTSn bit must be read each time an...
Page 634 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (b) A condition in which arbitration fails during the sending of an extension code When WTIMn=0 ST AD6~AD0 R/W D7~D0 D7~D0 1:IICSn=0110X010B 2:IICSn=0010X000B 3:IICSn=0010X000B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 635 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (6) Operation of arbitration failure (not participating in the communication after arbitration failure) When used as a master device in a multi-master system, the MSTSn bit must be read each time an INTIICAn interrupt request signal is generated to confirm the arbitration result.
Page 636 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (c) When arbitration fails while transferring data When WTIMn=0 ST AD6~AD0 D7~D0 D7~D0 1:IICSn=10001110B 2:IICSn=01000000B 3:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) When WTIMn=1 ST AD6~AD0...
Page 637 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (d) When arbitration fails due to restart conditions when transferring data Non-extended codes (for example, SVAn is different) ST AD6~AD0 R/W D7~D0 ST AD6~AD0 D7~D0 1:IICSn=1000X110B 2:IICSn=01000110B 3:IICSn=00000001B Remark must generate...
Page 638 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (e) When arbitration fails due to a stop condition when transferring data ST AD6~AD0 D7~Dm 1:IICSn=10000110B 2:IICSn=01000001B Remark must generate only generate while SPIEn bit is '1' m=0~6 Remark: n=0 When arbitration fails because the data is low when you want to generate a restart condition...
Page 639 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (g) Arbitration failure due to a stop condition when trying to generate a restart conditi When WTIMn=0 STTn=1 ST AD6~AD0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(set WTIMn bit to 3:IICSn=1000XX00B(set STTn bit to 1 )
Page 640 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA (h) Arbitration failure due to low level data when trying to generate a stop condition When WTIMn=0 SPTn=1 ST AD6~AD0 D7~D0 D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(set WTIMn bit to 3:IICSn=1000X100B(set WTIMn bit to 0 )
Page 641: Timing Diagram
CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Timing diagram In the I C bus mode, the master device selects a slave device from among multiple slave devices for communication by giving the serial bus output address. The master device sends the TRCn bit (bit 3 of the IICA status register n (IICSn)) indicating the direction of data transfer after the slave device address to start serial communication with the slave device.
Page 642 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure18-31: example of a slave device→a master device (Master: Select 9 clocks to wait, Slave: Choose 9 clocks to wait)(1/4) (1) Start Condition ~ Address ~ Data master control Note IICAn ACKDn （ACK...
Page 643 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure18-31shows the descriptions of ① to ⑥ of "1) Start condition ~ Address ~ Data" ① If the master sets the start condition trigger set (STTn=1), the bus data line (SDAAn) drops and the start condition is generated (SDAAn is changed from "1"...
Page 644 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure18-31: Communication example of a master device → slave device (Master: Select 9 clocks to wait, Slave: Choose 9 clocks to wait) (2/4) (2) Address ~ data ~ data master control...
Page 645 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure18-31 shows the descriptions of ③ to ⑩ of "(2) Address~Data~Data" ③ On the slave, if the receiving address and the local station address (the value of the SVAn) are the same note, the ACK is sent to the master through the hardware.
Page 646 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure18-31: Communication example of a master device → slave device (Master: Select 9 clocks to wait, Slave: Choose 9 clocks to wait)(3/4) (3) Data ~ data ~ stop condition master control...
Page 647 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure18-31 shows shows the descriptions of (7) ~ (15) of "(3) Data ~ Data ~ Stop": ⑦ At the end of the data transfer, because the ACKEn bit of the slave is "1", the ACK is sent to the master through the hardware.
Page 648 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure18-31: Communication example of a master device → slave device (Master: Select 9 clocks to wait, Slave: Choose 9 clocks to wait)(4/4) (4) Data ~ restart condition ~ address master control IICAn <3>...
Page 649 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA The operation of "(4) Data ~ Restart condition ~ Address" in Figure 17-31 is explained as follows. After executing steps ⑦ and ⑧, execute <1> to <3>, and return to the data sending step in step (3).
Page 650 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure18-32: Communication example of a slave device→master device (Master: Select 8 clocks to wait, Slave: Choose 9 clocks to wait)(1/3) (1) Start Condition ~ Address ~ Data master control IICAn ACKDn （ACKdetection）...
Page 651 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure18-32 The descriptions of ① to ⑦ of "(1) Start Condition ~ Address ~ Data"are as follows. ①If the master sets the start condition trigger set (STTn=1), the bus data line (SDAAn) drops and the start condition is generated (SDAAn is changed from "1"...
Page 652 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure18-32: Communication example of a slave device→master device (Master: Select 8 clocks to wait, Slave: Choose 9 clocks to wait)(2/3) (2) Address ~ data ~ data master control IICAn ACKDn （ACKdetection）...
Page 653 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Note 2: To release the slave from waiting during transmission, you must write data to the IICAn instead of setting the WRELn bit. www.mcu.com.cn 653 / 822 Rev.0.1.1...
Page 654 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure18-32 The description of ③ to ⑫ of "(2) Address ~ Data ~ Data" is as follows. ③On the slave, if the receiving address and the local station address (the value of the SVAn) are the same Note , the ACK is sent to the master through the hardware.
Page 655 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure18-32: Communication example of a slave device→master device (Master: Select 8 → 9 clocks to wait, Slave: Select 9 clocks to wait)(3/3) (3) Data ~ data ~ stop condition master control...
Page 656 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Note 1: To release the wait, the IICAn must be set to "FFH" or the WRELn bit must be set. Note 2: After the release of the stop condition, the time from the SCLAn pin signal to generate the stop condition is at least 4.0us when set to standard mode and at least 0.6us when set to fast mode.
Page 657 CMS32H6157 User Manual | Chapter 18 Serial Interface IICA Figure18-32 The description of ⑧~⑲ of "(3) Data~Data~Stop Condition" is as follows. ⑧The master enters a waiting state (SCLAn = 0) on the falling edge of the 8th clock and generates an interrupt (INTIICAn: Transmit End-of-Off).
Page 658: Irda
CMS32H6157 User Manual | Chapter 19 IrDA IrDA The IrDA implements the transmission and reception of IrDA communication waveforms in accordance with IrDA (InfraredDataAssociation) 1.0 by cooperating with SCI. 19.1 Function of IrDA If the IrDA function is enabled by the IRE bit of the IRCR register, the TxD1 signal and RxD1 signal of the Universal Serial Communication Unit 1 (UART1) can encode or decode the waveform conforming to the IrDA1.0...
Page 659: Registers For Controlling Irda
CMS32H6157 User Manual | Chapter 19 IrDA 19.2 Registers for controlling IrDA IrDA functions are controlled through the following registers. • Peripheral enable register 0 (PER0) • IrDA control register (IRCR) 19.2.1 Peripheral enable register 0 (PER0) The PER0 register is the register that sets whether to enable or disable the supply of clocks to each peripheral hardware.
Page 660: Irda Control Register (Ircr)
CMS32H6157 User Manual | Chapter 19 IrDA 19.2.2 IrDA control register (IRCR) This is the register that controls the IrDA function. It performs polarity switching of received data and transmitted data, clock selection of IrDA, and selection of serial input/output pin function (usually serial function and IrDA function) switching.
Page 661: Operation Of Irda
CMS32H6157 User Manual | Chapter 19 IrDA 19.3 Operation of IrDA 19.3.1 Procedure for IrDA communication (1) Initial set-up process for IrDA communication Follow these steps to initially set up IrDA. (a) Set the IRDAEN bit of the PER0 register to "1".
Page 662: Transmission
CMS32H6157 User Manual | Chapter 19 IrDA 19.3.2 Transmission At transmission, the output signal (UART frames) from the SCI is converted to IR frames via IrDA (seeFigure 19-4). When the IRTXINV bit is "0" and the serial data is "0", the output bit period (1 bit width period) x3/16 high level pulse (initial value).
Page 663: Selection Of High Level Pulse Width
CMS32H6157 User Manual | Chapter 19 IrDA 19.3.4 Selection of high level pulse width If the pulse width at transmission is less than 3/16, the suitable setting (minimum pulse width) of IRCKS2~IRCKS0 bit and the setting high level pulse width are shown inTable 19-2.
Page 664: Cautions When Using Irda
CMS32H6157 User Manual | Chapter 19 IrDA 19.4 Cautions when using IrDA A runtime clock that allows or disables the provision of IrDA can be set through a peripheral admission register. The register cannot be accessed because the initial state is to disable clock provisioning. Prior to setting the register, it is necessary to set the state of the peripheral admission register to allow the provision of the IrDA running clock.
Page 665: Lcd Controller/Driver
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver LCD Controller/Driver 20.1 Function of LCD controller / driver The functions of the LCD controller / driver are shown below. (1) You can select either waveform A or waveform B. (2) The LCD driver voltage generation circuit is capable of internal boost, capacitive splitting and resistive splitting switching.
Page 666: Structure Of Lcd Controller / Driver
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.2 Structure of LCD controller / driver The LCD controller / driver consists of the following hardware Table 20-2: LCD controller/driver structure Item Structure LCD mode register 1 (LCDM1) Subsystem clock supply mode control register (OSMC)
Page 667 CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver Figure 20-1: Block diagram of LCD controller/driver www.mcu.com.cn 667 / 822 Rev.0.1.1...
Page 668: Registers For Controlling Lcd Controller/Driver
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.3 Registers for controlling LCD controller/driver The LCD controller/driver is controlled by the following 7 registers. • LCD mode register 0(LCDM0) • LCD mode register 1(LCDM1) • Subsystem clock supply mode control register (OSMC) •...
Page 669: Lcd Mode Register 0(Lcdm0)
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.3.1 LCD mode register 0(LCDM0) This is the register for setting the LCD operation. The LCDM0 register is set by an 8-bit memory manipulation instruction. After the reset signal is generated, the value of this register becomes "00H".
Page 670 CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver Table 20-3: Combination of display waveform, time slice, bias method and frame rate Display Mode Set value Drive voltage generation method External Display Time Bias Internal Capacitive LWAVE LDTY2 LDTY1 LDTY0 LBAS1 LBAS0...
Page 671: Lcd Mode Register 1(Lcdm1)
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.3.2 LCD mode register 1(LCDM1) This register enables or disables the display operation, the operation of the booster and capacitor splitting circuits and sets the display data area and low voltage mode.
Page 672 CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver MDSET1 and MDSET0 bits are "01B", the internal reference voltage generation operates internally and therefore consumes power. When setting the external resistor splitting method (MDSET1, MDSET0=00B for LCDM0) or capacitor splitting method (MDSET1, MDSET0=10B), LCDVLM must be set to "0".
Page 673: Subsystem Clock Supply Mode Control Register (Osmc)
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.3.3 Subsystem Clock Supply Mode Control Register (OSMC) OSMC registers is a register that reduces power consumption by stopping unneeded clock functions. If RTCLPC is set to "1", it stops clocking peripheral functions other than the real time clock, 15-bit interval timer, clock output/buzzer output and LCD controller/driver in STOP mode or HALT mode where the CPU is running with a sub-system clock, thus reducing power consumption.
Page 674: Lcd Clock Control Register 0 (Lcdc0)
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.3.4 LCD clock control register 0 (LCDC0) This is the register for setting the LCD clock. The frame rate is determined by the LCD clock and time slice. The LCDC0 register is set by an 8-bit memory manipulation instruction.
Page 675: Lcd Boost Level Control Register (Vlcd)
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.3.5 LCD Boost Level Control Register (VLCD) This is a register to select the generated reference voltage (to adjust the contrast) during the operation of the boost circuit. 16 reference voltages can be selected.
Page 676 CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver Notice: The VLCD register setting is valid only when the boost circuit is running. Bits 5 to 7 must be set to "0". The value of the VLCD register must be changed after the operation of the boost circuit is stopped (VLCON=0).
Page 677: Lcd Input Switching Control Register (Isclcd)
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.3.6 LCD input switching control register (ISCLCD) The input of Schmitt trigger buffer needs to be disabled in order to prevent through-current flow during the period when the CAPL, CAPH, and VLx pins are set to operate as LCD functions.
Page 678: 20.3.7 Lcd Port Function Register
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.3.7 LCD port function register This is the register that sets whether to use the Pmn pin as a port or as an LCD output. The SEGEN0, SEGEN1, SEGEN2 and SEGEN3 registers are set by 16-bit memory manipulation instructions.
Page 679: Lcd Display Data Register
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.4 LCD display data register The LCD display data register is mapped as follows Table 20-4. The LCD display can be changed by changing the contents of the LCD display data register.
Page 680 CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver Table 20-4: Relationship between the contents of the LCD display data register, segment output, and common output (2/2) (b) 6 time slices and 8 time slices bit7 bit6 bit5 bit4 bit3 bit2...
Page 681: Lcd Display Register Selection
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver The data in the graphic area A and the COM signal correspond to bit0->COM0, bit1->COM1, bit2->COM2, bit3->COM3. The data in the graphic area B and the COM signal correspond to bit4->COM0, bit5->COM1, bit6->COM2, bit7->COM3.
Page 682: 20.5.1 Data Display In Graphic Area A And Graphic Area B
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.5.1 Data display in graphic area A and graphic area B When both BLON bit and LCDSEL bit are "0", the data in graphic area A (the lower 4 bits of LCD display data register) is output as LCD display register.
Page 683: Lcd Drive Voltage Provided By
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.6 LCD drive voltage provided by V The LCD driver power supply generation method can be selected from internal resistance splitting method, external resistance splitting method, internal boost method and capacitance splitting method.
Page 684: 20.6.2 External Resistance Splitting Method
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.6.2 External resistance splitting method An example of LCD drive voltage connection according to each bias method is shown in Figure 20-12. Figure 20-12: Example of LCD driver power connection (external resistor splitting method)
Page 685: 20.6.3 Internal Boost Method
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.6.3 Internal boost method The chip is equipped with an internal boost circuit for LCD drive power. The LCD drive voltage is generated by an external capacitor (0.47uF±30%) of the internal boost circuit. The internal boost method can only use 1/3 bias method or 1/4 bias method.
Page 686: 20.6.4 Capacitance Splitting Method
CMS32H6157 User Manual | Chapter 20 LCD Controller/Driver 20.6.4 Capacitance splitting method The chip has a built-in capacitance splitting circuit for LCD drive power. The LCD drive voltage is generated by an external capacitor (0.47uF±30%) of the capacitance splitting circuit. Only 1/3 bias method can be used for capacitance splitting.
Page 687: Enhanced Dma
CMS32H6157 User Manual | Chapter 21 Enhanced DMA Enhanced DMA 21.1 Function of DMA DMA is the function of transferring data between memories without using the CPU. Start the DMA for data transfer via peripheral interrupts. When the DMA and CPU access the same unit in flash, SRAM0, SRAM1, or peripheral modules at the same time, their bus usage is higher than the CPU.
Page 688 CMS32H6157 User Manual | Chapter 21 Enhanced DMA Table 21-1: Specification of DMA (2/2) Item specification When a data transfer with a DMCTj register changed from "1" to "0", an interrupt of the Normal mode source is requested to the CPU and interrupt processing is performed.
Page 689: Structure Of Dma
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.2 Structure of DMA A block diagram of the DMA is Figure 21-1. Figure 21-1: Block diagram of DMA peripherial interrupt signal interrupt source/ transmit start data transmission source selection control peripherial...
Page 690: Registers For Controlling Dma
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3 Registers for controlling DMA The registers that control the DMA are shown in Table 21-2. Table 21-2: Registers for controlling DMA Register Name Symbol Peripheral enable register 1 PER1 DMA start enable register 0...
Page 691: Dma Control Data Areas And Dma Vector Table Areas Allocation
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3.1 DMA control data areas and DMA vector table areas allocation The DMABAR register is used to set the 416 byte area of the control data and vector table of the allocated DMA to the RAM area.
Page 692: Control Data Allocation
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3.2 Control data allocation Starting from the start address, follow DMACRj, DMBLSj, DMACTj, DMRLDj, DMSARj, DMDARj ( j=0~23) Registers are assigned control data sequentially. The start address is set by the DMABAR register, and the low 10 bits are set separately by the vector table assigned by each boot source.
Page 693 CMS32H6157 User Manual | Chapter 21 Enhanced DMA Table 21-4: Starting address of control data Address baseaddr+190H baseaddr+180H baseaddr+170H baseaddr+160H baseaddr+150H baseaddr+140H baseaddr+130H baseaddr+120H baseaddr+110H baseaddr+100H baseaddr+0F0H baseaddr+0E0H baseaddr+0D0H baseaddr+0C0H baseaddr+0B0H baseaddr+0A0H baseaddr+090H baseaddr+080H baseaddr+070H baseaddr+060H baseaddr+050H baseaddr+040H baseaddr+030H baseaddr+020H Remark: baseaddr: The setting value of the DMABAR registe www.mcu.com.cn...
Page 694: Vector Table
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3.3 Vector table Once the DMA is started, the control data is determined by reading the data from the vector table allocated by each boot source, and the control data is read to be allocated in the DMA control data area.
Page 695 CMS32H6157 User Manual | Chapter 21 Enhanced DMA Table 21-5: DMA startup source and vector addresses DMA start source (interrupt request generation Source number Vector address Priority source) Set address of DMABAR register External interrupt pin input edge detection 0...
Page 696: Peripheral Enable Register 1 (Per1)
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3.4 Peripheral enable register 1 (PER1) The PER1 register is a register that sets to enable or disable providing clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocks to hardware that is not in use.
Page 697: Dma Control Register J(Dmacrj)(J=0~23)
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3.5 DMA control register j(DMACRj)(j=0~23) DMACRj register controls the operation mode of DMA. Figure 21-5: Format of DMA control register j (DMACRj) Address: See“21.3.2 Control data allocation”. After reset: Indefinite value Symbol:...
Page 698 CMS32H6157 User Manual | Chapter 21 Enhanced DMA Control of the delivery source address SAMOD fixed Increasing When the MODE bit is "1" (repeat mode) and the RPTSEL bit is "1" (the transmission source is a repeating region), the setting of the SAMOD bit is invalid.
Page 699: Dma Block Size Register J (Dmblsj)(J=0~23)
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3.6 DMA block size register j (DMBLSj)(j=0~23) This register sets the block size of the data transfer that is started once. Figure 21-6: Format of DMA block size register j (DMBLSj) Address: see “21.3.2 Control data allocation”.
Page 700: Dma Transmit Count Register J(Dmactj)(J=0~23)
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3.7 DMA transmit count register j(DMACTj)(j=0~23) This register sets the number of data transfers for the DMA. 1 is minus each time DMA transfer is initiated. Figure 21-7: Format of DMA Transfer Times Register j (DMACTj) Address: see “21.3.2 Control data allocation”.
Page 701: Dma Transfer Count Reload Register J (Dmrldj)(J=0~23)
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3.8 DMA transfer count reload register j (DMRLDj)(j=0~23) This register sets the initial value of the transfer count register in repeat mode. In repeat mode, since the value of this register is reloaded into the DMACT register, the value must be the same as the initial value of the DMACT register.
Page 702: Dma Source Address Register J(Dmsarj)(J=0~23)
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3.9 DMA source address register j(DMSARj)(j=0~23) This register specifies the delivery source address at the time of data transfer. When the SZ bit of the DMACRj register is "01" (16 bits transmitted), the lowest bit is ignored and treated as a even address.
Page 703: Dma Destination Address Register J(Dmdarj)(J=0~23)
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3.10 DMA destination address register j(DMDARj)(j=0~23) This register specifies the destination address at which the data is transferred. When the SZ bit of the DMACRj register is "01" (16 bits transmitted), the lowest bit is ignored and treated as a even address.
Page 704: Dma Start Enable Register I (Dmaeni)(I=0~2)
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3.11 DMA start enable register i (DMAENi)(i=0~2) This is an 8-bit register that controls enable or disable the startup of the DMA through each interrupt source. The interrupt source corresponds to the DMAENi0~DMAENi7 bits as shown in Table 21-6.
Page 705 CMS32H6157 User Manual | Chapter 21 Enhanced DMA DMAENi2 DMA start enable i2 disable startup. enable startup. Depending on the condition under which the end-of-transmit interrupt occurs, the DMAENi2 bit becomes "0" (disable) DMAENi1 DMA start enable i1 disable startup.
Page 706: Dma Base Address Register (Dmabar)
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3.12 DMA base address register (DMABAR) This is a 32-bit register that sets the vector address that holds the start address of the DMA control data area and the address of the DMA control data area.
Page 707: Dmaeni Set Register I(Dmseti)(I=0~2)
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.3.13 DMAENi set register i(DMSETi)(i=0~2) This is a set register for the DMA start enable register DMAENi, and setting the corresponding bit to 1 will set the corresponding bit of DMAENi to 1.
Page 708: Operation Of Dma
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.4 Operation of DMA Once the DMA is started, the control data is read from the DMA control data area, the data is transmitted according to this control data, and the control data after the data transmission is written back to the DMA control data area.
Page 709: Normal Mode
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.4.2 Normal mode In 8-bit transmission, the transmission data of one boot is 1 to 65535 bytes; In 16-bit transmission, the transmission data initiated once is 2~131070 bytes; In 32-bit transfers, the transmission data for one boot is 4 to 262140 bytes.
Page 710 CMS32H6157 User Manual | Chapter 21 Enhanced DMA (1) Example 1 of the use of normal mode: Continuous A/D conversion results The DMA CH5 is started by the A/D conversion end interrupt, and the value of the A/D conversion result register is transferred to RAM.
Page 711 CMS32H6157 User Manual | Chapter 21 Enhanced DMA (2) Example 2 of the use of normal mode: UART0 transmits continuously The DMA CH6 is started through the UART0 transmit buffer null interrupt, and the RAM value is transferred to the UART0 transmit buffer.
Page 712: Repeat Pattern
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.4.3 Repeat pattern The transmission data for 1 boot is 1 to 65535 bytes. Specify the transmission source or transmission destination as the repeating area, and the number of transmissions is 1 to 65535 times. Once the specified number of transfers has ended, the DMCTj (j=0~23) register and the address designated as the repeat region are initialized and then repeated.
Page 713 CMS32H6157 User Manual | Chapter 21 Enhanced DMA DMDARj register=DST j=0~23 FFFFFFFFH SRC/DST 00000000H Control of the source Control of the The source The destination Settings for the DMACR register address destination address after address after DAMOD SAMOD RPTSEL MODE...
Page 714 CMS32H6157 User Manual | Chapter 21 Enhanced DMA (1) Example of the use of repeat mode: Use the stepper motor of the port to control the pulse output The DMA CH14 is started using Timer8's channel 0 interval timer function, and the pattern of motor control pulses stored in the code flash is transferred to the general purpose port.
Page 715: Chain Transmission
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.4.4 Chain transmission When the DMACRj (j=0~23) register has a CHNE bit of "1 (allow chain transfer), multiple data can be transferred continuously through one start source. Once the DMA is started, the control data is selected by reading the data from the corresponding vector address of the startup source, and the control data is allocated in the DMA control data area.
Page 716 CMS32H6157 User Manual | Chapter 21 Enhanced DMA (1) Example of using chain transfer: Continuous A/D conversion result for UART0 transmission The DMA CH5 and CH6 are started by the A/D conversion end interrupt, and the A/D conversion result is transferred to RAM for UART0 transmission.
Page 717: Cautions When Using Dma
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.5 Cautions when using DMA 21.5.1 DMA control data and vector table settings • The DMA base address register (DMABAR) must be changed with all DMA start sources set to disabled. •...
Page 718: Number Of Execution Clocks For Dma
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.5.3 Number of execution clocks for DMA The execution of the DMA at startup and the number of clocks required are shown in Table 21-9. Table 21-9: Execution and number of clocks required when DMA is started...
Page 719: Response Time Of Dma
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.5.4 Response time of DMA The DMA response time is shown in Table 21-12. DMA response time is the time from the time when the DMA initiates the source when the DMA is detected and the DMA transmission begins, excluding the number of execution clocks for the DMA.
Page 720: Operation In Standby Mode
CMS32H6157 User Manual | Chapter 21 Enhanced DMA 21.5.6 Operation in standby mode State DMA operation Sleep mode Capable of operation (disable operation in low-power RTC mode). Note 1 Deep sleep mode Can accept DMA start source, and perform DMA transfer Note 1: In deep sleep mode, DMA transmission can be performed after the DMA startup source is detected, and the deep sleep mode can be returned after the transfer is completed.
Page 721: Linkage Controller (Eventc)
CMS32H6157 User Manual | Chapter 22 Linkage Controller (EVENTC) Linkage Controller (EVENTC) Function of EVENTC EVENTC links the events output by each peripheral function to each other between the peripheral functions. It can be connected through event chaining without going through the CPU and directly perform collaborative operation between peripheral functions.
Page 722: Control Register
CMS32H6157 User Manual | Chapter 22 Linkage Controller (EVENTC) Control register The control registers are shown in Table 22-1. Table 22-1: Control registers of EVENTC Register Name Symbol Event output target selection register 00 ELSELR00 Event output target selection register 01...
Page 723: Output Target Selection Register N(Elselrn)(N=00~15)
CMS32H6157 User Manual | Chapter 22 Linkage Controller (EVENTC) Output target selection register n(ELSELRn)(n=00~15) The ELSELRn register links each event signal to the event receiver peripheral function (link target peripheral function) that runs when an event is accepted. You cannot link multiple event inputs to the same event output destination (event receiver).
Page 724 CMS32H6157 User Manual | Chapter 22 Linkage Controller (EVENTC) Table 22-2: Correspondence of ELSELRn registers (n=00~15) and peripheral functions Register Name Event occurrence source (output source for event input n). Content External interrupt edge detection 0 ELSELR00 INTP0 External interrupt edge detection 1...
Page 725 CMS32H6157 User Manual | Chapter 22 Linkage Controller (EVENTC) Table 22-3: Correspondence between the setting value of ELSELRn register (n=00~15) and the operation when the link target peripheral function accepts the event ELSELRn register Link target Linking target peripheral Running when accepting events...
Page 726: Operation Of Eventc
CMS32H6157 User Manual | Chapter 22 Linkage Controller (EVENTC) Operation of EVENTC The paths used by the event signals generated by each peripheral function as interrupt requests for the interrupt control circuit and the paths used as EVENTC events are independent of each other. Therefore, each event signal is independent of the interrupt control and can be used as an event signal for the operation of the peripheral function of the event recipient.
Page 727 CMS32H6157 User Manual | Chapter 22 Linkage Controller (EVENTC) The responses of the peripheral functions that accept the events are shown in Table 22-4. Table 22-4: Response of the peripheral function of the received event Event Function of event link...
Page 728: Interrupt Function
CMS32H6157 User Manual | Chapter 23 Interrupt Function Interrupt Function The Cortex-M0+ processor has a built-in nested vector interrupt controller (NVIC), which supports up to 32 interrupt request (IRQ) inputs and one non-maskable interrupt (NMI) input, in addition to multiple internal exceptions.
Page 729 CMS32H6157 User Manual | Chapter 23 Interrupt Function Table 23-1: List of interrupt sources (1/2) Interrupt source Interrupt Basic Interrupt Internal/External source structure handling Name Trigger Note 1 type Note 2 INTLVI Voltage detection Internal INTP0 Detection of pin input edges...
Page 730 CMS32H6157 User Manual | Chapter 23 Interrupt Function Table 23-1 List of interrupt sources (2/2) Interrupt Basic Interrupt source Interrupt source Internal/External structure handling Name Trigger Note 1 type INTIICA0 End of IICA0 communication INTSPI00 End of SPI communication INTTM00...
Page 731 CMS32H6157 User Manual | Chapter 23 Interrupt Function Figure 23-1: Basic structure of interrupt function (A) Internal maskable interrupt Internal bus CPU.IRQ Standby release signal (B) External Maskable Interrupt (INTPn) Internal bus External Interrupt Edge Enable register (EGN, EGP) edge CPU.IRQ...
Page 732: Registers For Controlling Interrupt Function
CMS32H6157 User Manual | Chapter 23 Interrupt Function 23.3 Registers for controlling interrupt function Interrupt function is controlled by the following four registers. • Interrupt request flag register (IF00~IF31) • Interrupt Mask Flag Register (MK00~MK31) • External interrupt rising edge enable register (EGP0) •...
Page 733: Interrupt Mask Flag Register (Mk00~Mk31)
CMS32H6157 User Manual | Chapter 23 Interrupt Function 23.3.2 Interrupt mask flag register (MK00~MK31) The interrupt mask flag is set to enable or disable the corresponding maskable interrupt processing. Set MK00L~MK31L registers by an 8-bit memory manipulation instruction or MK00~MK31 registers by a 32- bit memory manipulation instruction.
Page 734 CMS32H6157 User Manual | Chapter 23 Interrupt Function Table 23-2: Correspondence between interrupt sources and flag registers Number Interrupt source Interrupt request flag register Interrupt Mask Flag Register INTLVI IF00.IFL MK00.MKL INTP0 IF01.IFL MK01.MKL INTP1 IF02.IFL MK02.MKL INTP2 IF03.IFL MK03.MKL INTP3 IF04.IFL...
Page 735: External Interrupt Rising Edge Enable Register (Egp0), External Interrupt Falling Edge Enable Register (Egn0)
CMS32H6157 User Manual | Chapter 23 Interrupt Function 23.3.3 External interrupt rising edge enable register (EGP0), External interrupt falling edge enable register (EGN0) These registers set the active edges of INTP0 to INTP5. The EGP0, EGN0 registers are set by 8-bit memory manipulation instruction.
Page 736: Operation Of Interrupt Handling
CMS32H6157 User Manual | Chapter 23 Interrupt Function 23.4 Operation of interrupt handling 23.4.1 Acceptance of maskable interrupt requests If the interrupt request flag is set to "1" and the mask (MK) flag for the interrupt request is cleared to "0", the interrupt request is accepted and can be passed to the NVIC.
Page 737: Key Interrupt Function
CMS32H6157 User Manual | Chapter 24 Key Interrupt Function Key Interrupt Function The number of channels for key interrupt input varies by product. Function of key interrupt A key interrupt (INTKR) can be generated by inputting a falling edge to the key interrupt input pins (KR0~KR7).
Page 738 CMS32H6157 User Manual | Chapter 24 Key Interrupt Function Figure 24-1: Block diagram of key interrupt INTKR KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register www.mcu.com.cn 738 / 822 Rev.0.1.1...
Page 739: Register Controlling Key Interrupts
CMS32H6157 User Manual | Chapter 24 Key Interrupt Function Register controlling key interrupts The key interrupt function is controlled by the following registers. • Key Return Mode Register (KRM) • Port Mode Register (PMx) Key return mode register (KRM) The KRM0~KRM7 bits control the KR0~KR7 signals.
Page 740: Standby Function
CMS32H6157 User Manual | Chapter 25 Standby Function Standby Function Standby function The standby function is a function that further reduces the operating current of the system, and there are two modes as follows. (1) Sleep mode Sleep mode is the mode in which the CPU is stopped from running the clock. If the high-speed system clock oscillation circuit, high-speed internal oscillator, or subsystem clock oscillation circuit is oscillating before the sleep mode is set, the clocks continue to oscillate.
Page 741: Sleep Mode
CMS32H6157 User Manual | Chapter 25 Standby Function Sleep mode Setting of sleep mode When the SLEEPDEEP bit of the SCR register is 0, execute the WFI instruction and enter sleep mode. In sleep mode, the CPU stops operating, but the values of the internal registers are still maintained, and the peripheral modules remain in the state they were in before they entered sleep mode.
Page 742 CMS32H6157 User Manual | Chapter 25 Standby Function Table25-1: Operation status in sleep mode (1/2) Execution of WFI instructions while the CPU is running at the main system clock Sleep mode setting CPU with external master CPU with high speed internal...
Page 743 CMS32H6157 User Manual | Chapter 25 Standby Function Disable Run: Stops running before shifting to sleep mode. : High-speed internal oscillator clock F : Low-speed internal oscillator clock : X1 clock F : External master system clock : XT1 clock F : External subsystem clock www.mcu.com.cn...
Page 744 CMS32H6157 User Manual | Chapter 25 Standby Function Table 25-1: Operation status in sleep mode (2/2) Execution of WFI instructions while the CPU is running at the subsystem clock Sleep mode setting CPU running on external subsystem clock Item CPU running at XT1 clock (F System Clock Stop providing clocks to the CPU.
Page 745: Release Of Sleep Mode
CMS32H6157 User Manual | Chapter 25 Standby Function Release of sleep mode Sleep mode can be released by any interrupt and external reset terminal, POR reset, low voltage detect reset, RAM parity error reset, WDT reset, software reset. (1) Dismissed by interrupt...
Page 746: Deep Sleep Mode
CMS32H6157 User Manual | Chapter 25 Standby Function Deep sleep mode Setting of deep sleep mode When theSLEE PDEEP bit of the SCR register is 1, the WFI instruction is executed and deep sleep mode is entered. In this mode, the CPU, most of the peripheral modules, and the vibrator stop functioning. However, the values of the CPU internal registers, the RAM data, the peripheral modules, the state of the I/O are maintained.
Page 747 CMS32H6157 User Manual | Chapter 25 Standby Function Table 25-2: Operating status in deep sleep mode Deep sleep mode setting Execution of WFI instructions while the CPU is running at the main system clock CPU runs on a high-speed CPU running at X1 clock...
Page 748 CMS32H6157 User Manual | Chapter 25 Standby Function Remark: Stop Run: Automatically stops running when shifting to deep sleep mode. Disable run: Stops running before shifting to deep sleep mode. : High-speed internal oscillator clock F : Low-speed internal oscillator clock...
Page 749: Release Of Deep Sleep Mode
CMS32H6157 User Manual | Chapter 25 Standby Function Release of deep sleep mode Deep sleep mode can be released in 2 ways. (a) Release by unmasked interrupt request If an unmasked interrupt request occurs, deep sleep mode is released. After the oscillation stabilization time, if the interrupt is allowed to be accepted, the vector interrupt is processed.
Page 750: Reset Function
CMS32H6157 User Manual | Chapter 26 Reset Function Reset Function The following 8 methods generate the reset signal. (1) External reset is input via the RESETB pin. (2) Internal reset is generated by programmed runaway detection of the watchdog timer.
Page 751 CMS32H6157 User Manual | Chapter 26 Reset Function Figure 26-1: Block diagram of reset function internal bus reset control flag register （RESF） SYSRF WDTRF RPERF IAWRF LVIRF reset reset reset reset reset watchdog timer reset signal erase erase erase erase erase...
Page 752: Reset Timing
CMS32H6157 User Manual | Chapter 26 Reset Function Reset timing When the RESETB pin is input low, a reset is generated. The reset state is then released if the RESETB lead is entered high and the program begins with a high-speed internal oscillator clock after the reset process is complete.
Page 753 CMS32H6157 User Manual | Chapter 26 Reset Function Figure 26-3: Reset timing due to overflow of watchdog timer, assertion of system reset request bits, detection of RAM parity errors, or detection of illegal memory access wait till osc precision stablized...
Page 754 CMS32H6157 User Manual | Chapter 26 Reset Function Table 26-1: Operational status during reset During reset Item Stop providing clocks to the CPU. System clock Stop running. Main system Stop operation (pins X1 and X2 are in input port mode).
Page 755: Register For Confirming The Reset Source
Register for confirming the reset source Reset control flag register (RESF) The CMS32H6157 microcontroller has multiple internal reset generation sources. The Reset Control Flag register (RESF) holds the reset source where the reset request occurs. The RESF register can be read by an 8- bit memory manipulation instruction.
Page 756 CMS32H6157 User Manual | Chapter 26 Reset Function The status of the RESF register when a reset request occurs is shown in Table 26-2. Table 26-2: RESF register status when a reset request occurs System reset Access to the Reset Source...
Page 757: Power-On Reset Circuit
(RESF) is cleared to "00H" Remark: The CMS32H6157 has built-in hardware to generate several internal reset signals. When the internal reset signal is generated by the watchdog timer (WDT), voltage detection (LVD) circuit, system reset request bit, RAM parity error or illegal memory access, the flag to indicate the reset source is assigned in the RESF register;...
Page 758: Structure Of Power-On Reset Circuit
CMS32H6157 User Manual | Chapter 27 Power-on Reset Circuit Structure of power-on reset circuit The block diagram of the power-on reset circuit is shown in Figure 27-1. Figure 27-1: Block diagram of power-on reset circuit internal reset signal basic voltage source www.mcu.com.cn...
Page 759: Operation Of Power-On Reset Circuit
CMS32H6157 User Manual | Chapter 27 Power-on Reset Circuit Operation of power-on reset circuit The timing of the internal reset signal generation for the power-on reset circuit and the voltage detection circuit is shown below. Figure 27-2: Timing of internal reset signal generation for power-on reset circuit and voltage detection circuit(1/3)
Page 760 CMS32H6157 User Manual | Chapter 27 Power-on Reset Circuit Note 5: When the power supply voltage rises, the power supply voltage must be maintained by external reset before it reaches the working voltage range shown in the AC characteristics of the data sheet; When the supply voltage drops, it must be reset through deep sleep mode transfer, voltage detection circuitry, or external reset before the supply voltage falls below the operating voltage range.
Page 761 CMS32H6157 User Manual | Chapter 27 Power-on Reset Circuit Figure 27-3: Timing of internal reset signal generation for power-on reset circuit and voltage detection circuit (2/3) (2) LVD is the case of interrupt & reset mode (LVIMDS1, LVIMDS0=1, 0 for option bytes 000C1H)
Page 762 CMS32H6157 User Manual | Chapter 27 Power-on Reset Circuit Figure 27-4: Timing of internal reset signal generation for power-on reset circuit and voltage detection circuit (3/3) (3) LVD reset mode (LVIMDS1, LVIMDS0=1, 1 for option byte 000C1H) power supply voltage(V...
Page 763: Voltage Detection Circuit
CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Voltage Detection Circuit Function of voltage detection circuit The voltage detection circuit sets the operating mode and detection voltage (V ) by option LVDH LVDL byte (000C1H). The Voltage Sense (LVD) circuit has the following functions.
Page 764: Structure Of Voltage Detection Circuit
CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Structure of voltage detection circuit The block diagram of the voltage detection circuit is shown in Figure 28-1. Figure 28-1: Block diagram of voltage detection circuit internal reset N-ch signal voltage...
Page 765: Registers For Controlling Voltage Detection Circuit
CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Registers for controlling voltage detection circuit The voltage detection circuit is controlled by the following registers. • Voltage detection register (LVIM) • Voltage detection level register (LVIS) Voltage detection register (LVIM) This register is set to enable or disable overwriting of the voltage detection level register (LVIS), and to confirm the masking status of the LVD output.
Page 766: Voltage Detection Level Register (Lvis)
CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Voltage detection level register (LVIS) This is a register that sets the voltage sense level. The LVIS register is set by an 8-bit memory manipulation instruction. After generating a reset signal, the value of this register changes to “00H/01H/81H”Note 1.
Page 767 CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Table 28-1: Format of user option bytes (000C1H/010C1H) (1/2) Note Address: 000C1H/010C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD settings (interrupt & reset mode) Detection voltage Setting value of option byte...
Page 768 CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Table 28-1: Format of user option byte (000C1H) (2/2) Address: 000C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD settings (interrupt mode) Detection voltage Setting value of option byte Mode setting...
Page 769: Operation Of Voltage Detection Circuit
CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Operation of voltage detection circuit Settings when used in reset mode The operation mode (reset mode (LVIMDS1, LVIMDS0=1, 1)) and the detection voltage (V ) are set via the option byte 000C1H. If the reset mode is set, operation starts with the following initial settings.
Page 770: Settings When Used In Interrupt Mode
CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Settings when used in interrupt mode The operation mode (interrupt mode (LVIMDS1, LVIMDS0=0, 1)) and the detection voltage (V ) are set via the option byte 000C1H. If the interrupt mode is set, operation starts with the following initial settings.
Page 771 CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Figure 28-5: Timing of interrupt signal generation (LVIMDS1, LVIMDS0=0, 1 for option byte) Note2 power supply Note2 voltage(V low limit of working voltage range =1.51V(TYP.) =1.50V(TYP.) Time LVIMK logo Note1 (mask interrupt)
Page 772: Settings For Interrupt & Reset Mode
CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Settings for interrupt & reset mode The operation mode (interrupt & reset mode (LVIMDS1, LVIMDS0=1, 0)) and the detection voltage (V LVDH ) are set via the option byte 000C1H. LVDL If the interrupt &...
Page 773 CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit The timing of the internal reset signal and interrupt signal generation in LVD interrupt & reset mode is shown inFigure 28-6. Figure 28-6: Reset & Interrupt Signal Generation Timing (LVIMDS1, LVIMDS0=1, 0)(1/2) if after release mask no reset is generated, then it can be tell that VDD has recovered to value VLVDH.
Page 774 CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Note 1: After the reset signal is generated, the LVIMK flag becomes "1". Note 2: When using the interrupt & reset mode, you must follow “Figure 28-7: Setting procedure for confirmation /reset of operating voltage” after an interrupt occurs.
Page 775 CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Figure 28-6: Reset & Interrupt Signal Generation Timing (LVIMDS1, LVIMDS0=1, 0)(2/2) after release mask while VDD＜VLVDH, due to LVIMD=1(reset mode), the reset will be generated. power supply voltage(VDD) VLVD VLVD low limit of working voltage range VPOR=1.51V(TYP.)
Page 776 CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Note 1: After the reset signal is generated, the LVIMK flag becomes "1". Note 2: When using the interrupt & reset mode, you must follow “Figure 28-7: Setting procedure for confirmation /reset of operating voltage” after an interrupt occurs.
Page 777 CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Figure 28-7: Setting procedure for confirmation/reset of operating voltage INTLVI occurs push stack operation perform necessary push stack operation set LVISEN bit to "1",mask voltage LVISEN = 1 detection(LVIOMSK=1). set LVILV bit to "0", configure high voltage detection...
Page 778 CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit If the interrupt & reset mode is set (LVIMDS1, LVIMDS0=1, 0), it will take 400us or 5 F clocks for the voltage detection to stabilize after the LVD reset (LVIRF=1) is released. The LVIMD bit must be cleared to "0" for initialization after waiting for the voltage detection to stabilize.
Page 779: Cautions For Voltage Detection Circuits
CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit Cautions for voltage detection circuits (1) About voltage fluctuations when power is turned on For systems where the supply voltage (VDD) fluctuates over time near the LVD detection voltage, it is possible to repeatedly enter the reset state and the reset release state. Through the following processing, any setting can be set to reset to the time when the microcontroller starts running.
Page 780 CMS32H6157 User Manual | Chapter 28 Voltage Detection Circuit (2) Delay from generating the LVD reset source to generating or releasing the LVD reset A delay occurs from the time the supply voltage (V ) < LVD detection voltage (V ) is met to the time ) ≤...
Page 781: Security Feature
Security Feature Overview In order to comply with IEC60730 and EC61508 safety standards, the CMS32H6157 has the following built-in security features. The purpose of this function is to safely stop the operation when a fault is detected through the self-diagnosis of the microcontroller.
Page 782: Registers Used For Security Functions
CMS32H6157 User Manual | Chapter 29 Security Feature Registers Used for Security Functions The following registers are used for each function of the security function. Register Name Function • Flash CRC control register (CRC0CTL). Flash CRC operation function • Flash CRC Operation Result Register (PGCRCL).
Page 783: Operation Of Security Features
CMS32H6157 User Manual | Chapter 29 Security Feature Operation of security features Flash CRC operational function (high-speed CRC) The IEC60730 standard requires verification of the data in the flash memory and recommends CRC as a means of verification. This high-speed CRC can check the entire code flash area in the initial setup (initialization) procedure.
Page 784: Flash Crc Operation Result Register
CMS32H6157 User Manual | Chapter 29 Security Feature Flash CRC operation result register (PGCRCL) This is the register where the results of high-speed CRC operations are stored The PGCRCL register is set by a 16-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "0000H".
Page 785 CMS32H6157 User Manual | Chapter 29 Security Feature The flowchart of the flash memory CRC operation function (high-speed CRC) is shown inFigure29-3. ＜Operation Flow＞ Figure29-3: Flow chart of flash CRC operation function (high-speed CRC) Start save expected value of CRC...
Page 786: Crc Operation Function (General-Purpose Crc)
CMS32H6157 User Manual | Chapter 29 Security Feature CRC operation function (general-purpose CRC) In order to ensure safety during operation, the IEC61508 standard requires that the data need to be confirmed even during CPU operation. This general-purpose CRC can perform CRC operations as a peripheral function during CPU operation.
Page 787: Crc Input Register (Crcin)
CMS32H6157 User Manual | Chapter 29 Security Feature CRC input register (CRCIN) This is an 8-bit register that sets the CRC calculation data for the general-purpose CRC. The range that can be set is "00H~FFH". The CRCIN register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes "00H".
Page 788 CMS32H6157 User Manual | Chapter 29 Security Feature ＜Operation process＞ Figure29-6: Flowchart of CRC operation function (Universal CRC) Start appointed start and end address save start and end address to general register write "0000H" into CRCD register perform initalization of CRCD register...
Page 789: Ram Parity Error Detection Function
RAM parity error detection function The IEC60730 standard requires validation of RAM data. Therefore, the CMS32H6157's RAM is appended with 1 bit of parity bits for every 8 bits. The RAM parity error detection feature appends parity bits when writing data, checks parity bits when reading data, and can generate resets when parity errors occur.
Page 790 CMS32H6157 User Manual | Chapter 29 Security Feature Figure29-8: Flow of RAM parity check parity check start Note PRERF=1 disable reset due to parity check error RAM parity check RAM parity check Read RAM parity check error occurs confirm parity check...
Page 791: Sfr Protection Function
CMS32H6157 User Manual | Chapter 29 Security Feature SFR protection function In order to ensure safety during operation, the IEC61508 standard requires that even if the CPU is out of control, it is necessary to protect important SFR from being rewritten. The SFR protection function is used to protect data from the control registers of the comparator function, port function, interrupt function, clock control function, voltage detection circuitry, and RAM parity error detection function.
Page 792: Frequency Detection Function
CMS32H6157 User Manual | Chapter 29 Security Feature Frequency detection function The IEC60730 standard requires confirmation that the oscillation frequency is normal. The frequency detection function uses the CPU/peripheral hardware clock frequency (F ) and can determine whether the ratio of the two clocks is correct by measuring the Channel 1 input pulse of Timer8.
Page 793: A/D Test Function
CMS32H6157 User Manual | Chapter 29 Security Feature A/D test function The IEC60730 standard requires testing of A/D converters. This A/D test function is performed on the positive (+) reference voltage, negative (–) reference voltage, analog input channel (ANI), output voltage of the temperature sensor, and internal reference voltage of the A/D converter A/D conversion to confirm that the A/D converter is running normally.
Page 794 CMS32H6157 User Manual | Chapter 29 Security Feature Figure29-11: Structure of the A/D test function ・ADISS ・ADS4~0 ANI09/AVREFP ANI08/AVREFM ANIxx ANIxx temperature sensor ・ADTES1~0 internal reference voltage(1.2V) A/D convertor Positive (+) reference voltage ・ADREFP convertor A/D convertor Negative (-) reference voltage ・ADREFM...
Page 795: A/D Test Register (Adtes)
CMS32H6157 User Manual | Chapter 29 Security Feature A/D test register (ADTES) This register selects the positive (+) reference voltage, negative (–) reference voltage, analog input channel (ANIxx), output voltage of the temperature sensor, and internal reference voltage (1.45V) of the A/D converter ) as an A/D conversion object.
Page 796: Product Unique Identification Register
CMS32H6157 User Manual | Chapter 29 Security Feature Product Unique Identification Register The unique identification of the product is perfect for: • Used as a serial number (e.g. USB character serial number or other terminal applications). • Used as a password, this unique identifier is used in conjunction with a software encryption and decryption algorithm when writing flash memory to improve the security of the code in the flash memory.
Page 797: Temperature Sensor And Internal Reference Voltage
CMS32H6157 User Manual | Chapter 30 Temperature sensor and internal reference voltage Temperature sensor and internal reference voltage Temperature sensor The on-chip temperature sensor measures and monitors the core temperature of the product, thus ensuring reliable operation of the product. The voltage output by the temperature sensor is proportional to the core temperature, and there is a linear relationship between the voltage and temperature.
Page 798: Register For Temperature Sensor
CMS32H6157 User Manual | Chapter 30 Temperature sensor and internal reference voltage Register for temperature sensor Temperature sensor calibration data register TSN25 Address: 0x500C6C After Symbol reset: TSN25 TSN25[11:0] Read-only registers for recording calibration data for temperature sensors1 are automatically loaded when powered on or reset is initiated, with each chip having its own calibration data.
Page 799: Instructions For Using The Temperature Sensor
CMS32H6157 User Manual | Chapter 30 Temperature sensor and internal reference voltage Instructions for using the temperature sensor How temperature sensors are used The temperature (T) is proportional to the sensor voltage output (Vs), so the temperature is calculated as...
Page 800: How To Use Temperature Sensor
CMS32H6157 User Manual | Chapter 30 Temperature sensor and internal reference voltage How to use temperature sensor Method 1: In this product, the TSN25 register stores the voltage conversion value (CAL25) of the temperature sensor measured at T =25° C and VDD=3.0v. The TSN85 register stores the voltage conversion value of the temperature sensor measured at T =85°...
Page 801: Internal Reference Voltage
CMS32H6157 User Manual | Chapter 30 Temperature sensor and internal reference voltage Internal reference voltage The Band-gap reference voltage (V ) is an internal fixed reference voltage, independent of the external supply. The V output can be converted by connecting it internally to an ADC, so that V...
Page 802: Option Bytes
Option Bytes Function of option bytes CMS32H6157 flash memory 000C0H~000C4H, 500004H is the option byte region. The option bytes consist of user option bytes (000C0H~000C2H) and flash data protection option bytes (000C3H, 500004H) composition. When powered on or reset is initiated, the specified function is set with reference to the option byte.
Page 803: Flash Data Protection Option Bytes (000C3H, 500004H)
CMS32H6157 User Manual | Chapter 31 Option Bytes Flash data protection option bytes (000C3H, 500004H) ⚫ Control of flash data protection when debugging on-chip Level0: Allows read/write/erase operations on flash data via debugger Level1: Allows chip full erase of flash data via debugger, read and write operations are not allowed.
Page 804: Format Of The User Option Bytes
CMS32H6157 User Manual | Chapter 31 Option Bytes Format of the user option bytes Figure 31-1: Format of user option bytes (000C0H) Address: 000C0H Symbol WDSTBYO WDTINT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 Interval interrupt of watchdog timer WDTINT Interval interrupt is not used.
Page 805 CMS32H6157 User Manual | Chapter 31 Option Bytes Figure31-2: Format of user option bytes (000C1H) (1/4) Address: 000C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD settings (interrupt & reset mode) Detect voltage Setting value of option byte Mode Setting...
Page 806 CMS32H6157 User Manual | Chapter 31 Option Bytes Figure31-2: Format of user option bytes (000C1H) (2/4) Address: 000C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (reset mode) Detect voltage Setting value of option byte Mode Setting VPOC2...
Page 807 CMS32H6157 User Manual | Chapter 31 Option Bytes Figure 31-2: Format of user option bytes (000C1H) (3/4) Address: 000C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt mode) Detect voltage Setting value of option byte Mode Setting...
Page 808 CMS32H6157 User Manual | Chapter 31 Option Bytes Figure 31-2: Format of user option bytes (000C1H) (4/4) Address: 000C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • Setting when LVD is OFF (external reset input using the RESETB Detect voltage...
Page 809 CMS32H6157 User Manual | Chapter 31 Option Bytes Figure 31-3: Format of user option bytes (000C2H) Address: 000C2H FRQSEL2 FRQSEL1 FRQSEL0 High-speed internal oscillator frequency FRQSEL2 FRQSEL1 FRQSEL0 HOCO 32MHz 32MHz 32MHz 16MHz 32MHz 8MHz 32MHz 4MHz 32MHz 2MHz 32MHz...
Page 810: Format Of Flash Data Protection Option Bytes
CMS32H6157 User Manual | Chapter 31 Option Bytes Format of flash data protection option bytes The format of the flash data protection option bytes is as follows. Figure 31-4: Format of flash data protection option bytes Address: 000C3H Symbol OCDEN[7:0]...
Page 811: Flash Control
CMS32H6157 User Manual | Chapter 32 FLASH Control FLASH Control Description of FLASH control This product contains a 128KByte FLASH memory, divided into 256 sectors, each sector has a capacity of 512Byte. This module supports erase, program and read operations of this memory. In addition, this module supports the protection for FLASH memory erase and write protection for control registers.
Page 812: Registers For Controlling Flash
CMS32H6157 User Manual | Chapter 32 FLASH Control Registers for controlling FLASH The registers that control FLASH are as follows: • Flash write protection register (FLPROT). • Flash operation control register (FLOPMD1, FLOPMD2). • Flash erase mode control register (FLERMD).
Page 813: Flash Operation Control Register (Flopmd1,Flopmd2)
CMS32H6157 User Manual | Chapter 32 FLASH Control FLASH operation control register (FLOPMD1,FLOPMD2) Flash operation control registers to set the erase and write operations of FLASH. 0x40020004 Address: After reset: 00000000H FLOPMD1[7:0] SymbolFLOPMD1 0x40020008 Address: After reset: 00H FLOPMD2[7:0] SymbolFLOPMD2...
Page 814: Flash Erase Control Register (Flermd)
CMS32H6157 User Manual | Chapter 32 FLASH Control Flash erase control register (FLERMD) Flash erase control register to set the type of FLASH erase operation. Address: 0x4002000C After reset: 00H Symbol ERMD1 ERMD0 FLERMD ERMD1 ERMD0 OPERATE Sector erase Settings are disabled...
Page 815: Flash Status Register (Flsts)
CMS32H6157 User Manual | Chapter 32 FLASH Control Flash status register (FLSTS) The status register allows to query the status of the FLASH controller. 0x40020000 Address: After reset: 00H Symbol Note FLSTS FLASH erase operation finished flag FLASH erase operation not completed FLASH erase operation completed Note: The OVF needs to be cleared by writing "1"...
Page 816: Flash Sector Erase Time Control Register (Flsercnt)
CMS32H6157 User Manual | Chapter 32 FLASH Control Flash sector erase time control register (FLSERCNT) The FLSERCNT register allows you to set the FLASH full erase time. 0x40020014 Address: After reset: indefinite R/W Symbol FLSERCNT load FLSERCNT[9:0] Note Selection of erase time settings...
Page 817: Flash Write Time Control Register (Flprocnt)
CMS32H6157 User Manual | Chapter 32 FLASH Control Flash write time control register (FLPROCNT) The FLPROCNT register allows you to set the FLASH WORD write time. 0x4002001C Address: After reset: indefinite R/W Symbol FLPROCNT Load1 FLPGSCNT[8:0] Load0 FLPROCNT[8:0] Write Time (Tprog) Setting Note...
Page 818: Flash Erase Protection Control Register (Flsecpr)
CMS32H6157 User Manual | Chapter 32 FLASH Control Flash erase protection control register (FLSECPR) When the Sector is protected, all erase operations on the Sector are invalid. 0x40020210 Address: After reset: 00000000H KEY[31:16] KEY[15:8] SECPR[3:0] Symbol FLSECPR Register SECPR write protection...
Page 819: How To Operate Flash
CMS32H6157 User Manual | Chapter 32 FLASH Control How to operate FLASH Sector erase Sector erase, and the erase time are implemented by hardware or can be configured by FLSERCNT. The operation flow is as follows: (1) Set up FLERMD. ERMD0 is 1'b0, select thesector erase mode;...
Page 820: Chip Erase
CMS32H6157 User Manual | Chapter 32 FLASH Control Chip erase Chip erase, and the erase time are implemented by hardware and can also be configured via FLCERCNT. The operation process is as follows (1) Set up FLERMD. ERMD0 is 1'b 1, select chip erase mode;...
Page 821: Flash Read
CMS32H6157 User Manual | Chapter 32 FLASH Control Flash Read The fastest finger frequency supported by flash built into this device is 20 MHz. When the HCLK frequency exceeds 20 MHz, the hardware inserts a 1 wait period when the CPU accesses flash.
Page 822: Revision History
CMS32H6157 User Manual | Chapter 33 Revision History Revision History Version Date Revised Content V0.1.0 February 2023 Initial Version Correct a clerical error in 20.3.2 Modify some section descriptions in 32.3.3 Flash erase control register (FLERMD) Modify the register value in section32.3.4 Flash status register (FLSTS) V0.1.1...

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