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ABB REL 352 Instruction Manual

Numerical phase comparison transmission line protection system
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October 1996
Instruction Manual
40-201.9
NUMERICAL PHASE COMPARISON
TRANSMISSION LINE PROTECTION SYSTEM
REL 352
Version 1.00
ABB Network Partner
Power Automation and Protection Division
4300 Coral Ridge Drive
Coral Springs, Florida 33065

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Summary of Contents for ABB REL 352

  • Page 1 October 1996 Instruction Manual 40-201.9 NUMERICAL PHASE COMPARISON TRANSMISSION LINE PROTECTION SYSTEM REL 352 Version 1.00 ABB Network Partner Power Automation and Protection Division 4300 Coral Ridge Drive Coral Springs, Florida 33065...
  • Page 3 Failure to do so may result in injury to personnel or damage to the equipment, and may affect the equipment warranty. If the REL 352 relay system is mounted in a cabinet, the cabinet must be bolted to the floor, or otherwise secured before REL 352 installation, to prevent the system from tipping over.

  • Page 4: Table Of Contents

    Equipment Identification The REL 352 equipment is identified by the Catalog Number on the REL 352 chassis nameplate. The Catalog Number can be decoded by using Catalog Number ( see Section 3, pg. 3-26 ). Production Changes When engineering and production changes are made to the REL 352 equipment, a revision notation (Sub #) is reflected on the appropriate schematic diagram, and associated parts information.
  • Page 5 CONTENTS DISLAY MODULE POWER SUPPLY MODULE ANALOG INPUT MODULE ACCEPTANCE TESTS COMPUTER COMMUNICATIONS APPLICATION NOTES SYSTEM DIAGRAMS * Star next to section title indicates changes made within chapter since last issue Power Automation and Protection Division REL 352 Version 1.00...
  • Page 6 OST And OSB Logic Diagram - - - - - - - - - - - - - - - - - - - - - - - - - 3-24 REL 352 Backplate- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 4-12...
  • Page 7 Square Wave Duration 50 Hz - - - - - - - - - - - - - - - - - - - - - - - - - - K-5 REL 352 Block Diagram - - - - - - - - - - - - - - - - - - - - - - - - - - - - L-2...
  • Page 8 • Circuit – a complete function on a printed circuit board (e.g., analog-to-digital conversion) • The REL 352 relay assembly consists of an outer-chassis and an inner-chassis which slides into the outer-chassis. The REL 352 conforms to the following dimensions and weight (...

  • Page 9: Backplane

    Backplane module (via connector J4). Interconnect Module The Interconnect module ( ) becomes the floor of the REL 352 inner chassis; it see Appendix B provides electrical connections from and to all other modules: from the Backplane (at the rear),...

  • Page 10: Microprocessor

    Three different styles of power supply boards are required to accommodate the input voltage ranges listed below. The REL 352 relay is capable of continued operation during a 200 msec voltage dip from the dc battery input; the magnitude of this voltage dip is also shown below:...
  • Page 11 • Channel alarm (1 Form A) SELF-CHECKING SOFTWARE REL 352 continually monitors its ac input subsystems using multiple A/D converter calibration- check inputs, plus loss-of-potential and loss-of-current monitoring. Failures of the converter, or any problem in a single ac channel which unbalances nonfault inputs, trigger alarms. Self- checking software includes the following functions: a.
  • Page 12 A special PC software (WRELCOM RCP and OSCAR) program are available for obtaining or sending the setting information to the REL 352. The REL 352 front panel shows two fault events (last and previous faults), but with the remote communication, 16 fault events and 3 records of oscillographic data can be obtained and stored.
  • Page 13 Figure 1-1. REL 352 Front Panel...
  • Page 14 Figure 1-1a. REL 352 (Rear view)

  • Page 15: Display

    PONI BACKPLANE BD. XFMR OPTOISOLATED INPUT BD. RELAY OUTPUT BDS. INTERCONNECT BD. PROCESSOR BD. DISPLAY BD. Top View Figure 1-2. Layout of REL 352 Modules within Inner and Outer Chassis...
  • Page 17 ØA Trip Sub 99 Direction 1618C33 Figure 1-4. Block Diagram of REL 352 Relay...
  • Page 18 Power Automation and Protection Division I.L. 40-201.9 Section 2. REL 352 SPECIFICATIONS TECHNICAL Principle of Operation Phase Comparison, Single-Comparer and Dual Comparer using Low Speed Power Line Carrier (ON-OFF and FSK), Audio Tone and Microwave. Miscellaneous Nominal ac Voltage (VLN) at 60 Hz 69.3 V rms...
  • Page 19 — for local network communications using INCOM network CHASSIS DIMENSIONS AND WEIGHT Height 7" (177.8 mm) 4 Rack Units ( See Figure 2-1 Width 19" (482.6 mm) Depth 14" (356 mm) including terminal blocks Weight 38 lb. (17.5 kg) REL 352 Version 1.00...
  • Page 20 Fast Transient Voltage 4 kV, 10/100 ns Withstand (ANSI C37.90.1, IEC 255-22-4) EMI Field Strength Withstand 25 MHz-1GHz, 10V/m Withstand (ANSI C37.90.2) Electrostatic Discharge Tests (IEC 255-22-2, IEC, 801-Y) 8/12 kV test voltage. Emission Tests (EN 55022, Class A) REL 352 Version 1.00...
  • Page 21 (447.294) 17.610 (21.666) 0.853 (346.049) 13.624 (290.601) 11.441 (17.653) 0.695 (176.632) 6.954 (101.600) 4.000 .140 R (3.556) (37.516) 1.477 0.242 (6.147) 0.090 (2.286) (482.600) 19.000 Figure 2-1. REL 352 Outline Drawing...
  • Page 22 Hz) modulation such as Single-Side-Band (SSB) PLC, Audio Tone or analog microwave. The REL 352 is a high speed relaying system; suitable for application to any voltage level. Its principle of operation makes it ideal for short lines and tapped lines with a power transformer, where traditional distance protection fails.
  • Page 23 Power Automation and Protection Division COMPOSITE SEQUENCE FILTER PHASE COMPARISON Current only systems, like the REL 352, compare the currents measured at the terminals of the transmission line. In a phase comparison system, like the REL 352, the phase relationship de- termines whether the condition is internal or external.
  • Page 24 LP1, LN1, LP2 and LN2 signals delayed by the respective LDT1 or LDT2 settings. It is extreme- ly important that the settings reflect the true channel delays of the communications channel. The correct comparison of phases is totally dependent on the proper channel delay measure- ment. REL 352 Version 1.00...
  • Page 25 Power Automation and Protection Division PILOT TRIP LOGIC Figure 3-7 illustrates the decision logic for the REL 352. The comparison signal, COUT feeds into a 4 millisecond timer (supervised by FD2, fault detector signal explained later). For security purposes, to account for inaccuracies and transmission line charging current effects, a mini- mum width of the squarewave logic “1”...
  • Page 26 Phase reach setting in secondary ohms for SLGF. 7.4. Phase-to-Phase The Phase-to-Phase unit ( see Figure 3-12 ) responds to all forward Phase-to-Phase faults, and some phase-phase-to-ground faults. Expressions 5 and 6 are for operating and reference REL 352 Version 1.00...
  • Page 27 7.5. Zone 2 and Zone 3 Distance Relaying The optional back-up system in REL 352 consists of two zones of distance protection for both phase and ground faults. Each zone consists of four distance units that are able to detect all fault types. The impedance units are three-phase-to- Ground units (ag, bg and cg) and a Phase-to-Phase unit.
  • Page 28 Timer OST2 times the trip after an OST condition has been detected and the trajectory moves from point 2 to point 3 in Figure 3-16. When OST 2 times out a trip signal is sent if the REL 352 has been set to trip on the way in under out of step conditions.
  • Page 29 This logic is provided when the backup system is included in the relaying system. The simple logic (shown in Figure 3-13) will detect the loss of one or two current inputs. The output of this logic is only used to energize the failure alarm relay of REL 352. 8.3.
  • Page 30 (X, Y Any A, B, C phase) The algorithm has limitations, especially when REL 352 is being applied to lines with series ca- pacitors. The above equations represent the apparent impedance to the relay and do not ac- count for the presence of the series negative reactance. The user should account for this in the final estimate.
  • Page 31 1) “Normal Internal Fault” 2) “External Fault” Figure 3-1. REL 352 Phase Comparison, Fault Recognition...
  • Page 32 Power Automation and Protection Division I.L. 40-201.9 Symmetrical Component Filter IT = C Figure 3-2. Symmetrical Component Filter IKEY (Mark) (Space) Figure 3-3. REL 352 Version 1.00 3-11...
  • Page 33 I.L. 40-201.9 Power Automation and Protection Division Remote Local IKEY IKEY IKEY MARK POSITIVE TRIP COINCIDENCE SPACE NEGATIVE TRIP COINCIDENCE NOTE: For ON-OFF Power Line Carrier only negative half-cycle comparison is performed. Figure 3-4. Internal Fault 3-12 REL 352 Version 1.00...
  • Page 34 Power Automation and Protection Division I.L. 40-201.9 Remote Local IKey IKey MARK POSITIVE TRIP COINCIDENCE SPACE NEGATIVE TRIP COINCIDENCE NOTE: For ON-OFF Power Line Carrier only negative half-cycle comparison is performed. Figure 3-5. External Fault REL 352 Version 1.00 3-13...
  • Page 35 Fault Detector 2 Sequence LDT1 Network Filter IKEY, LP TERM LDT2 COMPARERS From Phase LN = – LP Currents CHOK “1” C0, C1, C2 IKEY LDT1 COMM TEST TERM LDT2 IKEY “0” To Channel CHOK “1” Transmitter 2 CDT SPACE 1 MARK 1 COMM “1”...
  • Page 36 STUB BUS TRIP LDT + 8 COMM COMPARISON PILOT TRIP TRIP OR COUT FD2T ARMT (PILOT TRIP) (2) These Timers are 20% longer for 50 Hz Figure 3-7. Pilot Trip Logic...
  • Page 37 I.L. 40-201.9 Power Automation and Protection Division Fault Detection Level Setting Figure 3-8. Fault Detector IACD IBCD ICCD IGCD VACD ∆V∆I VBCD VCCD ∆I (2) 20% Higher for 50 Hz Figure 3-9. Change Detector 3-16 REL 352 Version 1.00...
  • Page 38 Z GF ϒ Z GR Z GF : Forward Reach Setting Z GR : Reverse Reach Setting ϒ: Maximum Torque Angle Balance Point Sub 3 ESK00042 Figure 3-10. Mho Characteristics for Single Phase-to-Ground Fault Detection REL 352 Version 1.00 3-17...
  • Page 39 Power Automation and Protection Division ϒ Z GR Z P : Forward Reach Setting Z GR : Reverse Reach Setting ϒ: Maximum Torque Angle Balance Point Sub 5 ESK00043 Figure 3-11. Mho Characteristics for Three-Phase Fault Detection 3-18 REL 352 Version 1.00...
  • Page 40 Power Automation and Protection Division I.L. 40-201.9 Sub 1 9654A15 Figure 3-12. Mho Characteristics for Phase-to-Phase Fault Detection REL 352 Version 1.00 3-19...
  • Page 41 I.L. 40-201.9 Power Automation and Protection Division LOPB Sub 2 ESK00047 Figure 3-13. Loss of Potential and Loss of Current Block Logic 3-20 REL 352 Version 1.00...
  • Page 42 Load Restriction Sub 1 2420F06 Sheet 2 in part Figure 3-14. Zone 2 and Zone 3 Back-up System...
  • Page 43 I.L. 40-201.9 Power Automation and Protection Division Sub 1 2420F06 Sheet 2 in part Figure 3-15. Optional Directional Overcurrent Units 3-22 REL 352 Version 1.00...
  • Page 44 Power Automation and Protection Division I.L. 40-201.9 Sub 1 esk00257 Figure 3-16. Blinders for the Out-of-Step Logic REL 352 Version 1.00 3-23...
  • Page 45 Sub 1 2420F06 Sheet 2 in part Figure 3-17. OST and OSB Logic Diagram...
  • Page 46 Power Line carri- er, Audio Tone, etc. • Complete system including REL 352 and communication equipment, factory configured and tested. The system will be delivered in sepa- rate containers, the interconnecting wiring harness and installation instructions will be included.
  • Page 47 [F] = FT-14 SWITCHES [N] = NO FT-14 SWITCHES REMOTE COMMUNICATION DEVICE (DIGIT #9) [R] = RS-232C PONI [C] = INCOM PONI [B] = RS-232C W/IRG PORT PONI ADDITIONAL FEATURES (DIGIT #10) [G] = OSCILLOGRAPHIC DATA STORAGE 3-26 REL 352 Version 1.00...
  • Page 48 Telemetry (slow speed Direct Transfer Trip; contains no noise processing or channel logic; not recommended for line relaying application) No Logic (Transmitter only chassis) NA Not applicable to REL 352 Accessories * For 50 or 100 watt output, see separate information on the LPA, Linear Power Amplifier...
  • Page 49 LPA, Linear Power Amplifier TC-10B/TCF-10B Extender Board - - - - - Style #1353D70G01 ** Available in Transmitter/Receiver chassis only. TC-10B to KR mounting kit - - - - - - - - - - Style #1355D61G01 3-28 REL 352 Version 1.00...

  • Page 50: Power Supply

    SEPARATING THE INNER AND OUTERCHASSIS CAUTION It is recommended that the user of this equipment become acquainted with the information in these instructions before energizing the REL 352 and associated assemblies. Failure to observe this precaution may result in damage to the equipment.
  • Page 51 • 1 “value accepted” indicator • 5 display-select indicators When the “Relay-in-Service” LED illuminates, the REL 352 relay is in service, there is dc power to the relay and the relay has passed the self-check and self-test. The LED is turned “OFF” if the relay-in-service relay has at least one of the internal failures shown in the “Test”...
  • Page 52 ). For each settings function displayed, depress the “VALUE see Table 4-3 RAISE” or “VALUE LOWER” key in order to scroll thru the REL 352 values available for the par- ticular function. (Each value that appears, as each different function appears in the function field, is considered to be the “current value”...
  • Page 53 4.4. Test Mode Function The test display mode provides diagnostic and testing capabilities for REL 352. Relay status display, local delay time computation, and relay testing are among the functions provided. The test mode functions are listed in Table 4-1.
  • Page 54 Bit Pattern 0 0 0 1 1 0 0 0 Bit Number 7 6 5 4 3 2 1 0 HEX “Value” Field Display For reference, refer to Table 4-2 for the binary-to-hexadecimal conversion. REL 352 Version 1.00...
  • Page 55 Continually depress the “DISPLAY” key until the “TEST” LED is illuminated; then depress the “FUNCTION RAISE” or “FUNCTION LOWER” key until the word “STAT” appears in the FUNCTION FIELD. b. The VALUE FIELD will display the status of the relay in hexadecimal Format: REL 352 Version 1.00...

  • Page 56: Analog Input

    2. A zero value indicates that no self-test failure has occurred. A non-zero value in the low byte (bits 0 to 7) represents an REL 352 failure condition which enables the failure alarm, and dis- ables tripping. A non-zero value in the third character from the right (bits 8 to 11) indicate a self- test-warning, but does not disable tripping.
  • Page 57 Power Automation and Protection Division 4.4.3. Test Enable The TEST ENABLE signal on the REL 352 channel logic diagram is provided through the front panel TEST mode. When the TEST mode TEST or TLDT functions are selected, the TEST EN- ABLE signal on the REL 352 phase comparison logic diagram is active, otherwise it is disabled.
  • Page 58 If a user loses his assigned password, a new password can be installed by turning the REL 352 relay’s dc power supply “OFF” and then “ON”. REL 352 allows a change of password within the next 15 minutes, by using a default “PASSWORD”.
  • Page 59 10. TARGET (FAULT DATA) INFORMATION ® The REL 352 stores 16 sets of targets (fault data). All 16 sets are accessible through INCOM but only the two most recent sets of data are accessible from the front panel ( see Table 4-5 The first part of the fault data contains “Yes/No”...
  • Page 60 With the exception of checking to insure proper mating of connectors, or setting jumpers, the following procedures are normally not recommended. (If there is a problem with the REL 352, it should be returned to the factory. See PREFACE.) 14. DISASSEMBLY PROCEDURES a.
  • Page 61 Sub 13 1354D22 Sheet 10 of 10 Figure 4-1. REL 352 Backplate...
  • Page 62 Power Automation and Protection Division I.L. 40-201.9 TABLE 4-3. REL 352 SETTINGS (Sheet 1 of 2) VERS . . Software Version FREQ . . Rated Frequency Setting Selection RP . . Enable Readouts In Primary Values CTYP . . Current Transformer Type: 1A or 5A ct .
  • Page 63 I.L. 40-201.9 Power Automation and Protection Division TABLE 4-3. REL 352 SETTINGS (Sheet 2 of 2) DIRU . . Directional Unit selection . Medium Set Ground Current Pickup Value In Amps TOG . . Timer for Ground Overcurrent Unit . Zone 2 Phase Distance Setting In Ohms .
  • Page 64 1.500 0.001 ohms/DTYP DTYP MI/KM PANG XXXX GANG XXXX XXX.X BKUP IN/OUT LOPB YES/NO FDOP IN/OUT FDOG IN/OUT DIRU ZSEQ/NSEQ 2.0 X I 0.02 X I Amps XX.XX 0.1 X I XX.XX 0.10 9.99 0.01 REL 352 Version 1.00 4-15...
  • Page 65 The impedance settings are dependent upon the CTYP setting. The setting ranges shown are for a 5 A ct. The displayed setting range is multiplied by 5 if a 1 A ct is used (CTYP = 1). 4-16 REL 352 Version 1.00...
  • Page 66 Power Automation and Protection Division I.L. 40-201.9 TABLE 4-5. MONITORING FUNCTIONS FUNCTION DESCRIPTION FORMAT UNITS CHRX . REL 352 channel receive status ARM/CHTB CHTX. . REL 352 channel transmit status KEY IA . metered current magnitude . XXX.X . Amps ∠...
  • Page 67 XXX.X fault voltage magnitude XXX.X Volts ∠ fault voltage angle XXX.X fault voltage magnitude XXX.X Volts ∠ 3V 0 fault voltage angle XXX.X Pole Disagreement Trip, 3 Pole Tripping in Backup mode YES/NO 4-18 REL 352 Version 1.00...
  • Page 68 The impedance is dependent upon the CTYP setting. The internal impedance values are for a 5 A ct. The impedance value is multiplied by 5 if a 1 A ct is used (CTYP = 1). REL 352 Version 1.00 4-19...
  • Page 69 It is imperative that the proper selection of frequency is made prior to applica- tion of power system currents and voltage. Readout in Primary Values (RP) A “YES” setting enables the REL 352 system to display all the monitored voltages and currents in primary kAmperes and kVolts. Current Transformer Type (CTYP) This setting is used for load current monitoring, if the selection is to be displayed in primary kA- mperes or secondary amperes.
  • Page 70 — The REL 352 system detected the operation of either the TRGP or TRGG, phase or ground current trigger respectively (see below). • ∆V, ∆I — The REL 352 system has detected a fault in the system that may not even be within the protective zone of the relay The change detector occurs when current or voltage change between the corresponding data samples, spaced one power line cycle apart, exceeds 12.5%.
  • Page 71 For 3-terminal line TERM = 3 As seen on figure 3-6 the setting for TERM = 3 enables comparison of received signals S2 and M2 from the third terminal with local signals LN2 and LP2 respectively. REL 352 Version 1.00...
  • Page 72 — No Reclose Block for the system. This logic may be provided by exter- nal devices. • ALRB — Reclose block will be activated for all types of faults. 4.10 Unblock Logic Enable (UNBK) This setting is primarily for Power Line Carrier (PLC) applications. REL 352 Version 1.00...
  • Page 73 4.14 High Set Phase Overcurrent Unit (IPH) This unit is provided in the REL 352 system to supplement the phase comparison protection by providing a non-pilot direct trip capability for high current internal faults. The IPH unit should be set above the maximum expected external fault current with a security margin.
  • Page 74 Zone 2 and Zone 3 ground impedance units use this parameter for their operation. For Example: If the assumed zero sequence impedance of the line is Zl0 = 15 ohms at 80° then set GANG = 80. REL 352 Version 1.00...
  • Page 75 If TOG is being used it is also used for tripping after a time delay, TOG. It is measuring the ground return current or 3Io. It should be set above the maximum expected unbalance in the normal load current flow in the line. The recommended setting is IOM = 0.5 amps. REL 352 Version 1.00...
  • Page 76 The phase to phase unit in REL 352 has only a forward reach (ZP). This unit is inherently di- rectional and its characteristics, which are dependent on the source impedance. This implies that all phase to phase and some phase to phase to ground faults have a forward reach only determined by the phase to phase unit.
  • Page 77 Set Z2GF = 30 if the Zone 2 reach is 30 ohms at 75°. Reverse Zone 2 ground unit reach (Z2GR) Phase to ground units in REL 352 have been designed to have a definite reverse looking reach. This makes the phase to ground units non-directional.
  • Page 78 Phase comparison system is immune to system swings. When voltage inputs are part of the REL 352, blinders are provided for power swing detection. The Out of Step Trip (OST) logic is executed all the time regardless of the status of the channel. This means that OST is possible when the system is operating the phase comparison algorithm only.
  • Page 79 For Example: OSOT = 1600 msec TIME SETTINGS REL 352 has an internal clock for event time tagging purposes. Even if the unit has lost its pow- er supply the internal clock will continue running. REL 352 Version 1.00 5-11...
  • Page 80 To set the clock in the relay, set TIME = YES. The next fields are self explanatory: - Year YEAR - Month MNTH - Day - Day of the week WDAY - Hour HOUR - Minutes Enter the correct values as appropriate. 5-12 REL 352 Version 1.00...
  • Page 81 4 chokes (L1 thru L4) for dc power supply filter • surge-suppressor capacitors INCOM/PONI is supplied in two versions: • INCOM/PONI to RS232 computer interface (supplied as standard). • INCOM/PONI to INCOM network interface (supplied as option). REL 352 Version 1.00...
  • Page 82 Sub 7 1611C26 Figure A-1. REL 352 Backplane Module Component Location Diagram...
  • Page 83 Power Automation and Protection Division I.L. 40-201.9 Sub 1 1502B38 Figure A-2. REL 352 Backplane/Transformer Module PC Board. REL 352 Version 1.00...
  • Page 84 Sub 5 1612C22 Figure A-3. REL 352 Backplane/Transformer Module Schematic.
  • Page 85  JMP6 KEY OUT Related connections are shown below: Module Connector Destination J11, J12, J13 Backplane Power Supply Analog Input Microprocessor Relay Output (Single Pole Trip) Relay Output (Base 1) Relay Output (Base 2) Contact Input REL 352 Version 1.00...
  • Page 86 Sub 1 1618C45 Figure B-1. REL 352 Interconnect Module Component Location Diagram...
  • Page 87 Sub 1 1618C35 Figure B-2. REL 352 Interconnect Module Schematic...
  • Page 88 Sub 1 1618C35 Figure B-2. REL 352 Interconnect Module Schematic...
  • Page 89 Failure Alarm JB-8C Reed C1 — — JA-14AC/12AC BFIB-1 BFIA-1 RI1-1 JB-2C Trip C GS (Gen. Start) Failure Alarm JA-10AC/8AC BFIB-2 BFIA-2 Ri1-2 JB-4A BFIB BFIA JA-6AC/4AC BFIC-1 RB-1 RI2-1 JB-4C BFIC JA-2A/2C BFIC-2 RB-2 RI2-2 REL 352 Version 1.00...
  • Page 90 I.L. 40-201.9 Power Automation and Protection Division Sub 3 1611C27 Figure C-1. REL 352 Relay Output Module Component Location Diagram REL 352 Version 1.00...
  • Page 91 24V Relay 48V Relay 2.0 µF 1.0 µF 0.47 µF C1, 2, 3, 4 Q1, 2, 3, 4 VN2410M VN2410M ZVN0535R Sub 3 1611C36 Sheet 1 of 3 Figure C-2. REL 352 Relay Output Module Schematic. REL 352 Version 1.00...
  • Page 92 12V Relay 24V Relay 48V Relay 2.0 µF 1.0 µF 0.47 µF C1, 2, 4 Q1, 2, 3, 4 VN2410M VN2410M ZVN0535R Sub 3 1611C36 Sheet 2 of 3 Figure C-2. REL 352 Relay Output Module Schematic. REL 352 Version 1.00...
  • Page 93 12V Relay 24V Relay 48V Relay 2.0 µF 1.0 µF 0.47 µF C1, 2, 4 Q1, 2, 3, 4 VN2410M VN2410M ZVN0535R Sub 3 1611C36 Sheet 3 of 3 Figure C-2. REL 352 Relay Output Module Schematic REL 352 Version 1.00...
  • Page 94 Note: Position 1-2 is the factory setting. • Connector JA connects to the Backplane module and, via terminal block TB-5, to the exter- nal contacts. • Connector JB interfaces to the Microprocessor module via connector JB-4 (on the intercon- nect module). REL 352 Version 1.00...
  • Page 95 Sub 1 1618C38 Figure D-1. REL 352 Optoisolated Input Module Component Location Diagram...
  • Page 96 Power Automation and Protection Division I.L. 40-201.9 Sub 1 1618C36 Figure D-2. REL 352 Optoisolated Input Module Schematic Sheet 1 of 2 REL 352 Version 1.00...
  • Page 97 I.L. 40-201.9 Power Automation and Protection Division Sub 1 1618C36 Sheet 2 of 2 Figure D-2. REL 352 Optoisolated Input Module Schematic REL 352 Version 1.00...
  • Page 98 TASK ASSIGNMENT The processors perform the following major tasks: Processor 1 • Analog input sampling and Fourier computations • Operator interface • INCOM communications • Non-volatile data storage with 2-out-of-3 memory sampling (voting) REL 352 Version 1.00...
  • Page 99 Disable Display Saver 2-3* Enable Display Saver Spare, not used at this time“ “ “ “ “ P2 RAM 2kx8 2-3* P2 RAM 8kx8 or 32kx8 1-2* P2RAM 32kx8 P2 RAM 8kx8 or 2kx8 Factory Setting REL 352 Version 1.00...
  • Page 100 8k x 16 32k x 16 4/U39, U47 2/U7, U23 Contact Input Interface EEPROM φ 8k x 8 2/U26 Real-Time 5 V Regulator Power Supply φ Clock 2/U16 J3 +8.5V ESK00052 Figure E-1. Microprocessor Module Block Diagram REL 352 Version 1.00...
  • Page 101 8k EEPROM (8k x 8) 6000H 4000H 64k EPROM Program Memory (32k x 16) 100H 80C196 special Function Registers ESK00053 Figure E-2. REL 352 Processor 1 Memory Map FFFFH Memory Mapped I/0 F000H Dual Port RAM (2k x 16) E000H (4k x 16)
  • Page 102 Sub 4 1611C22 Sheet 3 of 3 Figure E-4. REL 352 Microprocessor Module Component Location Diagram...
  • Page 103 I.L. 40-201.9 Power Automation and Protection Division Sub 1 1612C18 Sheet 1 of 7 Figure E-5. REL 352 Microprocessor Module Schematic REL 352 Version 1.00...
  • Page 104 Sub 1 1612C18 Sheet 2 of 7 Figure E-5. REL 352 Microprocessor Module Schematic...
  • Page 105 I.L. 40-201.9 Power Automation and Protection Division Sub 1 1612C18 Sheet 3 of 7 Figure E-5. REL 352 Microprocessor Module Schematic REL 352 Version 1.00...
  • Page 106 Sub 1 1612C18 Sheet 4 of 7 Figure E-5. REL 352 Microprocessor Module Schematic...
  • Page 107 Sub 1 1612C18 Sheet 5 of 7 Figure E-5. REL 352 Microprocessor Module Schematic...
  • Page 108 Sub 1 1612C18 Sheet 6 of 7 Figure E-5. REL 352 Microprocessor Module Schematic...
  • Page 109 Sub 1 1612C18 Sheet 7 of 7 Figure E-5. REL 352 Microprocessor Module Schematic...
  • Page 110 Function U38-2 XMTR KEY U38-5 Not used U38-6 Not used U38-9 Not used U38-12 Not used U38-15 Not used U38-16 Not used U38-19 Not used U29-12 Not used U29-15 Not used DATAVAL U35-21 Not used REL 352 Version 1.00 E-13...
  • Page 111 TASK ASSIGNMENT The processors perform the following major tasks: Processor 1 • Analog input sampling and Fourier computations • Operator interface • INCOM communications • Non-volatile data storage with 2-out-of-3 memory sampling (voting) REL 352 Version 1.00...
  • Page 112 Disable Display Saver 2-3* Enable Display Saver Spare, not used at this time“ “ “ “ “ P2 RAM 2kx8 2-3* P2 RAM 8kx8 or 32kx8 1-2* P2RAM 32kx8 P2 RAM 8kx8 or 2kx8 Factory Setting REL 352 Version 1.00...
  • Page 113 8k x 16 32k x 16 4/U39, U47 2/U7, U23 Contact Input Interface EEPROM φ 8k x 8 2/U26 Real-Time 5 V Regulator Power Supply φ Clock 2/U16 J3 +8.5V ESK00052 Figure E-1. Microprocessor Module Block Diagram REL 352 Version 1.00...
  • Page 114 8k EEPROM (8k x 8) 6000H 4000H 64k EPROM Program Memory (32k x 16) 100H 80C196 special Function Registers ESK00053 Figure E-2. REL 352 Processor 1 Memory Map FFFFH Memory Mapped I/0 F000H Dual Port RAM (2k x 16) E000H (4k x 16)
  • Page 115 Sub 4 1611C22 Sheet 3 of 3 Figure E-4. REL 352 Microprocessor Module Component Location Diagram...
  • Page 116 I.L. 40-201.9 Power Automation and Protection Division Sub 1 1612C18 Sheet 1 of 7 Figure E-5. REL 352 Microprocessor Module Schematic REL 352 Version 1.00...
  • Page 117 Sub 1 1612C18 Sheet 2 of 7 Figure E-5. REL 352 Microprocessor Module Schematic...
  • Page 118 I.L. 40-201.9 Power Automation and Protection Division Sub 1 1612C18 Sheet 3 of 7 Figure E-5. REL 352 Microprocessor Module Schematic REL 352 Version 1.00...
  • Page 119 Sub 1 1612C18 Sheet 4 of 7 Figure E-5. REL 352 Microprocessor Module Schematic...
  • Page 120 Sub 1 1612C18 Sheet 5 of 7 Figure E-5. REL 352 Microprocessor Module Schematic...
  • Page 121 Sub 1 1612C18 Sheet 6 of 7 Figure E-5. REL 352 Microprocessor Module Schematic...
  • Page 122 Sub 1 1612C18 Sheet 7 of 7 Figure E-5. REL 352 Microprocessor Module Schematic...
  • Page 123 Function U38-2 XMTR KEY U38-5 Not used U38-6 Not used U38-9 Not used U38-12 Not used U38-15 Not used U38-16 Not used U38-19 Not used U29-12 Not used U29-15 Not used DATAVAL U35-21 Not used REL 352 Version 1.00 E-13...
  • Page 124 • Previous Fault (DS6) • Value Accepted (DS7) • Test (DS8) Test points (TP1 thru TP5) are used to monitor dc voltages: • -24V (TP1) • + 5V (TP2) • -12V (TP3) • +12V (TP4) • Common (TP5) REL 352 Version 1.00...
  • Page 125 Sub 4 1498B40 Sheet 7 of 7 Figure F-1. REL 352 Display Module Component Location Diagram...
  • Page 126 Sub 3 1608C93 Figure F-2. REL 352 Display Module Schematic...
  • Page 127 • +24 Vdc thru voltage doubler circuit C16, C19, D23, C18 and auctioneering diode D24 (to terminal J7/8A, 8C) • -24 Vdc thru voltage doubler circuit C17, D20, D25, C19 and auctioneering diode D22 (to terminal J7/6A, 6C) REL 352 Version 1.00...
  • Page 128 PRDC1 (Term. J7/16AC) 70.00Vdc PRDC1 (Term. J7/16AC) G02 and G03 26.00Vdc PRDC2 (Term. J7/18AC) 70.00Vdc PRDC2 (Term. J7/18AC) G02 and G03 NOTE: For proper operation of the auctioneered outputs, PRDC1 and PRDC2 should have identical values. REL 352 Version 1.00...
  • Page 129 Sub 1 1612C63 Sheet 12 Figure G-1. REL 352 Power Supply PC Board...
  • Page 131 - Y) path of U4 is selected (by U3.1 and U3.2), connecting the output of U2 (analog input with a gain of 8) to the A/D converter, performing a multiplication by 8 in the analog domain. NOTE: Adjust potentiometer (R59) for 5.000V at the test point (TP2) to ground. REL 352 Version 1.00...
  • Page 132 Filters 2/U7 To Voltage and Current 4/U16 Transformers via > + .5 V Interconnect Module Range Select Comp 3/U3.2 3/U5 < - .5 V Comp 3/U3.1 Autoranging Circuits ESK00055 Figure H-1. Analog Input Module Block Diagram REL 352 Version 1.00...
  • Page 133 Sub 4 1611C23 Sheet 3 of 3 Figure H-2. Analog Input Module Component Location Diagram...
  • Page 134 I.L. 40-201.9 Power Automation and Protection Division Sub 2 1612C20 Sheet 1 of 4 Figure H-3. Analog Input Module Schematic REL 352 Version 1.00...
  • Page 135 Power Automation and Protection Division I.L. 40-201.9 Sub 2 1612C20 Sheet 2 of 4 Figure H-3. Analog Input Module Schematic REL 352 Version 1.00...
  • Page 136 I.L. 40-201.9 Power Automation and Protection Division Sub 2 1612C20 Sheet 3 of 4 Figure H-3. Analog Input Module Schematic REL 352 Version 1.00...
  • Page 137 Power Automation and Protection Division I.L. 40-201.9 Sub 2 1612C20 Sheet 4 of 4 Figure H-3. Analog Input Module Schematic REL 352 Version 1.00...
  • Page 138 3.1. Current and voltage Inputs Connect the Relay Test System to REL 352 Relay, per application diagram 1618C33 (see SYSTEM DIA- GRAMS section). Please note that the Relay Test System Simulates Power System shown on 1618C33. Do not leave fault currents with trip relays energized for long periods of time.
  • Page 139 Using the procedure described in 4. 4.1.1 in Section 4, verify operation of relay output subsystem. The relay contact wiring is shown on Block Diagram 1618C33 System Diagrams section of this I.L. Please note that the Failure Alarm Relay (TB4, 5-6) has a normally closed contact. REL 352 Version 1.00...
  • Page 140 0.50 FDOG OST2 OST3 OSOT Step 2. Power the Unit Down Step 3. Make the following connections on the rear of REL 352: XMTR BAT (+) SPACE 1 (+) XMTR KEY (+) MARK 1 (+) CHAN FAIL 1 (+) XMTR RETURN (-)
  • Page 141 Connect terminal TB5-9 (Channel Failure) to battery (+). This generates channel failure state, disables phase comparison and activates distance backup system. Verify that in metering mode CHRX display reads CHTB. The following settings should be used: PANG GANG Z2GF BKUP Z2GR LOPB FDOP FDOG DIRU ZSEQ Z3GF Z3GR REL 352 Version 1.00...
  • Page 142 Vb = 69 ∠-120 Ib = 0 Vc = 69 ∠+120 1.5 ∠−105 Ic = 0 Va = 69 ∠0 Ia = 0 Vb = 10 ∠-120 Ib = 4∠-15 Vc = 69 ∠+120 1.5 ∠-105 Ic = 0 REL 352 Version 1.00...
  • Page 143 Ib = 2∠+165 Vc = 69 ∠+120 Ic = 0 Va = 69 ∠0 Ia = 0 Vb = 69 ∠-120 Ib = 0 Vc = 25 ∠+120 Ic = 2∠+45 The system should not trip. REL 352 Version 1.00...
  • Page 144 Vb = 35 ∠-120 Ib = 10∠-165 Vc = 35 ∠+120 Ic = 10∠+15 3.08∠75 Va = 35 ∠0 Ia = 10∠-105 Vb = 69 ∠-120 Ib = 0 Vc = 35 ∠+120 Ic = 10∠+75 3.08∠75 REL 352 Version 1.00...
  • Page 145 Ic = 5∠+75 6.16∠75 The REL 352 should trip and the tripping time should be 1.0 ±5% seconds. Zone 3 phase (Z3P) unit should op- erate for all of the above tests. For forward external faults apply the following quantities: Va = 35 ∠0...
  • Page 146 Vc = 35 ∠+120 Ic = 4∠-105 The REL 352 should not trip. Out of Step System Functional Tests For systems equipped with OST logic the following settings may be used to check the OST logic in REL 352: PANG GANG 11.0...
  • Page 147 Test #1 indicates the sequence of positions in the RX diagram to be applied and the time in cycles to hold the position and the action of the relay. TEST #1 Trip OST on the Way Out Time Trip Action 50-67 ms after 2 The fault impedance measured should be 10.6 ∠105 ohms. I-10 REL 352 Version 1.00...
  • Page 148 1.2. Communication Port Options REL 352 is supplied with a rear communications port. If the network interface is not specified, a RS-232C (hard- ware standard) communications port is supplied. Network interface comm. port option allows the connection of the relay with many other devices to a 2-wire network. A detailed discussion of networking capabilities can be found in AD 40-600, Substation Control and Communications Application Guide.
  • Page 149 Password: When the REL 352 is received from the factory or if the user loses the relay password, a new password can be assigned with the following procedure: Turn off the relay dc supply voltage for a few seconds, Restore the dc supply voltage and wait for the relay to complete the self check/start-up routine, Using RCP, perform the Password Menu choice “Set Relay Password”,...
  • Page 150 (several attempts), the communication equipment needs to be serviced. 1.7. SIXTEEN FAULT TARGET DATA The REL 352 saves the latest 16 fault records, but only the latest two fault records can be accessed from the front panel. For complete 16 fault data, the computer communication is necessary. 1.8.
  • Page 151 NOTE: Turn the power OFF and ON, anytime Dip Switch changes are made. OSCILLOGRAPHIC DATA DEFINITIONS The OSCAR program under selection “Load Screen Layout File” of the main menu and “REL 352" of the sub- menu offers the following display files: PHCOMP. 352 PHASE COMPARISON BACKUP BACKUP.352...
  • Page 152 Zone 3 trip (phase or ground after T3) TOG: Ground Overcurrent trip IOM: Medium set ground overcurrent unit operated LOP: Loss of potential detected (V0 and not IO) 2.3. R352ANA.352 , – 3I and 3V : Self Explanatory. REL 352 Version 1.00...
  • Page 153 TB1-3 NOISE CHAN FAIL 1 + NOTE 1: ALL VOLTAGE SELECTION JUMPERS IN REL 352 AND TCF 10B TO BE SET TO 15/20 V POSITION NOTE 2: +20 V ZENER REGULATOR INCLUDED WITH TCF 10B NOTE 3: WIRES 2, 11, 12 IN SHIELDED CABLE, CONNECT SHIELD TO TB4-10 OF REL 352...
  • Page 154 REL 352 must be in “Normal” position as shown on the diagram. If the channel failure input to REL 352 is intentionally not connected to data communication equipment (floating input) than JMP1 in normal position results in CF being false (logical “1”).
  • Page 155 LOCAL & REMOTE TCF-10B LOCAL REL 352 REMOTE REL 352 TCF-10B REL 352 IKEY OUT REMOTE IKEY INVERSION MARK 1 INPUT POLARITY OUTPUT FROM AND DELAY MARK 1 POLARITY uPROCESSOR OPTO-COUPLER INVERTED TCF KEY INVERSION INVERTED TCF MARK OUT INPUT...
  • Page 156 5A rms 60.1 0.65 5.59 0.75 5.37 5.15 I< t(r) >I 0.85 4.90 4.67 0.95 4.43 4.17 1.05 3.89 IKEY 3.61 1.15 2.96 1.25 2.58 2.15 1.35 0.75 Figure 3. Square Wave Duration - 60 Hz REL 352 Version 1.00...
  • Page 157 7.46 of 1A rms 7.21 0.65 6.96 0.75 6.44 6.17 I< t(r) >I 0.85 5.61 0.95 5.31 1.05 4.67 IKEY 4.33 1.15 3.95 3.55 1.25 2.58 1.35 1.93 Figure 4. Square Wave Duration - 50 Hz REL 352 Version 1.00...
  • Page 158 L-3 - - - - - - - - - - - - - - - - - - - - REL 352 Backup System Logic Diagram (sheet 2 of 2) - - - - - - - - -...
  • Page 159 ØA Trip Direction Figure L-1: REL 352 Block Diagram...
  • Page 160 (2) timers are 20% higher for 50Hz systems XOR DEFINITION INPUT 1 INPUT 2 OUTPUT TD296.OH sub 2 “0” – Logic 0 SYSTEM SETTINGS IN BOLD LETTERS Sheet 1 of 3 “1” – Logic 1 Figure L-2: REL 352 Logic Diagram...
  • Page 161 Opto Primary Power Input Supply Isolator Power Backup Power Stub Opto Input Supply Isolator Power Protection Opto Target Reset Target Reset Isolator FDOP OUT NONDIRECTIONAL IACD IAHT VACD FDOP A DIRECTIONAL FDOP OUT IBCD IBHT VBCD FDOP B HIGH SET OVERCURRENT FDOP OUT TRIP...
  • Page 162 STUB BUS TRIP LDT + 8 GENERAL COMM START COMPARISON PILOT TRIP CHANNEL CH ALARM TRIP OR ALARM COUT FD2T TRIP TRIP ALARM 2 CNT ARMT DC POWER OK FAILURE ALARM mP SELFCHECK OK BFI-1 BFI-2 TRIP BFI-3 BFI-4 TRIP SIGNAL TO ACTIVATE BACKUP SYSTEM BKUP...
  • Page 163 Sub 1 2420F06 (Sheet 2 of 2) Figure L-3: REL 352 Backup System Logic Diagram...