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Registers
Base Address: 0000D0
(1) Data register
SDAT
7
Address: D0
SD7
H
Initial Value
(X)
Note: R/W for I/O ports means the following:
Read: The data from the receive buffer is read. Read clears the DR bit in the
status register.
Write: Data are written to the transmit buffer.
(2) Line control register
LCR
7
Address: D1
SBRK
H
Read/Write
(R/W)
Initial Value
(0)
[Bit 7] SBRK: Send Break signal (start bit=0, databits=00
transmitted when this bit is set
[Bit 6] ETBEI: Enable Transmit Buffer Empty Interrupt. If this bit is set, the
interrupt INT1 is activated whenever the THRE bit of the LSR
register goes high.
[Bit 5] ERBEI: Enable Receive Buffer Full Interrupt. If this bit is set, the
interrupt INT1 is activated whenever the DR bit of the LSR
register goes high.
Note: When both ETBEI='0' and ERBEI='0', the INT1 pin will stay in high
impedance state with a 47k pullup connected to it.
(3) Line status register
LSR
7
Address: D2
TEMT
H
Read/Write
(R)
Initial Value
(1)
[Bit 7] TEMT: This bit is set when transmit register and transmit shift register
are empty. It can be cleared by writing data to the SDAT register.
[Bit 6] THRE: This bit is set when transmit register is empty. It can be cleared
by writing data to the SDAT register.
H
6
5
4
SD6
SD5
SD4
(X)
(X)
(X)
6
5
4
---
ETBEI
ERBEI
(R/W)
(R/W)
(---)
(0)
(0)
(---)
6
5
4
THRE
---
---
(R)
(---)
(---)
(1)
(---)
(---)
66
66
66
66
3
2
1
SD3
SD2
SD1
(X)
(X)
(X)
3
2
1
---
---
---
(---)
(---)
(---)
(---)
(---)
(---)
, stop bit=0) is
H
3
2
1
BI
FE
OE
(R)
(R)
(R)
(0)
(0)
(0)
0
SD0
(X)
0
---
(---)
(---)
0
DR
(R)
(0)
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