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K8-A/D connector
This connector provides an access to the A/D port signals of the CPU:
AVCC 1
AGND 3
AVR+ 5
ADTG 7
AN0 9
AN2 11
AN4 13
AN6 15
K11-FPGA User Programmable Pins
This connector allows an user to access the Xilinx user programmable
input/output pins. Its pinout is shown on the next figure:
UP10 11
UP12 13
UP14 15
UP16 17
UP18 19
VCC 21
UP20 23
UP22 25
UP24 27
UP26 29
UP28 31
UP30 33
UP32 35
UP34 37
UP36 39
2 AVCC
4 AGND
6 AVR+
8 AVR-
10 AN1
12 AN3
14 AN5
16 AN7
UP0 1
2 UP1
UP2 3
4 UP3-
UP4 5
6 UP5
UP6 7
8 UP7
UP8 9
10 UP9
12 UP11
14 UP13
16 UP15
18 UP17
20 UP19
22 GND
24 UP21
26 UP23
28 UP25
30 UP27
32 UP29
34 UP31
36 UP33
38 UP35
40 UP37
51
51
51
51
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