Lattice Semiconductor ECP5 Technical Notes page 68

Port
DQSR90
DQSW270
DQSW
RDPNTR[2:0]
WRPNTR[2:0]
DATAVALID
BURSTDET
Table 29. DQSBUFM Attributes
Attribute
DQS_LI_DEL_ADJ Sign bit for READ delay
adjustment, DDR input
DQS_LI_DEL_VA Value of delay for input
DDR.
DQS_LO_DEL_ADJ Sign bit for WRITE
delay adjustment, DDR
output
DQS_LO_DEL_VAL Value of delay for output
DDR.
1. Default value is set based on device characterization to achieve the 90 degree phase shift
Input and Output Memory DDR Primitives
The ECP5 and ECP5-5G device IDDR/ODDR modules support 4:1(2X) gearing mode that are used to implement
the memory functions.
Table 30 shows a summary of all the DDR memory primitives. See the sections below for detailed descriptions.
Table 30. Summary of all DDR Memory Primitives
DDR Memory DQ Input
DDR2
DDR3 IDDRX1DQA
DDR3L
LPDDR2
IDDRX2DQA
LPDDR3
IDDRX2DQA
Note: The D0 and D1 inputs are tied together. The D2 and D3 inputs are also tied together.
I/O
O 90° delay DQS used for read
O 90° delay clock used for DQ write
O Clock used for DQS write
O Read pointer for IFIFO module
O Write pointer for IFIFO module
O Signal indicating start of valid data
O Burst Detect indicator
Description
PLUS, MINUS
0 to 255(PLUS)
1 to 256 (MINUS)
PLUS, MINUS
0 to 255 (PLUS)
1 to 256 (MINUS)
DQ Output DQ Tristate
ODDRX2DQA TSHX2DQA
ODDRX2DQA TSHX2DQA
ODDRX2DQA TSHX2DQA
ECP5 and ECP5-5G High-Speed I/O Interface
Description
Values Default
PLUS
Note
PLUS
Note
DQS Output DQS Tristate
ODDRX2DQSB TSHX2DQSA
ODDRX2DQSB TSHX2DQSA
ODDRX2DQSB TSHX2DQSA
68
DQSBUF
All
1
All
All
1
All
Addr/Cmd Clock
ODDRX1F
CS_N: ODDRX2F
OSHX2A
ODDRX2DQA
CS_N & CKE: ODDRX2DQSA
1
ODDRX2DQA
ODDRX2DQA
CS_N, CKE &
ODDRX2DQSA
ODT:
1
ODDRX2DQA